/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// Generic clock generator 0 configuration
// Indicates whether generic clock 0 configuration is enabled or not
// enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// Generic Clock Generator Control
// Generic clock generator 0 source
// External Crystal Oscillator 0.4-32MHz (XOSC)
// Generic clock generator input pad
// Generic clock generator 1
// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// 32kHz External Crystal Oscillator (XOSC32K)
// 16MHz Internal Oscillator (OSC16M)
// Digital Frequency Locked Loop (DFLL48M)
// Fractional Digital Phase Locked Loop (FDPLL96M)
// This defines the clock source for generic clock generator 0
// gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M
#endif
// Run in Standby
// Indicates whether Run in Standby is enabled or not
// gclk_arch_gen_0_runstdby
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// Divide Selection
// Indicates whether Divide Selection is enabled or not
// gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// Output Enable
// Indicates whether Output Enable is enabled or not
// gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 0
#endif
// Output Off Value
// Indicates whether Output Off Value is enabled or not
// gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// Improve Duty Cycle
// Indicates whether Improve Duty Cycle is enabled or not
// gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// Generic Clock Generator Enable
// Indicates whether Generic Clock Generator Enable is enabled or not
// gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
//
// Generic Clock Generator Division
// Generic clock generator 0 division <0x0000-0xFFFF>
// gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
//
//
// Generic clock generator 1 configuration
// Indicates whether generic clock 1 configuration is enabled or not
// enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 0
#endif
// Generic Clock Generator Control
// Generic clock generator 1 source
// External Crystal Oscillator 0.4-32MHz (XOSC)
// Generic clock generator input pad
// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// 32kHz External Crystal Oscillator (XOSC32K)
// 16MHz Internal Oscillator (OSC16M)
// Digital Frequency Locked Loop (DFLL48M)
// Fractional Digital Phase Locked Loop (FDPLL96M)
// This defines the clock source for generic clock generator 1
// gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SOURCE
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// Run in Standby
// Indicates whether Run in Standby is enabled or not
// gclk_arch_gen_1_runstdby
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// Divide Selection
// Indicates whether Divide Selection is enabled or not
// gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// Output Enable
// Indicates whether Output Enable is enabled or not
// gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 0
#endif
// Output Off Value
// Indicates whether Output Off Value is enabled or not
// gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// Improve Duty Cycle
// Indicates whether Improve Duty Cycle is enabled or not
// gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// Generic Clock Generator Enable
// Indicates whether Generic Clock Generator Enable is enabled or not
// gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 0
#endif
//
// Generic Clock Generator Division
// Generic clock generator 1 division <0x0000-0xFFFF>
// gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1
#endif
//
//
// Generic clock generator 2 configuration
// Indicates whether generic clock 2 configuration is enabled or not
// enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 0
#endif
// Generic Clock Generator Control
// Generic clock generator 2 source
// External Crystal Oscillator 0.4-32MHz (XOSC)
// Generic clock generator input pad
// Generic clock generator 1
// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// 32kHz External Crystal Oscillator (XOSC32K)
// 16MHz Internal Oscillator (OSC16M)
// Digital Frequency Locked Loop (DFLL48M)
// Fractional Digital Phase Locked Loop (FDPLL96M)
// This defines the clock source for generic clock generator 2
// gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// Run in Standby
// Indicates whether Run in Standby is enabled or not
// gclk_arch_gen_2_runstdby
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// Divide Selection
// Indicates whether Divide Selection is enabled or not
// gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 0
#endif
// Output Enable
// Indicates whether Output Enable is enabled or not
// gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 0
#endif
// Output Off Value
// Indicates whether Output Off Value is enabled or not
// gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// Improve Duty Cycle
// Indicates whether Improve Duty Cycle is enabled or not
// gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// Generic Clock Generator Enable
// Indicates whether Generic Clock Generator Enable is enabled or not
// gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 0
#endif
//
// Generic Clock Generator Division
// Generic clock generator 2 division <0x0000-0xFFFF>
// gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 1
#endif
//
//
// Generic clock generator 3 configuration
// Indicates whether generic clock 3 configuration is enabled or not
// enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 1
#endif
// Generic Clock Generator Control
// Generic clock generator 3 source
// External Crystal Oscillator 0.4-32MHz (XOSC)
// Generic clock generator input pad
// Generic clock generator 1
// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// 32kHz External Crystal Oscillator (XOSC32K)
// 16MHz Internal Oscillator (OSC16M)
// Digital Frequency Locked Loop (DFLL48M)
// Fractional Digital Phase Locked Loop (FDPLL96M)
// This defines the clock source for generic clock generator 3
// gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
// Run in Standby
// Indicates whether Run in Standby is enabled or not
// gclk_arch_gen_3_runstdby
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 1
#endif
// Divide Selection
// Indicates whether Divide Selection is enabled or not
// gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// Output Enable
// Indicates whether Output Enable is enabled or not
// gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// Output Off Value
// Indicates whether Output Off Value is enabled or not
// gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// Improve Duty Cycle
// Indicates whether Improve Duty Cycle is enabled or not
// gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 1
#endif
// Generic Clock Generator Enable
// Indicates whether Generic Clock Generator Enable is enabled or not
// gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 1
#endif
//
// Generic Clock Generator Division
// Generic clock generator 3 division <0x0000-0xFFFF>
// gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
//
//
// Generic clock generator 4 configuration
// Indicates whether generic clock 4 configuration is enabled or not
// enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 0
#endif
// Generic Clock Generator Control
// Generic clock generator 4 source
// External Crystal Oscillator 0.4-32MHz (XOSC)
// Generic clock generator input pad
// Generic clock generator 1
// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// 32kHz External Crystal Oscillator (XOSC32K)
// 16MHz Internal Oscillator (OSC16M)
// Digital Frequency Locked Loop (DFLL48M)
// Fractional Digital Phase Locked Loop (FDPLL96M)
// This defines the clock source for generic clock generator 4
// gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// Run in Standby
// Indicates whether Run in Standby is enabled or not
// gclk_arch_gen_4_runstdby
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// Divide Selection
// Indicates whether Divide Selection is enabled or not
// gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// Output Enable
// Indicates whether Output Enable is enabled or not
// gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 0
#endif
// Output Off Value
// Indicates whether Output Off Value is enabled or not
// gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// Improve Duty Cycle
// Indicates whether Improve Duty Cycle is enabled or not
// gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// Generic Clock Generator Enable
// Indicates whether Generic Clock Generator Enable is enabled or not
// gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 0
#endif
//
// Generic Clock Generator Division
// Generic clock generator 4 division <0x0000-0xFFFF>
// gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
//
//
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H