1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
|
/**
* \file
*
* \brief SAM NVIC
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifdef _SAML22_NVIC_COMPONENT_
#ifndef _HRI_NVIC_L22_H_INCLUDED_
#define _HRI_NVIC_L22_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <hal_atomic.h>
#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
#else
#define NVIC_CRITICAL_SECTION_ENTER()
#define NVIC_CRITICAL_SECTION_LEAVE()
#endif
typedef uint32_t hri_nvic_icer_reg_t;
typedef uint32_t hri_nvic_icpr_reg_t;
typedef uint32_t hri_nvic_ipr_reg_t;
typedef uint32_t hri_nvic_iser_reg_t;
typedef uint32_t hri_nvic_ispr_reg_t;
static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ISER.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISER.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw)
{
return ((Nvic *)hw)->ISER.reg;
}
static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ICER.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICER.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw)
{
return ((Nvic *)hw)->ICER.reg;
}
static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ISPR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ISPR.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw)
{
return ((Nvic *)hw)->ISPR.reg;
}
static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->ICPR.reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->ICPR.reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw)
{
return ((Nvic *)hw)->ICPR.reg;
}
static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg |= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
uint32_t tmp;
tmp = ((Nvic *)hw)->IPR[index].reg;
tmp &= mask;
return tmp;
}
static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg = data;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg &= ~mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
{
NVIC_CRITICAL_SECTION_ENTER();
((Nvic *)hw)->IPR[index].reg ^= mask;
NVIC_CRITICAL_SECTION_LEAVE();
}
static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index)
{
return ((Nvic *)hw)->IPR[index].reg;
}
#ifdef __cplusplus
}
#endif
#endif /* _HRI_NVIC_L22_H_INCLUDED */
#endif /* _SAML22_NVIC_COMPONENT_ */
|
