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author | cpldcpu <cpldcpu@gmail.com> | 2015-06-15 02:08:41 +0200 |
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committer | cpldcpu <cpldcpu@gmail.com> | 2015-06-15 02:08:41 +0200 |
commit | c2c3125d000b34b7b828e364b43216069aea5878 (patch) | |
tree | b5f143b6b6b2eb9938bab07bce4c377389d64db6 /firmware/configuration/t167_default/bootloaderconfig.h | |
parent | 8bc91379aedd457e9186f6a87c3efe59c02d35f9 (diff) | |
download | micronucleus-c2c3125d000b34b7b828e364b43216069aea5878.tar.gz micronucleus-c2c3125d000b34b7b828e364b43216069aea5878.tar.bz2 micronucleus-c2c3125d000b34b7b828e364b43216069aea5878.zip |
firmware: Fix configuration for ATtiny1672.0b
Diffstat (limited to 'firmware/configuration/t167_default/bootloaderconfig.h')
-rw-r--r-- | firmware/configuration/t167_default/bootloaderconfig.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/firmware/configuration/t167_default/bootloaderconfig.h b/firmware/configuration/t167_default/bootloaderconfig.h index 8c29913..01890a7 100644 --- a/firmware/configuration/t167_default/bootloaderconfig.h +++ b/firmware/configuration/t167_default/bootloaderconfig.h @@ -4,14 +4,14 @@ * according to the hardware. * * Controller type: ATtiny 167 - 16 MHz with crystal - * Configuration: Standard configuration + * Configuration: Standard configuration - Follows Digispark Pro defaults * USB D- : PB3 - * USB D+ : PB4 + * USB D+ : PB6 * Entry : Always - * LED : None + * LED : Active High on PB1 * OSCCAL : No change due to external crystal * Note: Uses 16 MHz V-USB implementation. - * Last Change: Mar 16,2014 + * Last Change: JUn 15,2015 * * License: GNU GPL v2 (see License.txt */ @@ -33,7 +33,7 @@ /* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. * This may be any bit in the port. */ -#define USB_CFG_DPLUS_BIT 4 +#define USB_CFG_DPLUS_BIT 6 /* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. * This may be any bit in the port, but must be configured as a pin change interrupt. */ @@ -222,7 +222,7 @@ * */ -#define LED_MODE NONE +#define LED_MODE ACTIVE_HIGH #define LED_DDR DDRB #define LED_PORT PORTB |