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| author | marcoveeneman <marco-veeneman@hotmail.com> | 2015-03-17 21:42:17 +0100 |
|---|---|---|
| committer | marcoveeneman <marco-veeneman@hotmail.com> | 2015-03-17 21:42:17 +0100 |
| commit | 04d46184192b4a5d706fbf3eb1a8e286fcd60603 (patch) | |
| tree | c484ac4321935f970ee2857b763b4ea9b3997a29 /os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | |
| parent | 817efe19e0a913287726bf47cc75a22566908823 (diff) | |
| download | ChibiOS-Contrib-04d46184192b4a5d706fbf3eb1a8e286fcd60603.tar.gz ChibiOS-Contrib-04d46184192b4a5d706fbf3eb1a8e286fcd60603.tar.bz2 ChibiOS-Contrib-04d46184192b4a5d706fbf3eb1a8e286fcd60603.zip | |
Renamed Tiva GPIOA SSI pins to their function (RX, TX and CLK) in TI_TM4C123G_LAUNCHPAD board.h.
Diffstat (limited to 'os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h')
| -rw-r--r-- | os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h index f77501b..e8b7abd 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h @@ -92,10 +92,10 @@ */ #define GPIOA_UART0_RX 0 #define GPIOA_UART0_TX 1 -#define GPIOA_PIN2 2 +#define GPIOA_SSI0_CLK 2 #define GPIOA_PIN3 3 -#define GPIOA_PIN4 4 -#define GPIOA_PIN5 5 +#define GPIOA_SSI0_RX 4 +#define GPIOA_SSI0_TX 5 #define GPIOA_PIN6 6 #define GPIOA_PIN7 7 @@ -191,115 +191,115 @@ */ #define VAL_GPIOA_DATA (PIN_DATA_LOW(GPIOA_UART0_RX) | \ PIN_DATA_LOW(GPIOA_UART0_TX) | \ - PIN_DATA_LOW(GPIOA_PIN2) | \ + PIN_DATA_LOW(GPIOA_SSI0_CLK) | \ PIN_DATA_LOW(GPIOA_PIN3) | \ - PIN_DATA_LOW(GPIOA_PIN4) | \ - PIN_DATA_LOW(GPIOA_PIN5) | \ + PIN_DATA_LOW(GPIOA_SSI0_RX) | \ + PIN_DATA_LOW(GPIOA_SSI0_TX) | \ PIN_DATA_LOW(GPIOA_PIN6) | \ PIN_DATA_LOW(GPIOA_PIN7)) #define VAL_GPIOA_DIR (PIN_DIR_IN(GPIOA_UART0_RX) | \ PIN_DIR_IN(GPIOA_UART0_TX) | \ - PIN_DIR_IN(GPIOA_PIN2) | \ + PIN_DIR_IN(GPIOA_SSI0_CLK) | \ PIN_DIR_IN(GPIOA_PIN3) | \ - PIN_DIR_IN(GPIOA_PIN4) | \ - PIN_DIR_IN(GPIOA_PIN5) | \ + PIN_DIR_IN(GPIOA_SSI0_RX) | \ + PIN_DIR_IN(GPIOA_SSI0_TX) | \ PIN_DIR_IN(GPIOA_PIN6) | \ PIN_DIR_IN(GPIOA_PIN7)) #define VAL_GPIOA_AFSEL (PIN_AFSEL_GPIO(GPIOA_UART0_RX) | \ PIN_AFSEL_GPIO(GPIOA_UART0_TX) | \ - PIN_AFSEL_GPIO(GPIOA_PIN2) | \ + PIN_AFSEL_GPIO(GPIOA_SSI0_CLK) | \ PIN_AFSEL_GPIO(GPIOA_PIN3) | \ - PIN_AFSEL_GPIO(GPIOA_PIN4) | \ - PIN_AFSEL_GPIO(GPIOA_PIN5) | \ + PIN_AFSEL_GPIO(GPIOA_SSI0_RX) | \ + PIN_AFSEL_GPIO(GPIOA_SSI0_TX) | \ PIN_AFSEL_GPIO(GPIOA_PIN6) | \ PIN_AFSEL_GPIO(GPIOA_PIN7)) #define VAL_GPIOA_ODR (PIN_ODR_DISABLE(GPIOA_UART0_RX) | \ PIN_ODR_DISABLE(GPIOA_UART0_TX) | \ - PIN_ODR_DISABLE(GPIOA_PIN2) | \ + PIN_ODR_DISABLE(GPIOA_SSI0_CLK) | \ PIN_ODR_DISABLE(GPIOA_PIN3) | \ - PIN_ODR_DISABLE(GPIOA_PIN4) | \ - PIN_ODR_DISABLE(GPIOA_PIN5) | \ + PIN_ODR_DISABLE(GPIOA_SSI0_RX) | \ + PIN_ODR_DISABLE(GPIOA_SSI0_TX) | \ PIN_ODR_DISABLE(GPIOA_PIN6) | \ PIN_ODR_DISABLE(GPIOA_PIN7)) #define VAL_GPIOA_PUR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \ PIN_PxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_PxR_DISABLE(GPIOA_PIN2) | \ + PIN_PxR_DISABLE(GPIOA_SSI0_CLK) | \ PIN_PxR_DISABLE(GPIOA_PIN3) | \ - PIN_PxR_DISABLE(GPIOA_PIN4) | \ - PIN_PxR_DISABLE(GPIOA_PIN5) | \ + PIN_PxR_DISABLE(GPIOA_SSI0_RX) | \ + PIN_PxR_DISABLE(GPIOA_SSI0_TX) | \ PIN_PxR_DISABLE(GPIOA_PIN6) | \ PIN_PxR_DISABLE(GPIOA_PIN7)) #define VAL_GPIOA_PDR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \ PIN_PxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_PxR_DISABLE(GPIOA_PIN2) | \ + PIN_PxR_DISABLE(GPIOA_SSI0_CLK) | \ PIN_PxR_DISABLE(GPIOA_PIN3) | \ - PIN_PxR_DISABLE(GPIOA_PIN4) | \ - PIN_PxR_DISABLE(GPIOA_PIN5) | \ + PIN_PxR_DISABLE(GPIOA_SSI0_RX) | \ + PIN_PxR_DISABLE(GPIOA_SSI0_TX) | \ PIN_PxR_DISABLE(GPIOA_PIN6) | \ PIN_PxR_DISABLE(GPIOA_PIN7)) #define VAL_GPIOA_DEN (PIN_DEN_ENABLE(GPIOA_UART0_RX) | \ PIN_DEN_ENABLE(GPIOA_UART0_TX) | \ - PIN_DEN_ENABLE(GPIOA_PIN2) | \ + PIN_DEN_ENABLE(GPIOA_SSI0_CLK) | \ PIN_DEN_ENABLE(GPIOA_PIN3) | \ - PIN_DEN_ENABLE(GPIOA_PIN4) | \ - PIN_DEN_ENABLE(GPIOA_PIN5) | \ + PIN_DEN_ENABLE(GPIOA_SSI0_RX) | \ + PIN_DEN_ENABLE(GPIOA_SSI0_TX) | \ PIN_DEN_ENABLE(GPIOA_PIN6) | \ PIN_DEN_ENABLE(GPIOA_PIN7)) #define VAL_GPIOA_AMSEL (PIN_AMSEL_DISABLE(GPIOA_UART0_RX) | \ PIN_AMSEL_DISABLE(GPIOA_UART0_TX) | \ - PIN_AMSEL_DISABLE(GPIOA_PIN2) | \ + PIN_AMSEL_DISABLE(GPIOA_SSI0_CLK) | \ PIN_AMSEL_DISABLE(GPIOA_PIN3)) #define VAL_GPIOA_DR2R (PIN_DRxR_ENABLE(GPIOA_UART0_RX) | \ PIN_DRxR_ENABLE(GPIOA_UART0_TX) | \ - PIN_DRxR_ENABLE(GPIOA_PIN2) | \ + PIN_DRxR_ENABLE(GPIOA_SSI0_CLK) | \ PIN_DRxR_ENABLE(GPIOA_PIN3) | \ - PIN_DRxR_ENABLE(GPIOA_PIN4) | \ - PIN_DRxR_ENABLE(GPIOA_PIN5) | \ + PIN_DRxR_ENABLE(GPIOA_SSI0_RX) | \ + PIN_DRxR_ENABLE(GPIOA_SSI0_TX) | \ PIN_DRxR_ENABLE(GPIOA_PIN6) | \ PIN_DRxR_ENABLE(GPIOA_PIN7)) #define VAL_GPIOA_DR4R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \ PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_DRxR_DISABLE(GPIOA_PIN2) | \ + PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) | \ PIN_DRxR_DISABLE(GPIOA_PIN3) | \ - PIN_DRxR_DISABLE(GPIOA_PIN4) | \ - PIN_DRxR_DISABLE(GPIOA_PIN5) | \ + PIN_DRxR_DISABLE(GPIOA_SSI0_RX) | \ + PIN_DRxR_DISABLE(GPIOA_SSI0_TX) | \ PIN_DRxR_DISABLE(GPIOA_PIN6) | \ PIN_DRxR_DISABLE(GPIOA_PIN7)) #define VAL_GPIOA_DR8R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \ PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \ - PIN_DRxR_DISABLE(GPIOA_PIN2) | \ + PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) | \ PIN_DRxR_DISABLE(GPIOA_PIN3) | \ - PIN_DRxR_DISABLE(GPIOA_PIN4) | \ - PIN_DRxR_DISABLE(GPIOA_PIN5) | \ + PIN_DRxR_DISABLE(GPIOA_SSI0_RX) | \ + PIN_DRxR_DISABLE(GPIOA_SSI0_TX) | \ PIN_DRxR_DISABLE(GPIOA_PIN6) | \ PIN_DRxR_DISABLE(GPIOA_PIN7)) #define VAL_GPIOA_SLR (PIN_SLR_DISABLE(GPIOA_UART0_RX) | \ PIN_SLR_DISABLE(GPIOA_UART0_TX) | \ - PIN_SLR_DISABLE(GPIOA_PIN2) | \ + PIN_SLR_DISABLE(GPIOA_SSI0_CLK) | \ PIN_SLR_DISABLE(GPIOA_PIN3) | \ - PIN_SLR_DISABLE(GPIOA_PIN4) | \ - PIN_SLR_DISABLE(GPIOA_PIN5) | \ + PIN_SLR_DISABLE(GPIOA_SSI0_RX) | \ + PIN_SLR_DISABLE(GPIOA_SSI0_TX) | \ PIN_SLR_DISABLE(GPIOA_PIN6) | \ PIN_SLR_DISABLE(GPIOA_PIN7)) #define VAL_GPIOA_PCTL (PIN_PCTL_MODE(GPIOA_UART0_RX, 0) | \ PIN_PCTL_MODE(GPIOA_UART0_TX, 0) | \ - PIN_PCTL_MODE(GPIOA_PIN2, 0) | \ + PIN_PCTL_MODE(GPIOA_SSI0_CLK, 0) | \ PIN_PCTL_MODE(GPIOA_PIN3, 0) | \ - PIN_PCTL_MODE(GPIOA_PIN4, 0) | \ - PIN_PCTL_MODE(GPIOA_PIN5, 0) | \ + PIN_PCTL_MODE(GPIOA_SSI0_RX, 0) | \ + PIN_PCTL_MODE(GPIOA_SSI0_TX, 0) | \ PIN_PCTL_MODE(GPIOA_PIN6, 0) | \ PIN_PCTL_MODE(GPIOA_PIN7, 0)) |