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authorRomain Reignier <rom.reignier@gmail.com>2018-03-11 22:13:06 +0100
committerRomain Reignier <rom.reignier@gmail.com>2018-03-12 21:20:07 +0100
commit918149d48d908cf8441cbd41571b768918a4d7b1 (patch)
tree5a76a68ddef2d04c15e2fcc3d9b3e9f8802056ab /os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
parentaa8c6cc4af857cdb3e7f4813cf7a22ebf5333818 (diff)
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hal: stm32: Keep track of latest STM32 RCC API
RCC API changed in 01/2018 so apply the changes. Note that ae7a4d40b84d8afc999691577210696f16e682f6 partially fixed the changes in QEI module but some were missing. So update the other modules too.
Diffstat (limited to 'os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c')
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index cef015e..e07b946 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -157,38 +157,38 @@ void qei_lld_start(QEIDriver *qeip) {
/* Clock activation and timer reset.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccEnableTIM1();
+ rccEnableTIM1(FALSE);
rccResetTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccEnableTIM2();
+ rccEnableTIM2(FALSE);
rccResetTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccEnableTIM3();
+ rccEnableTIM3(FALSE);
rccResetTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccEnableTIM4();
+ rccEnableTIM4(FALSE);
rccResetTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccEnableTIM5();
+ rccEnableTIM5(FALSE);
rccResetTIM5();
}
#endif
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccEnableTIM8();
+ rccEnableTIM8(FALSE);
rccResetTIM8();
}
#endif