Merge branch 'master' of github.com:ChibiOS/ChibiOS-Contrib

2 files changed, 17 insertions, 60 deletions

diff --git a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
index 9f122b2..bb379cb 100644
--- a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
+++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c
@@ -75,8 +75,8 @@ OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER)
 
   /* TODO Do we need to halt the system on a DMA error?*/
 
-  if (UDMA->ERRCLR) {
-    UDMA->ERRCLR = 1;
+  if (HWREG(UDMA_ERRCLR)) {
+    HWREG(UDMA_ERRCLR) = 1;
   }
 
   OSAL_IRQ_EPILOGUE();
@@ -96,18 +96,18 @@ void udmaInit(void)
   udma_channel_mask = 0;
 
   /* Enable UDMA module.*/
-  SYSCTL->RCGCDMA = 1;
-  while (!(SYSCTL->PRDMA & (1 << 0)))
+  HWREG(SYSCTL_RCGCDMA) = 1;
+  while (!(HWREG(SYSCTL_PRDMA) & (1 << 0)))
     ;
 
   nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY);
   nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY);
 
   /* Enable UDMA controller.*/
-  UDMA->CFG = 1;
+  HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
 
   /* Set address of control table.*/
-  UDMA->CTLBASE = (uint32_t)udmaControlTable.primary;
+  HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary;
 }
 
 /**
diff --git a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
index 6479b08..0157277 100644
--- a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
+++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h
@@ -22,52 +22,9 @@
 /*===========================================================================*/
 
 /**
- * @name    CHCTL register defines.
- * @{
+ * @brief   CHCTL XFERSIZE helper.
  */
-#define UDMA_CHCTL_DSTINC_MASK          0xC0000000
-#define UDMA_CHCTL_DSTINC_0             0xC0000000
-#define UDMA_CHCTL_DSTINC_8             0x00000000
-#define UDMA_CHCTL_DSTINC_16            0x40000000
-#define UDMA_CHCTL_DSTINC_32            0x80000000
-#define UDMA_CHCTL_DSTSIZE_MASK         0x30000000
-#define UDMA_CHCTL_DSTSIZE_8            0x00000000
-#define UDMA_CHCTL_DSTSIZE_16           0x10000000
-#define UDMA_CHCTL_DSTSIZE_32           0x20000000
-#define UDMA_CHCTL_SRCINC_MASK          0x0C000000
-#define UDMA_CHCTL_SRCINC_0             0x0C000000
-#define UDMA_CHCTL_SRCINC_8             0x00000000
-#define UDMA_CHCTL_SRCINC_16            0x04000000
-#define UDMA_CHCTL_SRCINC_32            0x08000000
-#define UDMA_CHCTL_SRCSIZE_MASK         0x03000000
-#define UDMA_CHCTL_SRCSIZE_8            0x00000000
-#define UDMA_CHCTL_SRCSIZE_16           0x01000000
-#define UDMA_CHCTL_SRCSIZE_32           0x02000000
-#define UDMA_CHCTL_ARBSIZE_MASK         0x0003C000
-#define UDMA_CHCTL_ARBSIZE_1            0x00000000
-#define UDMA_CHCTL_ARBSIZE_2            0x00004000
-#define UDMA_CHCTL_ARBSIZE_4            0x00008000
-#define UDMA_CHCTL_ARBSIZE_8            0x0000C000
-#define UDMA_CHCTL_ARBSIZE_16           0x00010000
-#define UDMA_CHCTL_ARBSIZE_32           0x00014000
-#define UDMA_CHCTL_ARBSIZE_64           0x00018000
-#define UDMA_CHCTL_ARBSIZE_128          0x0001C000
-#define UDMA_CHCTL_ARBSIZE_256          0x00020000
-#define UDMA_CHCTL_ARBSIZE_512          0x00024000
-#define UDMA_CHCTL_ARBSIZE_1024         0x00028000
-#define UDMA_CHCTL_XFERSIZE_MASK        0x00003FF0
 #define UDMA_CHCTL_XFERSIZE(n)          ((n-1) << 4)
-#define UDMA_CHCTL_NXTUSEBURST          0x00000008
-#define UDMA_CHCTL_XFERMODE_MASK        0x00000007
-#define UDMA_CHCTL_XFERMODE_STOP        0x00000000
-#define UDMA_CHCTL_XFERMODE_BASIC       0x00000001
-#define UDMA_CHCTL_XFERMODE_AUTO        0x00000002
-#define UDMA_CHCTL_XFERMODE_PINGPONG    0x00000003
-#define UDMA_CHCTL_XFERMODE_MSG         0x00000004
-#define UDMA_CHCTL_XFERMODE_AMSG        0x00000005
-#define UDMA_CHCTL_XFERMODE_PSG         0x00000006
-#define UDMA_CHCTL_XFERMODE_APSG        0x00000007
-/** @} */
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -137,43 +94,43 @@ typedef struct __attribute__((packed, aligned(1024)))
 /*===========================================================================*/
 
 #define dmaChannelEnable(dmach) {\
-  UDMA->ENASET = (1 << dmach);\
+  HWREG(UDMA_ENASET) = (1 << dmach);\
 }
 
 #define dmaChannelDisable(dmach) { \
-  UDMA->ENACLR = (1 << dmach); \
+  HWREG(UDMA_ENACLR) = (1 << dmach); \
 }
 
 #define dmaChannelPrimary(dmach) {\
-  UDMA->ALTCLR = (1 << dmach); \
+  HWREG(UDMA_ALTCLR) = (1 << dmach); \
 }
 
 #define dmaChannelAlternate(dmach) { \
-  UDMA->ALTSET = (1 << dmach); \
+  HWREG(UDMA_ALTSET) = (1 << dmach); \
 }
 
 #define dmaChannelSingleBurst(dmach) { \
-  UDMA->USEBURSTCLR = (1 << dmach); \
+  HWREG(UDMA_USEBURSTCLR) = (1 << dmach); \
 }
 
 #define dmaChannelBurstOnly(dmach) { \
-  UDMA->USEBURSTSET = (1 << dmach); \
+  HWREG(UDMA_USEBURSTSET) = (1 << dmach); \
 }
 
 #define dmaChannelPriorityHigh(dmach) { \
-  UDMA->PRIOSET = (1 << dmach); \
+  HWREG(UDMA_PRIOSET) = (1 << dmach); \
 }
 
 #define dmaChannelPriorityDefault(dmach) { \
-  UDMA->PRIOCLR = (1 << dmach); \
+  HWREG(UDMA_PRIOCLR) = (1 << dmach); \
 }
 
 #define dmaChannelEnableRequest(dmach) {\
-  UDMA->REQMASKCLR = (1 << dmach); \
+  HWREG(UDMA_REQMASKCLR) = (1 << dmach); \
 }
 
 #define dmaChannelDisableRequest(dmach) {\
-  UDMA->REQMASKSET = (1 << dmach); \
+  HWREG(UDMA_REQMASKSET) = (1 << dmach); \
 }
 
 /*===========================================================================*/