diff options
| author | marcoveeneman <marco-veeneman@hotmail.com> | 2016-08-24 20:43:29 +0200 |
|---|---|---|
| committer | marcoveeneman <marco-veeneman@hotmail.com> | 2016-08-24 20:43:29 +0200 |
| commit | 220619763ef2479a4e795bdd4f034d1e90acbc3d (patch) | |
| tree | 9f38484c436818db7ae34195df3dbcbd23577d66 /os/hal/ports/TIVA/TM4C123x/hal_lld.c | |
| parent | 99a7c1518c8753b1f0a4acdccc9b7d402854f7d3 (diff) | |
| download | ChibiOS-Contrib-220619763ef2479a4e795bdd4f034d1e90acbc3d.tar.gz ChibiOS-Contrib-220619763ef2479a4e795bdd4f034d1e90acbc3d.tar.bz2 ChibiOS-Contrib-220619763ef2479a4e795bdd4f034d1e90acbc3d.zip | |
Updated hal_lld.c files to use the new TivaWare macros.
Diffstat (limited to 'os/hal/ports/TIVA/TM4C123x/hal_lld.c')
| -rw-r--r-- | os/hal/ports/TIVA/TM4C123x/hal_lld.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c index ddcddb3..de131b1 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c @@ -76,8 +76,8 @@ void tiva_clock_init(void) * PLL. */ /* read */ - rcc = SYSCTL->RCC; - rcc2 = SYSCTL->RCC2; + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); /* modify */ rcc |= TIVA_RCC_BYPASS; @@ -85,8 +85,8 @@ void tiva_clock_init(void) rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2; /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically @@ -99,8 +99,8 @@ void tiva_clock_init(void) rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; for(i = 100000; i; i--); /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the @@ -113,23 +113,23 @@ void tiva_clock_init(void) rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw * Interrupt Status (RIS) register. */ - while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0); + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ rcc &= ~TIVA_RCC_BYPASS; rcc2 &= ~TIVA_RCC2_BYPASS2; rcc |= (TIVA_BYPASS_VALUE << 11); rcc2 |= (TIVA_BYPASS_VALUE << 11); - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; #if HAL_USE_PWM - SYSCTL->RCC |= TIVA_PWM_FIELDS; + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; #endif #if defined(TIVA_UDMA_REQUIRED) |