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| author | Diego Ismirlian <dismirlian (at) google's mail.com> | 2018-08-20 20:50:22 -0300 |
|---|---|---|
| committer | Diego Ismirlian <dismirlian (at) google's mail.com> | 2018-08-20 20:50:22 -0300 |
| commit | 0936be2541015b384b00e31ece7f42a510511aaa (patch) | |
| tree | b374d386e02aff0559457d11db61c96567a1fc50 /os/hal | |
| parent | 03615f40dc3d1cbb5354035c326963b49759f440 (diff) | |
| parent | fe95e90b80a28dd2f40bfee1ad90822b99519c6a (diff) | |
| download | ChibiOS-Contrib-0936be2541015b384b00e31ece7f42a510511aaa.tar.gz ChibiOS-Contrib-0936be2541015b384b00e31ece7f42a510511aaa.tar.bz2 ChibiOS-Contrib-0936be2541015b384b00e31ece7f42a510511aaa.zip | |
Merge branch 'master' of https://github.com/ChibiOS/ChibiOS-Contrib
Diffstat (limited to 'os/hal')
68 files changed, 8907 insertions, 1908 deletions
diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c index e6c6080..09b44f7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c @@ -14,45 +14,197 @@ limitations under the License. */ -#include "ch.h" #include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; -#if HAL_USE_PAL || defined(__DOXYGEN__) /** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. + * @brief STM32 GPIO static initialization data. */ -const PALConfig pal_default_config = -{ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif }; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); #endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ /** * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. + * @details GPIO ports and system clocks are initialized before everything + * else. */ void __early_init(void) { + stm32_gpio_init(); stm32_clock_init(); } @@ -60,21 +212,21 @@ void __early_init(void) { /** * @brief SDC card detection. */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief SDC card write protection detection. */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif /* HAL_USE_SDC */ @@ -82,21 +234,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { /** * @brief MMC_SPI card detection. */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief MMC_SPI card write protection detection. */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif @@ -105,4 +257,5 @@ bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any. */ void boardInit(void) { + } diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.c b/os/hal/boards/PJRC_TEENSY_3_5/board.c new file mode 100644 index 0000000..e93e11d --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_5/board.c @@ -0,0 +1,218 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+ Copyright (C) 2017 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+
+#define SOME_GPIO PAL_MODE_INPUT_PULLUP
+
+const PALConfig pal_default_config =
+{
+ .ports = {
+ {
+ /*
+ * PORTA setup.
+ *
+ * PTA0 -PTA3 -- bootloading coprocessor
+ * PTA5 -- PIN25
+ * PTA12-PTA13 -- PIN3-PIN4
+ * PTA14-PTA16 -- PIN26-PIN28
+ * PTA17 -- PIN39 / A20
+ * PTA26 -- PIN42
+ * PTA28 -- PIN40
+ * PTA29 -- PIN41
+ *
+ * PTA18/19 crystal
+ */
+ .port = IOPORT1,
+ .pads = {
+ /* PTA0-PTA3 -- bootloading coprocessor */
+ PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_7,
+
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_OUTPUT_PUSHPULL, /* PIN25 */
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, /* PIN3 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* PIN4 */
+ PAL_MODE_OUTPUT_PUSHPULL, /* PIN26 */
+ PAL_MODE_UNCONNECTED, /* PIN27 */
+ PAL_MODE_UNCONNECTED, /* PIN28 */
+ PAL_MODE_UNCONNECTED, /* PIN39 */
+ PAL_MODE_INPUT_ANALOG, /* XTAL0 */
+ PAL_MODE_INPUT_ANALOG, /* XTAL0 */
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, /* PIN42 */
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, /* PIN40 */
+ PAL_MODE_UNCONNECTED, /* PIN41 */
+ PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTB setup.
+ *
+ * PTB0 - PIN16
+ * PTB1 - PIN17
+ * PTB2 - PIN19
+ * PTB3 - PIN18
+ * PTB10 - PIN31
+ * PTB11 - PIN32
+ * PTB16 - PIN0 - UART0_TX
+ * PTB17 - PIN1 - UART0_RX
+ * PTB18 - PIN32
+ * PTB19 - PIN25
+ */
+ .port = IOPORT2,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, SOME_GPIO, SOME_GPIO,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, SOME_GPIO, SOME_GPIO,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, SOME_GPIO,
+ SOME_GPIO, SOME_GPIO, SOME_GPIO,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTC setup.
+ *
+ * PTC0 - PIN15
+ * PTC1 - PIN22
+ * PTC2 - PIN23
+ * PTC3 - PIN9
+ * PTC4 - PIN10
+ * PTC5 - PIN13
+ * PTC6 - PIN11
+ * PTC7 - PIN12
+ * PTC8 - PIN35
+ * PTC9 - PIN36
+ * PTC10 - PIN37
+ * PTC11 - PIN38
+ */
+ .port = IOPORT3,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTD setup.
+ *
+ * PTD0 - PIN2
+ * PTD1 - PIN14
+ * PTD2 - PIN7
+ * PTD3 - PIN8
+ * PTD4 - PIN6
+ * PTD5 - PIN20
+ * PTD6 - PIN21
+ * PTD7 - PIN5
+ */
+ .port = IOPORT4,
+ .pads = {
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, SOME_GPIO,
+ PAL_MODE_UNCONNECTED, SOME_GPIO, SOME_GPIO,
+ SOME_GPIO, SOME_GPIO, SOME_GPIO,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ {
+ /*
+ * PORTE setup.
+ *
+ * PTE0 - PTE5 -- SDHC slot
+ * PTE6 -- USB OTG power switch (Teensy3.6 only)
+ * PTE10 - PIN56
+ * PTE11 - PIN57
+ * PTE24 - PIN33
+ * PTE25 - PIN34
+ * PTE26 - PIN24
+ */
+ .port = IOPORT5,
+ .pads = {
+ PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4,
+ PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED,
+ },
+ },
+ },
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ k60x_clock_init();
+}
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.h b/os/hal/boards/PJRC_TEENSY_3_5/board.h new file mode 100644 index 0000000..cd33874 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_5/board.h @@ -0,0 +1,242 @@ +/*
+ ChibiOS - Copyright (C) 2017 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy 3.5 board.
+ */
+
+/*
+ * Board identifier
+ */
+#define BOARD_PJRC_TEENSY_3_5
+#define BOARD_NAME "PJRC Teensy 3.5"
+
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY 16000000UL
+
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+
+/*
+ * MCU type
+ */
+#define K64FX512
+
+/*
+ * IO pin assignments
+ */
+#define TEENSY_PIN25 5
+#define TEENSY_PIN3 12
+#define TEENSY_PIN4 13
+#define TEENSY_PIN26 14
+#define TEENSY_PIN27 15
+#define TEENSY_PIN28 16
+#define TEENSY_PIN39 17
+#define TEENSY_PIN42 26
+#define TEENSY_PIN40 28
+#define TEENSY_PIN41 29
+
+#define TEENSY_PIN25_IOPORT IOPORT1
+#define TEENSY_PIN3_IOPORT IOPORT1
+#define TEENSY_PIN4_IOPORT IOPORT1
+#define TEENSY_PIN26_IOPORT IOPORT1
+#define TEENSY_PIN27_IOPORT IOPORT1
+#define TEENSY_PIN28_IOPORT IOPORT1
+#define TEENSY_PIN39_IOPORT IOPORT1
+#define TEENSY_PIN42_IOPORT IOPORT1
+#define TEENSY_PIN40_IOPORT IOPORT1
+#define TEENSY_PIN41_IOPORT IOPORT1
+
+#define TEENSY_PIN16 0
+#define TEENSY_PIN17 1
+#define TEENSY_PIN19 2
+#define TEENSY_PIN18 3
+#define TEENSY_PIN49 4
+#define TEENSY_PIN50 5
+#define TEENSY_PIN31 10
+#define TEENSY_PIN32 11
+#define TEENSY_PIN0 16
+#define TEENSY_PIN1 17
+#define TEENSY_PIN29 18
+#define TEENSY_PIN30 19
+#define TEENSY_PIN43 20
+#define TEENSY_PIN46 21
+#define TEENSY_PIN44 22
+#define TEENSY_PIN45 23
+
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN49_IOPORT IOPORT2
+#define TEENSY_PIN50_IOPORT IOPORT2
+#define TEENSY_PIN31_IOPORT IOPORT2
+#define TEENSY_PIN32_IOPORT IOPORT2
+#define TEENSY_PIN0_IOPORT IOPORT2
+#define TEENSY_PIN1_IOPORT IOPORT2
+#define TEENSY_PIN29_IOPORT IOPORT2
+#define TEENSY_PIN30_IOPORT IOPORT2
+#define TEENSY_PIN43_IOPORT IOPORT2
+#define TEENSY_PIN46_IOPORT IOPORT2
+#define TEENSY_PIN44_IOPORT IOPORT2
+#define TEENSY_PIN45_IOPORT IOPORT2
+
+#define TEENSY_PIN15 0
+#define TEENSY_PIN22 1
+#define TEENSY_PIN23 2
+#define TEENSY_PIN9 3
+#define TEENSY_PIN10 4
+#define TEENSY_PIN13 5
+#define TEENSY_PIN11 6
+#define TEENSY_PIN12 7
+#define TEENSY_PIN35 8
+#define TEENSY_PIN36 9
+#define TEENSY_PIN37 10
+#define TEENSY_PIN38 11
+
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+#define TEENSY_PIN9_IOPORT IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN35_IOPORT IOPORT3
+#define TEENSY_PIN36_IOPORT IOPORT3
+#define TEENSY_PIN37_IOPORT IOPORT3
+#define TEENSY_PIN38_IOPORT IOPORT3
+
+#define TEENSY_PIN2 0
+#define TEENSY_PIN14 1
+#define TEENSY_PIN7 2
+#define TEENSY_PIN8 3
+#define TEENSY_PIN6 4
+#define TEENSY_PIN20 5
+#define TEENSY_PIN21 6
+#define TEENSY_PIN5 7
+#define TEENSY_PIN47 8
+#define TEENSY_PIN48 9
+#define TEENSY_PIN55 11
+#define TEENSY_PIN53 12
+#define TEENSY_PIN52 13
+#define TEENSY_PIN51 14
+#define TEENSY_PIN54 15
+
+#define TEENSY_PIN2_IOPORT IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN7_IOPORT IOPORT4
+#define TEENSY_PIN8_IOPORT IOPORT4
+#define TEENSY_PIN6_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+#define TEENSY_PIN5_IOPORT IOPORT4
+#define TEENSY_PIN47_IOPORT IOPORT4
+#define TEENSY_PIN48_IOPORT IOPORT4
+#define TEENSY_PIN55_IOPORT IOPORT4
+#define TEENSY_PIN53_IOPORT IOPORT4
+#define TEENSY_PIN52_IOPORT IOPORT4
+#define TEENSY_PIN51_IOPORT IOPORT4
+#define TEENSY_PIN54_IOPORT IOPORT4
+
+#define TEENSY_PIN56 10
+#define TEENSY_PIN57 11
+#define TEENSY_PIN33 24
+#define TEENSY_PIN34 25
+#define TEENSY_PIN24 26
+
+#define TEENSY_PIN56_IOPORT IOPORT5
+#define TEENSY_PIN57_IOPORT IOPORT5
+#define TEENSY_PIN33_IOPORT IOPORT5
+#define TEENSY_PIN34_IOPORT IOPORT5
+#define TEENSY_PIN24_IOPORT IOPORT5
+
+#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26 PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27 PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28 PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29 PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30 PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31 PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32 PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33 PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34 PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35 PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36 PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37 PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38 PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39 PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40 PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41 PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42 PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43 PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44 PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45 PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46 PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47 PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48 PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49 PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50 PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51 PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN51)
+#define LINE_PIN52 PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53 PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54 PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_PIN55 PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
+#define LINE_PIN56 PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
+#define LINE_PIN57 PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
+
+#define LINE_LED LINE_PIN13
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
+
diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.mk b/os/hal/boards/PJRC_TEENSY_3_5/board.mk new file mode 100644 index 0000000..4e18eb0 --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_5/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.c b/os/hal/boards/PJRC_TEENSY_3_6/board.c new file mode 100644 index 0000000..e59f4ae --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_6/board.c @@ -0,0 +1,216 @@ +/* + ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + .ports = { + { + /* + * PORTA setup. + * + * PTA0 - SWD + * PTA3 - SWD + * PTA5 - PIN25 + * PTA12 - PIN3 + * PTA13 - PIN4 + * PTA14 - PIN26 + * PTA15 - PIN27 + * PTA16 - PIN28 + * PTA17 - PIN39 + * PTA18 - Crystal + * PTA19 - Crystal + * PTA26 - PIN42 + * PTA28 - PIN40 + * PTA29 - PIN41 + * + */ + .port = IOPORT1, + .pads = { + PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_ALTERNATIVE_7, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_INPUT_ANALOG, PAL_MODE_INPUT_ANALOG, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + }, + }, + { + /* + * PORTB setup. + * + * PTB0 - PIN16 + * PTB1 - PIN17 + * PTB2 - PIN19 + * PTB3 - PIN18 + * PTB4 - PIN49 + * PTB5 - PIN50 + * PTB10 - PIN31 + * PTB11 - PIN32 + * PTB16 - PIN0 - UART0_RX + * PTB17 - PIN1 - UART0_TX + * PTB18 - PIN29 + * PTB19 - PIN30 + * PTB20 - PIN43 + * PTB21 - PIN46 + * PTB22 - PIN44 + * PTB23 - PIN45 + */ + .port = IOPORT2, + .pads = { + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_ALTERNATIVE_3, PAL_MODE_ALTERNATIVE_3, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + }, + }, + { + /* + * PORTC setup. + * PTC0 - PIN15 + * PTC1 - PIN22 + * PTC2 - PIN23 + * PTC3 - PIN9 + * PTC4 - PIN10 + * PTC5 - PIN13 + * PTC6 - PIN11 + * PTC7 - PIN12 + * PTC8 - PIN35 + * PTC9 - PIN36 + * PTC10 - PIN37 + * PTC11 - PIN38 + * + */ + .port = IOPORT3, + .pads = { + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + }, + }, + { + /* + * PORTD setup. + * + * PTD0 - PIN2 + * PTD1 - PIN14 + * PTD2 - PIN7 + * PTD3 - PIN8 + * PTD4 - PIN6 + * PTD5 - PIN20 + * PTD6 - PIN21 + * PTD7 - PIN5 + * PTD8 - PIN47 + * PTD9 - PIN48 + * PTD11 - PIN55 + * PTD12 - PIN53 + * PTD13 - PIN52 + * PTD14 - PIN51 + * PTD15 - PIN54 + */ + .port = IOPORT4, + .pads = { + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + }, + }, + { + /* + * PORTE setup. + * + * PTE0 - SDHC + * PTE1 - SDHC + * PTE2 - SDHC + * PTE3 - SDHC + * PTE4 - SDHC + * PTE5 - SDHC + * PTE6 - USB OTG power switch + * PTE10 - PIN56 + * PTE11 - PIN57 + * PTE24 - PIN33 + * PTE25 - PIN34 + * PTE26 - PIN24 + */ + .port = IOPORT5, + .pads = { + PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, + PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, PAL_MODE_ALTERNATIVE_4, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, PAL_MODE_OUTPUT_PUSHPULL, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + PAL_MODE_UNCONNECTED, PAL_MODE_UNCONNECTED, + }, + }, + }, +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + MK66F18_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.h b/os/hal/boards/PJRC_TEENSY_3_6/board.h new file mode 100644 index 0000000..febd40c --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_6/board.h @@ -0,0 +1,345 @@ +/* + ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for the PJRC Teensy 3.6 board. + */ + +/* + * Board identifier. + */ +#define BOARD_PJRC_TEENSY_3_6 +#define BOARD_NAME "PJRC Teensy 3.6" + +/* External 16 MHz crystal */ +#define KINETIS_XTAL_FREQUENCY 16000000UL + +/* Use internal capacitors for the crystal */ +#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P + +/* + * MCU type + */ +#define MK66F18 + +/* + * IO pins assignments. + */ +#define PORTA_PIN0 0 +#define PORTA_PIN1 1 +#define PORTA_PIN2 2 +#define PORTA_PIN3 3 +#define PORTA_PIN4 4 +#define TEENSY_PIN25 5 +#define PORTA_PIN6 6 +#define PORTA_PIN7 7 +#define PORTA_PIN8 8 +#define PORTA_PIN9 9 +#define PORTA_PIN10 10 +#define PORTA_PIN11 11 +#define TEENSY_PIN3 12 +#define TEENSY_PIN4 13 +#define TEENSY_PIN26 14 +#define TEENSY_PIN27 15 +#define TEENSY_PIN28 16 +#define TEENSY_PIN39 17 +#define PORTA_PIN18 18 +#define PORTA_PIN19 19 +#define PORTA_PIN20 20 +#define PORTA_PIN21 21 +#define PORTA_PIN22 22 +#define PORTA_PIN23 23 +#define PORTA_PIN24 24 +#define PORTA_PIN25 25 +#define TEENSY_PIN42 26 +#define PORTA_PIN27 27 +#define TEENSY_PIN40 28 +#define TEENSY_PIN41 29 +#define PORTA_PIN30 30 +#define PORTA_PIN31 31 + +#define TEENSY_PIN40_IOPORT IOPORT1 +#define TEENSY_PIN41_IOPORT IOPORT1 +#define TEENSY_PIN42_IOPORT IOPORT1 +#define TEENSY_PIN3_IOPORT IOPORT1 +#define TEENSY_PIN4_IOPORT IOPORT1 +#define TEENSY_PIN25_IOPORT IOPORT1 +#define TEENSY_PIN26_IOPORT IOPORT1 +#define TEENSY_PIN27_IOPORT IOPORT1 +#define TEENSY_PIN28_IOPORT IOPORT1 +#define TEENSY_PIN39_IOPORT IOPORT1 + +#define TEENSY_PIN16 0 +#define TEENSY_PIN17 1 +#define TEENSY_PIN19 2 +#define TEENSY_PIN18 3 +#define TEENSY_PIN49 4 +#define TEENSY_PIN50 5 +#define PORTB_PIN6 6 +#define PORTB_PIN7 7 +#define PORTB_PIN8 8 +#define PORTB_PIN9 9 +#define TEENSY_PIN31 10 +#define TEENSY_PIN32 11 +#define PORTB_PIN12 12 +#define PORTB_PIN13 13 +#define PORTB_PIN14 14 +#define PORTB_PIN15 15 +#define TEENSY_PIN0 16 +#define TEENSY_PIN1 17 +#define TEENSY_PIN29 18 +#define TEENSY_PIN30 19 +#define TEENSY_PIN43 20 +#define TEENSY_PIN46 21 +#define TEENSY_PIN44 22 +#define TEENSY_PIN45 23 +#define PORTB_PIN24 24 +#define PORTB_PIN25 25 +#define PORTB_PIN26 26 +#define PORTB_PIN27 27 +#define PORTB_PIN28 28 +#define PORTB_PIN29 29 +#define PORTB_PIN30 30 +#define PORTB_PIN31 31 + +#define TEENSY_PIN49_IOPORT IOPORT2 +#define TEENSY_PIN50_IOPORT IOPORT2 +#define TEENSY_PIN43_IOPORT IOPORT2 +#define TEENSY_PIN44_IOPORT IOPORT2 +#define TEENSY_PIN45_IOPORT IOPORT2 +#define TEENSY_PIN46_IOPORT IOPORT2 +#define TEENSY_PIN0_IOPORT IOPORT2 +#define TEENSY_PIN1_IOPORT IOPORT2 +#define TEENSY_PIN29_IOPORT IOPORT2 +#define TEENSY_PIN30_IOPORT IOPORT2 +#define TEENSY_PIN31_IOPORT IOPORT2 +#define TEENSY_PIN32_IOPORT IOPORT2 +#define TEENSY_PIN16_IOPORT IOPORT2 +#define TEENSY_PIN17_IOPORT IOPORT2 +#define TEENSY_PIN19_IOPORT IOPORT2 +#define TEENSY_PIN18_IOPORT IOPORT2 + +#define TEENSY_PIN15 0 +#define TEENSY_PIN22 1 +#define TEENSY_PIN23 2 +#define TEENSY_PIN9 3 +#define TEENSY_PIN10 4 +#define TEENSY_PIN13 5 +#define TEENSY_PIN11 6 +#define TEENSY_PIN12 7 +#define TEENSY_PIN35 8 +#define TEENSY_PIN36 9 +#define TEENSY_PIN37 10 +#define TEENSY_PIN38 11 +#define PORTC_PIN12 12 +#define PORTC_PIN13 13 +#define PORTC_PIN14 14 +#define PORTC_PIN15 15 +#define PORTC_PIN16 16 +#define PORTC_PIN17 17 +#define PORTC_PIN18 18 +#define PORTC_PIN19 19 +#define PORTC_PIN20 20 +#define PORTC_PIN21 21 +#define PORTC_PIN22 22 +#define PORTC_PIN23 23 +#define PORTC_PIN24 24 +#define PORTC_PIN25 25 +#define PORTC_PIN26 26 +#define PORTC_PIN27 27 +#define PORTC_PIN28 28 +#define PORTC_PIN29 29 +#define PORTC_PIN30 30 +#define PORTC_PIN31 31 + +#define TEENSY_PIN9_IOPORT IOPORT3 +#define TEENSY_PIN10_IOPORT IOPORT3 +#define TEENSY_PIN11_IOPORT IOPORT3 +#define TEENSY_PIN12_IOPORT IOPORT3 +#define TEENSY_PIN35_IOPORT IOPORT3 +#define TEENSY_PIN36_IOPORT IOPORT3 +#define TEENSY_PIN37_IOPORT IOPORT3 +#define TEENSY_PIN38_IOPORT IOPORT3 +#define TEENSY_PIN13_IOPORT IOPORT3 +#define TEENSY_PIN15_IOPORT IOPORT3 +#define TEENSY_PIN22_IOPORT IOPORT3 +#define TEENSY_PIN23_IOPORT IOPORT3 + +#define TEENSY_PIN2 0 +#define TEENSY_PIN14 1 +#define TEENSY_PIN7 2 +#define TEENSY_PIN8 3 +#define TEENSY_PIN6 4 +#define TEENSY_PIN20 5 +#define TEENSY_PIN21 6 +#define TEENSY_PIN5 7 +#define TEENSY_PIN47 8 +#define TEENSY_PIN48 9 +#define PORTD_PIN10 10 +#define TEENSY_PIN55 11 +#define TEENSY_PIN53 12 +#define TEENSY_PIN52 13 +#define TEENSY_PIN51 14 +#define TEENSY_PIN54 15 +#define PORTD_PIN16 16 +#define PORTD_PIN17 17 +#define PORTD_PIN18 18 +#define PORTD_PIN19 19 +#define PORTD_PIN20 20 +#define PORTD_PIN21 21 +#define PORTD_PIN22 22 +#define PORTD_PIN23 23 +#define PORTD_PIN24 24 +#define PORTD_PIN25 25 +#define PORTD_PIN26 26 +#define PORTD_PIN27 27 +#define PORTD_PIN28 28 +#define PORTD_PIN29 29 +#define PORTD_PIN30 30 +#define PORTD_PIN31 31 + +#define TEENSY_PIN51_IOPORT IOPORT4 +#define TEENSY_PIN52_IOPORT IOPORT4 +#define TEENSY_PIN53_IOPORT IOPORT4 +#define TEENSY_PIN54_IOPORT IOPORT4 +#define TEENSY_PIN55_IOPORT IOPORT4 +#define TEENSY_PIN47_IOPORT IOPORT4 +#define TEENSY_PIN48_IOPORT IOPORT4 +#define TEENSY_PIN2_IOPORT IOPORT4 +#define TEENSY_PIN5_IOPORT IOPORT4 +#define TEENSY_PIN6_IOPORT IOPORT4 +#define TEENSY_PIN7_IOPORT IOPORT4 +#define TEENSY_PIN8_IOPORT IOPORT4 +#define TEENSY_PIN14_IOPORT IOPORT4 +#define TEENSY_PIN20_IOPORT IOPORT4 +#define TEENSY_PIN21_IOPORT IOPORT4 + +#define PORTE_PIN0 0 +#define PORTE_PIN1 1 +#define PORTE_PIN2 2 +#define PORTE_PIN3 3 +#define PORTE_PIN4 4 +#define PORTE_PIN5 5 +#define PORTE_PIN6 6 +#define PORTE_PIN7 7 +#define PORTE_PIN8 8 +#define PORTE_PIN9 9 +#define TEENSY_PIN56 10 +#define TEENSY_PIN57 11 +#define PORTE_PIN12 12 +#define PORTE_PIN13 13 +#define PORTE_PIN14 14 +#define PORTE_PIN15 15 +#define PORTE_PIN16 16 +#define PORTE_PIN17 17 +#define PORTE_PIN18 18 +#define PORTE_PIN19 19 +#define PORTE_PIN20 20 +#define PORTE_PIN21 21 +#define PORTE_PIN22 22 +#define PORTE_PIN23 23 +#define TEENSY_PIN33 24 +#define TEENSY_PIN34 25 +#define TEENSY_PIN24 26 +#define PORTE_PIN27 27 +#define PORTE_PIN28 28 +#define PORTE_PIN29 29 +#define PORTE_PIN30 30 +#define PORTE_PIN31 31 + +#define TEENSY_PIN56_IOPORT IOPORT5 +#define TEENSY_PIN57_IOPORT IOPORT5 +#define TEENSY_PIN24_IOPORT IOPORT5 +#define TEENSY_PIN33_IOPORT IOPORT5 +#define TEENSY_PIN34_IOPORT IOPORT5 + + +#define LINE_PIN0 PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0) +#define LINE_PIN1 PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1) +#define LINE_PIN2 PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2) +#define LINE_PIN3 PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3) +#define LINE_PIN4 PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4) +#define LINE_PIN5 PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5) +#define LINE_PIN6 PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6) +#define LINE_PIN7 PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7) +#define LINE_PIN8 PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8) +#define LINE_PIN9 PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9) +#define LINE_PIN10 PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10) +#define LINE_PIN11 PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11) +#define LINE_PIN12 PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12) +#define LINE_PIN13 PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13) +#define LINE_PIN14 PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14) +#define LINE_PIN15 PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15) +#define LINE_PIN16 PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16) +#define LINE_PIN17 PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17) +#define LINE_PIN18 PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18) +#define LINE_PIN19 PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19) +#define LINE_PIN20 PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20) +#define LINE_PIN21 PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21) +#define LINE_PIN22 PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22) +#define LINE_PIN23 PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23) +#define LINE_PIN24 PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24) +#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25) +#define LINE_PIN25 PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25) +#define LINE_PIN26 PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26) +#define LINE_PIN27 PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27) +#define LINE_PIN28 PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28) +#define LINE_PIN29 PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29) +#define LINE_PIN30 PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30) +#define LINE_PIN31 PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31) +#define LINE_PIN32 PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32) +#define LINE_PIN33 PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33) +#define LINE_PIN34 PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34) +#define LINE_PIN35 PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35) +#define LINE_PIN36 PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36) +#define LINE_PIN37 PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37) +#define LINE_PIN38 PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38) +#define LINE_PIN39 PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39) +#define LINE_PIN40 PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40) +#define LINE_PIN41 PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41) +#define LINE_PIN42 PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42) +#define LINE_PIN43 PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43) +#define LINE_PIN44 PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44) +#define LINE_PIN45 PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45) +#define LINE_PIN46 PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46) +#define LINE_PIN47 PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47) +#define LINE_PIN48 PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48) +#define LINE_PIN49 PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49) +#define LINE_PIN50 PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50) +#define LINE_PIN51 PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN50) +#define LINE_PIN52 PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52) +#define LINE_PIN53 PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53) +#define LINE_PIN54 PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54) +#define LINE_PIN55 PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55) +#define LINE_PIN56 PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56) +#define LINE_PIN57 PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57) + +#define LINE_LED LINE_PIN13 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.mk b/os/hal/boards/PJRC_TEENSY_3_6/board.mk new file mode 100644 index 0000000..6e2695c --- /dev/null +++ b/os/hal/boards/PJRC_TEENSY_3_6/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6
diff --git a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c index dc058f6..3412452 100644 --- a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c +++ b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,15 +14,76 @@ limitations under the License.
*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+} gpio_config_t;
-#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
+ * @brief STM32 GPIO static initialization data.
*/
-const PALConfig pal_default_config = {
+static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
@@ -57,21 +118,103 @@ const PALConfig pal_default_config = { #endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB(STM32_GPIO_EN_MASK);
+ rccEnableAHB(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
/**
* @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
*/
void __early_init(void) {
+ stm32_gpio_init();
stm32_clock_init();
}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
@@ -99,4 +242,5 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any.
*/
void boardInit(void) {
+
}
diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk index 8232a30..22b5467 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk index 56298eb..e95de0b 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index cdedad6..83b1f02 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -48,7 +48,7 @@ #endif
#if !defined(HAL_USE_QEI)
-#define HAL_USE_QEI FALSE
+#define HAL_USE_QEI FALSE
#endif
#if !defined(HAL_USE_RNG)
diff --git a/os/hal/include/hal_qei.h b/os/hal/include/hal_qei.h index ce4a089..15f24ce 100644 --- a/os/hal/include/hal_qei.h +++ b/os/hal/include/hal_qei.h @@ -83,10 +83,10 @@ typedef void (*qeicallback_t)(QEIDriver *qeip); */
typedef enum {
QEI_OVERFLOW_WRAP = 0, /**< Counter value will wrap around. */
-#if QEI_USE_OVERFLOW_DISCARD == TRUE
+#if defined(QEI_USE_OVERFLOW_DISCARD) && QEI_USE_OVERFLOW_DISCARD == TRUE
QEI_OVERFLOW_DISCARD = 1, /**< Counter doesn't change. */
#endif
-#if QEI_USE_OVERFLOW_MINMAX == TRUE
+#if defined(QEI_USE_OVERFLOW_MINMAX) && QEI_USE_OVERFLOW_MINMAX == TRUE
QEI_OVERFLOW_MINMAX = 2, /**< Counter will be updated upto min or max.*/
#endif
} qeioverflow_t;
diff --git a/os/hal/include/usbh/dev/uvc.h b/os/hal/include/usbh/dev/uvc.h index 817d465..0477312 100644 --- a/os/hal/include/usbh/dev/uvc.h +++ b/os/hal/include/usbh/dev/uvc.h @@ -430,7 +430,7 @@ extern "C" { static inline msg_t usbhuvcLockAndFetchS(USBHUVCDriver *uvcdp, msg_t *msg, systime_t timeout) { chMtxLockS(&uvcdp->mtx); - msg_t ret = chMBFetchS(&uvcdp->mb, msg, timeout); + msg_t ret = chMBFetchTimeoutS(&uvcdp->mb, msg, timeout); if (ret != MSG_OK) chMtxUnlockS(&uvcdp->mtx); return ret; diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c index e6eeed8..594f7af 100644 --- a/os/hal/ports/KINETIS/K20x/hal_lld.c +++ b/os/hal/ports/KINETIS/K20x/hal_lld.c @@ -148,11 +148,10 @@ void k20x_clock_init(void) { * frequency, which would required other registers to be modified.
*/
/* Enable OSC, low power mode */
- MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
if (KINETIS_XTAL_FREQUENCY > 8000000UL)
- MCG->C2 |= MCG_C2_RANGE0(2);
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
else
- MCG->C2 |= MCG_C2_RANGE0(1);
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
frdiv = 7;
ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c new file mode 100644 index 0000000..cfe633b --- /dev/null +++ b/os/hal/ports/KINETIS/K60x/hal_lld.c @@ -0,0 +1,237 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+ Copyright (C) 2017 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/hal_lld.c
+ * @brief HAL Driver subsystem low level driver source template.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used,section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+ 0xFF, /* NV_BACKKEY3: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY2: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY1: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY0: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY7: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY6: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY5: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY4: KEY=0xFF */
+ 0xFF, /* NV_FPROT3: PROT=0xFF */
+ 0xFF, /* NV_FPROT2: PROT=0xFF */
+ 0xFF, /* NV_FPROT1: PROT=0xFF */
+ 0xFF, /* NV_FPROT0: PROT=0xFF */
+ 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+ 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+ NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ 0xFF,
+ 0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ * @todo Use a macro to define the system clock frequency.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+}
+
+/**
+ * @brief K60x clock initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ * @todo This function needs to be more generic.
+ * @todo This function should be combined with the nearly-identical
+ * functions in other Kinetis ports.
+ *
+ * @special
+ */
+void k60x_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+ /* Disable the watchdog */
+ WDOG->UNLOCK = 0xC520;
+ WDOG->UNLOCK = 0xD928;
+ __asm__("nop");
+ WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
+
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+ /* Set clock dividers */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] = 0;
+ PORTA->PCR[19] = 0;
+
+ /*
+ * Start in FEI mode
+ */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* TODO: need to add more flexible calculation, specially regarding
+ * divisors which may not be available depending on the XTAL
+ * frequency, which would required other registers to be modified.
+ */
+ /* Enable OSC, low power mode */
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
+ else
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
+
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
+
+ /* Wait for crystal oscillator to begin */
+ while (!(MCG->S & MCG_S_OSCINIT0));
+
+ /* Wait for the FLL to use the oscillator */
+ while (MCG->S & MCG_S_IREFST);
+
+ /* Wait for the MCGOUTCLK to use the oscillator */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
+
+ /*
+ * Now in FBE mode
+ */
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /*
+ * Config PLL input for 2 MHz
+ * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+ */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
+
+ /*
+ * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+ */
+ for(i = 24; i < 56; i++)
+ {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+ {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
+
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+ /* Wait for PLL to start using crystal as its input, and to lock */
+ while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
+
+ /*
+ * Now in PBE mode
+ */
+ /* Set the PLL dividers for the different clocks */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_IRC48M; /* FIXME ? Why this? */
+
+ /* Switch to PLL as clock source */
+ MCG->C1 = MCG_C1_CLKS(0);
+
+ /* Wait for PLL clock to be used */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
+
+ /*
+ * Now in PEE mode
+ */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.h b/os/hal/ports/KINETIS/K60x/hal_lld.h new file mode 100644 index 0000000..8da89b3 --- /dev/null +++ b/os/hal/ports/KINETIS/K60x/hal_lld.h @@ -0,0 +1,302 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K60x/hal_lld.h
+ * @brief Kinetis K60x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H_
+#define HAL_LLD_H_
+
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE /* FIXME check */
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
+/**
+ * @brief Clock divider for core/system clocks (OUTDIV1).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for bus clock (OUTDIV2).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz bus clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV2 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for flash clock (OUTDIV4).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 24 MHz flash clock
+ * from a 96 MHz PLL output
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 4
+ #endif
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
+#endif
+
+/**
+ * @brief MCU bus clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
+#endif
+
+/**
+ * @brief MCU flash clock frequency.
+ */
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+ #error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+ #error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+ #error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+ #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+ #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+ #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+ KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void k60x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/kinetis_registry.h b/os/hal/ports/KINETIS/K60x/kinetis_registry.h new file mode 100644 index 0000000..e595c35 --- /dev/null +++ b/os/hal/ports/KINETIS/K60x/kinetis_registry.h @@ -0,0 +1,198 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ (C) 2017 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K60x/kinetis_registry.h
+ * @brief K60x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef KINETIS_REGISTRY_H_
+#define KINETIS_REGISTRY_H_
+
+#if !defined(K60x) || defined(__DOXYGEN__)
+#define K60x /* Processor family */
+#endif
+
+#if defined(K64FX512) || defined(K64FN1M0) || defined(__DOXYGEN__)
+#define K64F /* Sub-family */
+#else
+#error "Unknown processor sub-family"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name K60x capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* K64F */
+/*===========================================================================*/
+#if defined(K64F) || defined(__DOXYGEN__)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 120000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 60000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR VectorDC
+#define KINETIS_HAS_ADC1 TRUE
+#define KINETIS_ADC1_IRQ_VECTOR Vector164
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINETIS_DAC0_IRQ_VECTOR Vector120
+#define KINETIS_HAS_DAC1 TRUE
+#define KINETIS_DAC1_IRQ_VECTOR Vector160
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_DMA4_IRQ_VECTOR Vector50
+#define KINETIS_DMA5_IRQ_VECTOR Vector54
+#define KINETIS_DMA6_IRQ_VECTOR Vector58
+#define KINETIS_DMA7_IRQ_VECTOR Vector5C
+#define KINETIS_DMA8_IRQ_VECTOR Vector60
+#define KINETIS_DMA9_IRQ_VECTOR Vector64
+#define KINETIS_DMA10_IRQ_VECTOR Vector68
+#define KINETIS_DMA11_IRQ_VECTOR Vector6C
+#define KINETIS_DMA12_IRQ_VECTOR Vector70
+#define KINETIS_DMA13_IRQ_VECTOR Vector74
+#define KINETIS_DMA14_IRQ_VECTOR Vector78
+#define KINETIS_DMA15_IRQ_VECTOR Vector7C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector80
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR Vector12C
+#define KINETIS_PORTB_IRQ_VECTOR Vector130
+#define KINETIS_PORTC_IRQ_VECTOR Vector134
+#define KINETIS_PORTD_IRQ_VECTOR Vector138
+#define KINETIS_PORTE_IRQ_VECTOR Vector13C
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR VectorA0
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR VectorA4
+#define KINETIS_HAS_I2C2 TRUE
+#define KINETIS_I2C2_IRQ_VECTOR Vector168
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR VectorBC
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorC0
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR VectorC4
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR VectorC8
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR VectorCC
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR VectorD0
+
+#define KINETIS_HAS_SERIAL3 TRUE
+#define KINETIS_SERIAL3_IRQ_VECTOR VectorD4
+#define KINETIS_SERIAL3_ERROR_IRQ_VECTOR VectorD8
+
+#define KINETIS_HAS_SERIAL4 TRUE
+#define KINETIS_SERIAL4_IRQ_VECTOR Vector148
+#define KINETIS_SERIAL4_ERROR_IRQ_VECTOR Vector14C
+
+#define KINETIS_HAS_SERIAL5 TRUE
+#define KINETIS_SERIAL5_IRQ_VECTOR Vector150
+#define KINETIS_SERIAL5_ERROR_IRQ_VECTOR Vector154
+
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR VectorAC
+#define KINETIS_HAS_SPI2 TRUE
+#define KINETIS_SPI2_IRQ_VECTOR Vector144
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+#define KINETIS_FTM3_CHANNELS 8
+
+#define KINETIS_FTM0_IRQ_VECTOR VectorE8
+#define KINETIS_FTM1_IRQ_VECTOR VectorEC
+#define KINETIS_FTM2_IRQ_VECTOR VectorF0
+#define KINETIS_HAS_FTM2 TRUE
+#define KINETIS_FTM3_IRQ_VECTOR Vector15C
+#define KINETIS_HAS_FTM3 TRUE
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR Vector100
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR Vector104
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR Vector108
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR Vector10C
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR Vector114
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/* SDHC (SDC, MMC, SDIO) attributes */
+#define KINETIS_HAS_SDHC TRUE
+#define KINETIS_SDHC_IRQ_VECTOR Vector184
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR Vector128
+
+#endif
+/** @} */
+
+#endif /* KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/platform.mk b/os/hal/ports/KINETIS/K60x/platform.mk new file mode 100644 index 0000000..33ac2cc --- /dev/null +++ b/os/hal/ports/KINETIS/K60x/platform.mk @@ -0,0 +1,19 @@ +# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
+# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_spi_lld.c \
+# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_pwm_lld.c \
+# ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index c6b3d11..f615dd5 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -442,7 +442,13 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* wait until the bus is released */
/* Calculating the time window for the timeout on the busy bus condition.*/
start = osalOsGetSystemTimeX();
+#if defined(OSAL_TIME_MS2I)
+ end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
+#elif defined(OSAL_TIME_MS2ST)
+ end = start + OSAL_TIME_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+#else
end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+#endif
while(true) {
osalSysLock();
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c new file mode 100644 index 0000000..6ba932e --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c @@ -0,0 +1,993 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ Copyright (C) 2017..2018 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc_lld.c
+ * @brief Kinetis SDC subsystem low level driver.
+ *
+ * This driver provides a single SDC driver based on the Kinetis
+ * "Secured Digital Host Controller (SDHC)" peripheral.
+ *
+ * In order to use this driver, other peripherals must also be configured:
+ *
+ * The MPU must either be disabled (CESR=0), or it must be configured
+ * to allow the SDHC peripheral DMA access to any data buffers (read
+ * or write).
+ *
+ * The SDHC signals must be routed to the desired pins, and pullups/pulldowns
+ * configured.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_mmcsd.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if defined(MK66F18)
+/* Configure SDHC block to use the IRC48M clock */
+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY 48000000UL
+#else
+/* We configure the SDHC block to use the system clock */
+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#ifndef KINETIS_SDHC_PRIORITY
+#define KINETIS_SDHC_PRIORITY 12 /* TODO? Default IRQ priority for SDHC */
+#endif
+
+/* The DTOC value (data timeout counter) controls how long the SDHC
+ will wait for a data transfer before indicating a timeout to
+ us. The card can tell us how long that should be, but various SDHC
+ documentation suggests that we should always allow around 500 msec
+ even if the card says it will finish sooner. This only comes into
+ play if there's a malfunction or something, so it's not critical to
+ get it exactly right.
+
+ It controls the ratio between the SDCLK frequency and the
+ timeout, so we have a different DTOCV for each bus clock
+ frequency.
+*/
+#define DTOCV_300ms_400kHz 4 /* 4 -> 2^17 -> 328 msec */
+#define DTOCV_700ms_25MHz 11 /* 11 -> 2^24 -> 671 msec */
+#define DTOCV_700ms_50MHz 12 /* 12 -> 2^25 -> 671 msec */
+
+#if 0
+#define TRACE(t, val) chDbgWriteTrace ((void *)t, (void *)(uintptr_t)(val))
+#define TRACEI(t, val) chDbgWriteTraceI((void *)t, (void *)(uintptr_t)(val))
+#else
+#define TRACE(t, val)
+#define TRACEI(t, val)
+#endif
+
+#define DIV_RND_UP(a, b) ( ((a)+(b)-1) / (b) )
+
+/* Error bits from the SD / MMC Card Status response word. */
+/* TODO: These really belong in a HLD, not here. */
+#define MMC_ERR_OUT_OF_RANGE (1U << 31)
+#define MMC_ERR_ADDRESS (1U << 30)
+#define MMC_ERR_BLOCK_LEN (1U << 29)
+#define MMC_ERR_ERASE_SEQ (1U << 28)
+#define MMC_ERR_ERASE_PARAM (1U << 27)
+#define MMC_ERR_WP (1U << 26)
+#define MMC_ERR_CARD_IS_LOCKED (1U << 25)
+#define MMC_ERR_LOCK_UNLOCK_FAILED (1U << 24)
+#define MMC_ERR_COM_CRC_ERROR (1U << 23)
+#define MMC_ERR_ILLEGAL_COMMAND (1U << 22)
+#define MMC_ERR_CARD_ECC_FAILED (1U << 21)
+#define MMC_ERR_CARD_CONTROLLER (1U << 20)
+#define MMC_ERR_ERROR (1U << 19)
+#define MMC_ERR_CSD_OVERWRITE (1U << 16)
+#define MMC_ERR_AKE_SEQ (1U << 3)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SDCD1 driver identifier.
+ */
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+SDCDriver SDCD1;
+#else
+#error HAL_USE_SDC is true but PLATFORM_SDC_USE_SDC1 is false
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void recover_after_botched_transfer(SDCDriver *);
+static msg_t wait_interrupt(SDCDriver *, uint32_t);
+static bool sdc_lld_transfer(SDCDriver *, uint32_t, uintptr_t, uint32_t, uint32_t);
+
+/**
+ * Compute the SDCLKFS and DVS values for a given SDCLK divisor.
+ *
+ * Note that in the current code, this function is always called with
+ * a constant argument (there are only a handful of valid SDCLK
+ * frequencies), and so GCC computes the results at compile time and
+ * does not actually emit this function into the output at all unless
+ * you're compiling with optimizations turned off.
+ *
+ * However if someone compiles with a KINETIS_SDHC_PERIPHERAL_FREQUENCY
+ * that is not a compile-time constant, this function would get emitted.
+ */
+static uint32_t divisor_settings(unsigned divisor)
+{
+ /* First, handle all the special cases */
+ if (divisor <= 1) {
+ /* Pass through */
+ return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(0);
+ }
+ if (divisor <= 16 && (divisor & 0x01)) {
+ /* Disable the prescaler, just use the divider. */
+ return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(divisor - 1);
+ }
+ if (divisor <= 32 && !(divisor & 0x01)) {
+ /* Prescale by 2, but do the rest with the divider */
+ return SDHC_SYSCTL_SDCLKFS(0x01) | SDHC_SYSCTL_DVS((divisor >> 1) - 1);
+ }
+ if (divisor >= 0x1000) {
+ /* It's not possible to divide by more than 2^12. If we're asked to,
+ just do the best we can. */
+ return SDHC_SYSCTL_SDCLKFS(0x80) | SDHC_SYSCTL_DVS(0xF);
+ }
+
+ /* The bit position in SDCLKFS provides a power-of-two prescale
+ factor, and the four bits in DVS allow division by up to 16
+ (division by DVS+1). We want to approximate `divisor` using these
+ terms, but we want to round up --- it's OK to run the card a
+ little bit too slow, but not OK to run it a little bit too
+ fast. */
+
+ unsigned shift = (8 * sizeof(unsigned int) - 4) - __builtin_clz(divisor);
+
+ /* Shift the divisor value right so that it only occupies the four
+ lowest bits. Subtract one because that's how the DVS circuit
+ works. Add one if we shifted any 1-bits off the bottom, so that
+ we always round up. */
+ unsigned dvs = (divisor >> shift) - ((divisor & ((1 << shift)-1))? 0 : 1);
+
+ return SDHC_SYSCTL_SDCLKFS(1 << (shift-1)) | SDHC_SYSCTL_DVS(dvs);
+}
+
+/**
+ * @brief Enable the SDHC clock when stable.
+ *
+ * Waits for the clock divider in the SDHC block to stabilize, then
+ * enables the SD clock.
+ */
+static void enable_clock_when_stable(uint32_t new_sysctl)
+{
+ SDHC->SYSCTL = new_sysctl;
+
+ /* Wait for clock divider to stabilize */
+ while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {
+ osalThreadSleepMilliseconds(1);
+ }
+
+ /* Restart the clock */
+ SDHC->SYSCTL = new_sysctl | SDHC_SYSCTL_SDCLKEN;
+
+ /* Wait for clock to stabilize again */
+ while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {
+ osalThreadSleepMilliseconds(1);
+ }
+}
+
+/**
+ * Translate error bits from a CMD transaction to the HAL's error flag set.
+ */
+static sdcflags_t translate_cmd_error(uint32_t status) {
+ /* Translate the failure into the flags understood by the top half */
+
+ sdcflags_t errors = 0;
+
+ if (status & SDHC_IRQSTAT_CTOE || !(status & SDHC_IRQSTAT_CC)) {
+ errors |= SDC_COMMAND_TIMEOUT;
+ }
+ if (status & SDHC_IRQSTAT_CCE) {
+ errors |= SDC_CMD_CRC_ERROR;
+ }
+
+ /* If CTOE and CCE are both set, this indicates that the Kinetis
+ SDHC peripheral has detected a CMD line conflict in a
+ multi-master scenario. There's no specific code for that, so just
+ pass it through as a combined timeout+CRC failure. */
+
+ /* Translate any other framing and protocol errors into CRC errors. */
+ if (status & ~(SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE|SDHC_IRQSTAT_CC)) {
+ errors |= SDC_CMD_CRC_ERROR;
+ }
+
+ return errors;
+}
+
+/**
+ * Translate error bits from a card's R1 response word into the HAL's
+ * error flag set.
+ *
+ * This function should probably be in the HLD, not here.
+ */
+static sdcflags_t translate_mmcsd_error(uint32_t cardstatus) {
+ sdcflags_t errors = 0;
+
+ cardstatus &= MMCSD_R1_ERROR_MASK;
+
+ if (cardstatus & MMC_ERR_COM_CRC_ERROR)
+ errors |= SDC_CMD_CRC_ERROR;
+
+ if (cardstatus & MMC_ERR_CARD_ECC_FAILED)
+ errors |= SDC_DATA_CRC_ERROR;
+
+ /* TODO: Extend the HLD error codes at least enough to distinguish
+ between invalid command/parameter errors (card is OK, but
+ retrying w/o change won't help) and other errors */
+ if (cardstatus & ~(MMC_ERR_COM_CRC_ERROR|MMC_ERR_CARD_ECC_FAILED))
+ errors |= SDC_UNHANDLED_ERROR;
+
+ return errors;
+}
+
+/**
+ * @brief Perform one CMD transaction on the SD bus.
+ */
+static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
+ /* SDCLKEN (CMD clock enabled) should be true;
+ * SDSTB (clock stable) should be true;
+ * CIHB (command inhibit / busy) should be false */
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_SDSTB|SDHC_PRSSTAT_CIHB)) == SDHC_PRSSTAT_SDSTB, "Not in expected state");
+ osalDbgAssert(SDHC->SYSCTL & SDHC_SYSCTL_SDCLKEN, "Clock disabled");
+ osalDbgCheck((cmd & SDHC_XFERTYP_DPSEL) == 0);
+ osalDbgCheck((SDHC->IRQSTAT & (SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC)) == 0);
+
+ /* This initiates the CMD transaction */
+ TRACE(1, cmd);
+ SDHC->XFERTYP = cmd;
+
+ uint32_t events =
+ SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+ wait_interrupt(sdcp, SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC);
+ uint32_t status = SDHC->IRQSTAT & events;
+
+ /* These bits are write-1-to-clear (w1c) */
+ SDHC->IRQSTAT = status;
+
+ /* In the normal case, the CC (command complete) bit is set but none
+ of the others are */
+ if (status == SDHC_IRQSTAT_CC)
+ return HAL_SUCCESS;
+
+ /* Translate the failure into the flags understood by the top half */
+ sdcp->errors |= translate_cmd_error(status);
+
+ TRACE(9, SDHC->PRSSTAT);
+
+ /* Issue a reset to the CMD portion of the SDHC peripheral to clear the
+ error bits and enable subsequent commands */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Perform one data transaction on the SD bus.
+ */
+static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
+
+ osalDbgCheck(cmd & SDHC_XFERTYP_DPSEL);
+ osalDbgCheck(cmd & SDHC_XFERTYP_DMAEN);
+
+ const uint32_t cmd_end_bits =
+ SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+
+ const uint32_t transfer_end_bits =
+ SDHC_IRQSTAT_DMAE | SDHC_IRQSTAT_AC12E | SDHC_IRQSTAT_DEBE |
+ SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_TC;
+
+ TRACE(3, cmd);
+
+ osalSysLock();
+ osalDbgCheck(sdcp->thread == NULL);
+
+ /* Clear anything pending from an earlier transfer */
+ SDHC->IRQSTAT = cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT;
+
+ /* Enable interrupts on completions or failures */
+ uint32_t old_staten = SDHC->IRQSTATEN;
+ SDHC->IRQSTATEN = (old_staten & ~(SDHC_IRQSTAT_BRR|SDHC_IRQSTAT_BWR)) | (cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT);
+ SDHC->IRQSIGEN = SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;
+
+ /* Start the transfer */
+ SDHC->XFERTYP = cmd;
+
+ /* Await an interrupt */
+ osalThreadSuspendS(&sdcp->thread);
+ osalSysUnlock();
+
+ /* Retrieve the flags and clear them */
+ uint32_t cmdstat = SDHC->IRQSTAT & cmd_end_bits;
+ SDHC->IRQSTAT = cmdstat;
+ TRACE(2, cmdstat);
+
+ /* If the command failed, the transfer won't happen */
+ if (cmdstat != SDHC_IRQSTAT_CC) {
+ /* The command couldn't be sent, or wasn't acknowledged */
+ sdcp->errors |= translate_cmd_error(cmdstat);
+
+ /* Clear the error status */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+ if (cmdstat == (SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE)) {
+ /* A CMD-line conflict is unlikely, but doesn't require further recovery */
+ } else {
+ /* For most error situations, we don't know whether the command
+ failed to send or we got line noise while receiving. Make sure
+ we're in a sane state by resetting the connection. */
+ recover_after_botched_transfer(sdcp);
+ }
+
+ return HAL_FAILED;
+ }
+
+ uint32_t cmdresp = SDHC->CMDRSP[0];
+ TRACE(11, cmdresp);
+ if (cmdresp & MMCSD_R1_ERROR_MASK) {
+ /* The command was sent, and the card responded with an error indication */
+ sdcp->errors |= translate_mmcsd_error(cmdresp);
+ return HAL_FAILED;
+ }
+
+ /* Check for end of data transfer phase */
+ uint32_t datastat;
+ for (;;) {
+ datastat = SDHC->IRQSTAT & (transfer_end_bits | SDHC_IRQSTAT_DINT);
+ if (datastat & transfer_end_bits)
+ break;
+ wait_interrupt(sdcp, transfer_end_bits);
+ }
+ TRACE(6, datastat);
+ SDHC->IRQSTAT = datastat;
+
+ /* Handle data transfer errors */
+ if ((datastat & ~(SDHC_IRQSTAT_DINT)) != SDHC_IRQSTAT_TC) {
+ bool should_cancel = false;
+
+ /* Data phase errors */
+ if (datastat & (SDHC_IRQSTAT_DCE|SDHC_IRQSTAT_DEBE)) {
+ sdcp->errors |= SDC_DATA_CRC_ERROR;
+ should_cancel = true;
+ }
+ if (datastat & SDHC_IRQSTAT_DTOE) {
+ sdcp->errors |= SDC_DATA_TIMEOUT;
+ should_cancel = true;
+ }
+
+ /* Internal DMA error */
+ if (datastat & SDHC_IRQSTAT_DMAE) {
+ sdcp->errors |= SDC_UNHANDLED_ERROR;
+ if (!(datastat & SDHC_IRQSTAT_TC))
+ should_cancel = true;
+ }
+
+ if (datastat & SDHC_IRQSTAT_AC12E) {
+ uint32_t cmd12error = SDHC->AC12ERR;
+
+ /* We don't know if CMD12 was successfully executed */
+ should_cancel = true;
+
+ if (cmd12error & SDHC_AC12ERR_AC12NE) {
+ sdcp->errors |= SDC_UNHANDLED_ERROR;
+ } else {
+ if (cmd12error & SDHC_AC12ERR_AC12TOE)
+ sdcp->errors |= SDC_COMMAND_TIMEOUT;
+ if (cmd12error & (SDHC_AC12ERR_AC12CE|SDHC_AC12ERR_AC12EBE))
+ sdcp->errors |= SDC_CMD_CRC_ERROR;
+ }
+ }
+
+ if (should_cancel) {
+ recover_after_botched_transfer(sdcp);
+ }
+
+ return HAL_FAILED;
+ }
+
+ /* For a read transfer, make sure the DMA has finished transferring
+ * to host memory. (For a write transfer, the DMA necessarily finishes
+ * before the transfer does, so we don't need to wait for it
+ * specially.) */
+ if (!(datastat & SDHC_IRQSTAT_DINT)) {
+ for(;;) {
+ datastat = SDHC->IRQSTAT & (SDHC_IRQSTAT_DINT|SDHC_IRQSTAT_DMAE);
+ if (datastat) {
+ SDHC->IRQSTAT = datastat;
+ TRACE(7, datastat);
+ break;
+ }
+ /* ...?? */
+ }
+ }
+
+ SDHC->IRQSTATEN = old_staten;
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Wait for an interrupt from the SDHC peripheral.
+ *
+ * @param[in] mask Bits to enable in IRQSIGEN.
+ *
+ * @return MSG_OK
+ */
+static msg_t wait_interrupt(SDCDriver *sdcp, uint32_t mask) {
+ osalSysLock();
+ SDHC->IRQSIGEN = mask;
+ msg_t wakeup = osalThreadSuspendS(&sdcp->thread);
+ osalSysUnlock();
+ return wakeup;
+}
+
+static void recover_after_botched_transfer(SDCDriver *sdcp) {
+
+ /* Query the card state */
+ uint32_t cardstatus;
+ if (sdc_lld_send_cmd_short_crc(sdcp,
+ MMCSD_CMD_SEND_STATUS,
+ sdcp->rca, &cardstatus) == HAL_SUCCESS) {
+ sdcp->errors |= translate_mmcsd_error(cardstatus);
+ uint32_t state = MMCSD_R1_STS(cardstatus);
+ if (state == MMCSD_STS_DATA) {
+
+ /* Send a CMD12 to make sure the card isn't still transferring anything */
+ SDHC->CMDARG = 0;
+ send_and_wait_cmd(sdcp,
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_STOP_TRANSMISSION) |
+ SDHC_XFERTYP_CMDTYP_ABORT |
+ /* TODO: Should we set CICEN and CCCEN here? */
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b);
+ }
+ }
+
+ /* And reset the data block of the SDHC peripheral */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTD;
+}
+
+/**
+ * @brief Perform one data transfer command
+ *
+ * Sends a command to the card and waits for the corresponding data transfer
+ * (either a read or write) to complete.
+ */
+static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,
+ uintptr_t buf, uint32_t n,
+ uint32_t cmdx) {
+
+ osalDbgCheck(n > 0);
+ osalDbgCheck((buf & 0x03) == 0); /* Must be 32-bit aligned */
+
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+ "SDHC interface not ready");
+
+ /* We always operate in terms of 512-byte blocks; the upper-layer
+ driver doesn't change the block size. The SDHC spec suggests that
+ only low-capacity cards support block sizes other than 512 bytes
+ anyway (SDHC "Physical Layer Simplified Specification" ver 6.0) */
+
+ if (sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) {
+ SDHC->CMDARG = startblk;
+ } else {
+ SDHC->CMDARG = startblk * MMCSD_BLOCK_SIZE;
+ }
+
+ /* Store the DMA start address */
+ SDHC->DSADDR = buf;
+
+ uint32_t xfer;
+ /* For data transfers, we need to set some extra bits in XFERTYP according to the
+ transfer we're starting:
+ DPSEL -> enable data transfer
+ DTDSEL -> 1 for a read (card-to-host) transfer
+ MSBSEL, BCEN -> multiple block transfer using BLKATTR_BLKCNT
+ AC12EN -> Automatically issue MMCSD_CMD_STOP_TRANSMISSION at end of transfer
+
+ Setting BLKCOUNT to 1 seems to be necessary even if MSBSEL+BCEN
+ is not set, despite the datasheet suggesting otherwise. I'm not
+ sure if this is a silicon bug or if I'm misunderstanding the
+ datasheet.
+ */
+ SDHC->BLKATTR =
+ SDHC_BLKATTR_BLKCNT(n) |
+ SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
+ if (n == 1) {
+ xfer =
+ cmdx |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+ } else {
+ xfer =
+ cmdx |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b |
+ SDHC_XFERTYP_MSBSEL | SDHC_XFERTYP_BCEN | SDHC_XFERTYP_AC12EN |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+ }
+
+ return send_and_wait_transfer(sdcp, xfer);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SDHC_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ osalSysLockFromISR();
+
+ TRACEI(4, SDHC->IRQSTAT);
+
+ /* We disable the interrupts, and wake up the usermode task to read
+ * the flags from IRQSTAT.
+ */
+ SDHC->IRQSIGEN = 0;
+
+ osalThreadResumeI(&SDCD1.thread, MSG_OK);
+
+ osalSysUnlockFromISR();
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SDC driver initialization.
+ *
+ * @notapi
+ */
+void sdc_lld_init(void) {
+#if PLATFORM_SDC_USE_SDC1 == TRUE
+ sdcObjectInit(&SDCD1);
+#endif
+}
+
+
+/**
+ * @brief Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start(SDCDriver *sdcp) {
+
+ if (sdcp->state == BLK_STOP) {
+#if defined(MK66F18)
+ /* Use IRC48M clock for SDHC */
+ SIM->SOPT2 |= SIM_SOPT2_SDHCSRC(1);
+ SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
+#else
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) |
+ SIM_SOPT2_SDHCSRC(0); /* SDHC clock source 0: Core/system clock. */
+#endif
+ SIM->SCGC3 |= SIM_SCGC3_SDHC; /* Enable clock to SDHC peripheral */
+
+ /* Reset the SDHC block */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTA;
+ while(SDHC->SYSCTL & SDHC_SYSCTL_RSTA) {
+ osalThreadSleepMilliseconds(1);
+ }
+
+ SDHC->IRQSIGEN = 0;
+ nvicEnableVector(SDHC_IRQn, KINETIS_SDHC_PRIORITY);
+ }
+}
+
+/**
+ * @brief Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop(SDCDriver *sdcp) {
+
+ if (sdcp->state != BLK_STOP) {
+ /* TODO: Should we perform a reset (RSTA) before putting the
+ peripheral to sleep? */
+
+ /* Disable the card clock */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Turn off interrupts */
+ nvicDisableVector(SDHC_IRQn);
+ SDHC->IRQSIGEN = 0;
+ SDHC->IRQSTATEN &= ~( SDHC_IRQSTATEN_CINTSEN |
+ SDHC_IRQSTATEN_CINSEN |
+ SDHC_IRQSTATEN_CRMSEN );
+
+ /* Disable the clock to the SDHC peripheral block */
+ SIM->SCGC3 &= ~( SIM_SCGC3_SDHC );
+ }
+}
+
+/**
+ * @brief Starts the SDIO clock and sets it to init mode (400kHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start_clk(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ /* Stop the card clock (it should already be stopped) */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Change the divisor and DTOCV for a 400kHz card closk */
+ uint32_t sysctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_300ms_400kHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 400000));
+
+ /* Restart the clock */
+ enable_clock_when_stable(sysctl);
+
+ /* Reset any protocol machinery; this also runs the clock for 80
+ cycles without any data bits to help initalize the card's state
+ (the Kinetis peripheral docs say that this is required after card
+ insertion or power-on, but the abridged SDHC specifications I
+ have don't seem to mention it) */
+ SDHC->SYSCTL |= SDHC_SYSCTL_INITA;
+
+ TRACE(9, SDHC->PRSSTAT);
+}
+
+/**
+ * @brief Sets the SDIO clock to data mode (25MHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] clk the clock mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
+
+ (void)sdcp;
+
+ /* Stop the card clock */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Change the divisor */
+ uint32_t ctl;
+ switch (clk) {
+ default:
+ case SDC_CLK_25MHz:
+ ctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_700ms_25MHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 25000000));
+ break;
+ case SDC_CLK_50MHz:
+ ctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_700ms_50MHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 50000000));
+ break;
+ }
+
+ /* Restart the clock */
+ enable_clock_when_stable(ctl);
+}
+
+/**
+ * @brief Stops the SDIO clock.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop_clk(SDCDriver *sdcp) {
+ (void)sdcp;
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+}
+
+/**
+ * @brief Switches the bus to 4 bit or 8 bit mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] mode bus mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
+ (void)sdcp;
+ uint32_t proctl = SDHC->PROCTL & ~( SDHC_PROCTL_DTW_MASK );
+
+ switch (mode) {
+ case SDC_MODE_1BIT:
+ proctl |= SDHC_PROCTL_DTW_1BIT;
+ break;
+ case SDC_MODE_4BIT:
+ proctl |= SDHC_PROCTL_DTW_4BIT;
+ break;
+ case SDC_MODE_8BIT:
+ proctl |= SDHC_PROCTL_DTW_8BIT;
+ break;
+ default:
+ osalDbgAssert(false, "invalid bus mode");
+ break;
+ }
+
+ SDHC->PROCTL = proctl;
+}
+
+/**
+ * @brief Sends an SDIO command with no response expected.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ *
+ * @notapi
+ */
+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=0 */
+ SDHC_XFERTYP_RSPTYP_NONE;
+
+ send_and_wait_cmd(sdcp, xfer);
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected.
+ * @note The CRC is not verified.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=0 */
+ SDHC_XFERTYP_RSPTYP_48;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ *resp = SDHC->CMDRSP[0];
+
+ return waited;
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=1, CCCEN=1 */
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ *resp = SDHC->CMDRSP[0];
+ TRACE(11, *resp);
+
+ return waited;
+}
+
+/**
+ * @brief Sends an SDIO command with a long response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (four words)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+
+ /* In response format R2 (the 136-bit or "long" response) the CRC7
+ field is valid, but the command index field is set to all 1s, so
+ we need to disable the command index check function (CICEN=0). */
+
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=1 */
+ SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_136;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ resp[0] = SDHC->CMDRSP[0];
+ resp[1] = SDHC->CMDRSP[1];
+ resp[2] = SDHC->CMDRSP[2];
+ resp[3] = SDHC->CMDRSP[3];
+
+ return waited;
+}
+
+/**
+ * @brief Reads one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[out] buf pointer to the read buffer
+ * @param[in] n number of blocks to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n) {
+ uint32_t cmdx = (n == 1)?
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_SINGLE_BLOCK) :
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_MULTIPLE_BLOCK);
+ cmdx |= SDHC_XFERTYP_DTDSEL;
+
+ return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief Writes one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to write
+ * @param[out] buf pointer to the write buffer
+ * @param[in] n number of blocks to write
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n) {
+ uint32_t cmdx = (n == 1)?
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_BLOCK) :
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_MULTIPLE_BLOCK);
+
+ return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief Waits for card idle condition.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdc_lld_sync(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ return HAL_SUCCESS;
+}
+
+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument) {
+ uintptr_t bufaddr = (uintptr_t)buf;
+
+ osalDbgCheck((bufaddr & 0x03) == 0); /* Must be 32-bit aligned */
+ osalDbgCheck(bytes > 0);
+ osalDbgCheck(bytes < 4096);
+
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+ "SDHC interface not ready");
+
+ TRACE(5, argument);
+
+ /* Store the cmd argument and DMA start address */
+ SDHC->CMDARG = argument;
+ SDHC->DSADDR = bufaddr;
+
+ /* We're reading one block, of a (possibly) nonstandard size */
+ SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(bytes);
+
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) | /* the command */
+ SDHC_XFERTYP_DTDSEL | /* read transfer (card -> host) */
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48 |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN; /* DMA-assisted data transfer */
+
+ return send_and_wait_transfer(sdcp, xfer);
+}
+
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return ( SDHC->PRSSTAT & SDHC_PRSSTAT_CLSL )? true : false;
+}
+
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+ (void)sdcp;
+ return false;
+}
+
+#endif /* HAL_USE_SDC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h new file mode 100644 index 0000000..9f77bf6 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h @@ -0,0 +1,202 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ Copyright (C) 2017 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc_lld.h
+ * @brief PLATFORM SDC subsystem low level driver header.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define SDHC_XFERTYP_CMDTYP_NORMAL SDHC_XFERTYP_CMDTYP(0)
+#define SDHC_XFERTYP_CMDTYP_SUSPEND SDHC_XFERTYP_CMDTYP(1)
+#define SDHC_XFERTYP_CMDTYP_RESUME SDHC_XFERTYP_CMDTYP(2)
+#define SDHC_XFERTYP_CMDTYP_ABORT SDHC_XFERTYP_CMDTYP(3)
+
+#define SDHC_XFERTYP_RSPTYP_NONE SDHC_XFERTYP_RSPTYP(0) /* no response */
+#define SDHC_XFERTYP_RSPTYP_136 SDHC_XFERTYP_RSPTYP(1) /* 136-bit response */
+#define SDHC_XFERTYP_RSPTYP_48 SDHC_XFERTYP_RSPTYP(2) /* 48-bit response */
+#define SDHC_XFERTYP_RSPTYP_48b SDHC_XFERTYP_RSPTYP(3) /* 48-bit plus busy */
+
+#define SDHC_PROCTL_DTW_1BIT SDHC_PROCTL_DTW(0)
+#define SDHC_PROCTL_DTW_4BIT SDHC_PROCTL_DTW(1)
+#define SDHC_PROCTL_DTW_8BIT SDHC_PROCTL_DTW(2)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief SDC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDC1 is included.
+ * @note The default is @p TRUE if HAL_USE_SDC is set.
+ */
+#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)
+#define PLATFORM_SDC_USE_SDC1 TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of card flags.
+ */
+typedef uint32_t sdcmode_t;
+
+/**
+ * @brief SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
+/**
+ * @brief Type of a structure representing an SDC driver.
+ */
+typedef struct SDCDriver SDCDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Working area for memory consuming operations.
+ * @note It is mandatory for detecting MMC cards bigger than 2GB else it
+ * can be @p NULL.
+ * @note Memory pointed by this buffer is only used by @p sdcConnect(),
+ * afterward it can be reused for other purposes.
+ */
+ uint8_t *scratchpad;
+ /**
+ * @brief Bus width.
+ */
+ sdcbusmode_t bus_width;
+ /* End of the mandatory fields.*/
+} SDCConfig;
+
+/**
+ * @brief @p SDCDriver specific methods.
+ */
+#define _sdc_driver_methods \
+ _mmcsd_block_device_methods
+
+/**
+ * @extends MMCSDBlockDeviceVMT
+ *
+ * @brief @p SDCDriver virtual methods table.
+ */
+struct SDCDriverVMT {
+ _sdc_driver_methods
+};
+
+/**
+ * @brief Structure representing an SDC driver.
+ */
+struct SDCDriver {
+ /**
+ * @brief Virtual Methods Table.
+ */
+ const struct SDCDriverVMT *vmt;
+ _mmcsd_block_device_data
+ /**
+ * @brief Current configuration data.
+ */
+ const SDCConfig *config;
+ /**
+ * @brief Various flags regarding the mounted card.
+ */
+ sdcmode_t cardmode;
+ /**
+ * @brief Errors flags.
+ */
+ sdcflags_t errors;
+ /**
+ * @brief Card RCA.
+ */
+ uint32_t rca;
+ /* End of the mandatory fields.*/
+
+ /* Platform specific fields */
+ thread_reference_t thread;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__)
+extern SDCDriver SDCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sdc_lld_init(void);
+ void sdc_lld_start(SDCDriver *sdcp);
+ void sdc_lld_stop(SDCDriver *sdcp);
+ void sdc_lld_start_clk(SDCDriver *sdcp);
+ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
+ void sdc_lld_stop_clk(SDCDriver *sdcp);
+ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
+ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
+ bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument);
+ bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n);
+ bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n);
+ bool sdc_lld_sync(SDCDriver *sdcp);
+ bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+ bool sdc_lld_is_write_protected(SDCDriver *sdcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDC == TRUE */
+
+#endif /* HAL_SDC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c index c80cf22..a1b6632 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+ Copyright (C) 2017 Wim Lewis
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -50,6 +51,18 @@ SerialDriver SD2; SerialDriver SD3;
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -95,33 +108,37 @@ static void serve_error_interrupt(SerialDriver *sdp) { UART_w_TypeDef *u = &(sdp->uart);
uint8_t s1 = *(u->s1_p);
- /* S1 bits are write-1-to-clear for UART0 on KL2x. */
- /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+ /* Clearing on K20x, K60x, and KL2x/UART>0 is done by reading S1 and
* then reading D.*/
-#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
- if(sdp == &SD1) {
- if(s1 & UARTx_S1_IDLE) {
- *(u->s1_p) |= UARTx_S1_IDLE;
- }
+ if(s1 & UARTx_S1_IDLE) {
+ (void)*(u->d_p);
+ }
- if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- set_error(sdp, s1);
- *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- }
- return;
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ (void)*(u->d_p);
}
-#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+}
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+static void serve_error_interrupt_uart0(void) {
+ SerialDriver *sdp = &SD1;
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ /* S1 bits are write-1-to-clear for UART0 on KL2x. */
if(s1 & UARTx_S1_IDLE) {
- (void)*(u->d_p);
+ *(u->s1_p) |= UARTx_S1_IDLE;
}
if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
set_error(sdp, s1);
- (void)*(u->d_p);
+ *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
}
}
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
/**
* @brief Common IRQ handler.
@@ -161,6 +178,12 @@ static void serve_interrupt(SerialDriver *sdp) { }
}
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ serve_error_interrupt_uart0();
+ return;
+ }
+#endif
serve_error_interrupt(sdp);
}
@@ -184,29 +207,28 @@ static void preload(SerialDriver *sdp) { /**
* @brief Driver output notification.
*/
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
+static void notify(io_queue_t *qp)
{
- (void)qp;
- preload(&SD1);
+ preload(qp->q_link);
}
-#endif
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
+/**
+ * @brief Common driver initialization, except LP.
+ */
+static void sd_lld_init_driver(SerialDriver *SDn, UART_TypeDef *UARTn) {
+ /* Driver initialization.*/
+ sdObjectInit(SDn, NULL, notify);
+ SDn->uart.bdh_p = &(UARTn->BDH);
+ SDn->uart.bdl_p = &(UARTn->BDL);
+ SDn->uart.c1_p = &(UARTn->C1);
+ SDn->uart.c2_p = &(UARTn->C2);
+ SDn->uart.c3_p = &(UARTn->C3);
+ SDn->uart.c4_p = &(UARTn->C4);
+ SDn->uart.s1_p = (volatile uint8_t *)&(UARTn->S1);
+ SDn->uart.s2_p = &(UARTn->S2);
+ SDn->uart.d_p = &(UARTn->D);
+ SDn->uart.uart_p = UARTn;
}
-#endif
/**
* @brief Common UART configuration.
@@ -240,9 +262,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) { }
#endif /* KINETIS_SERIAL_USE_UART0 */
-#elif defined(K20x) /* KL2x */
+#elif defined(K20x) || defined(K60x) || defined(MK66F18) /* KL2x */
- /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+ /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x and K60x. */
#if KINETIS_SERIAL_USE_UART0
if(sdp == &SD1)
divisor = KINETIS_SYSCLK_FREQUENCY;
@@ -260,9 +282,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) { *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
*(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
-#if defined(K20x)
+#if defined(K20x) || defined(K60x)
*(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
-#endif /* K20x */
+#endif /* K20x, K60x */
/* Line settings. */
*(uart->c1_p) = 0;
@@ -300,12 +322,40 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) { }
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD5);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD6);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
#if KINETIS_HAS_SERIAL_ERROR_IRQ
#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
+#if defined(KL2x)
+ serve_error_interrupt_uart0();
+#else
serve_error_interrupt(&SD1);
+#endif
OSAL_IRQ_EPILOGUE();
}
#endif
@@ -326,6 +376,30 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) { }
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD5);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD6);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
/*===========================================================================*/
@@ -341,19 +415,11 @@ void sd_lld_init(void) { #if KINETIS_SERIAL_USE_UART0
/* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
#if ! KINETIS_SERIAL0_IS_LPUART
- SD1.uart.bdh_p = &(UART0->BDH);
- SD1.uart.bdl_p = &(UART0->BDL);
- SD1.uart.c1_p = &(UART0->C1);
- SD1.uart.c2_p = &(UART0->C2);
- SD1.uart.c3_p = &(UART0->C3);
- SD1.uart.c4_p = &(UART0->C4);
- SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
- SD1.uart.s2_p = &(UART0->S2);
- SD1.uart.d_p = &(UART0->D);
+ sd_lld_init_driver(&SD1, UART0);
#else /* ! KINETIS_SERIAL0_IS_LPUART */
/* little endian! */
+ sdObjectInit(&SD1, NULL, notify);
SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -377,20 +443,11 @@ void sd_lld_init(void) { #if KINETIS_SERIAL_USE_UART1
/* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
#if ! KINETIS_SERIAL1_IS_LPUART
- SD2.uart.bdh_p = &(UART1->BDH);
- SD2.uart.bdl_p = &(UART1->BDL);
- SD2.uart.c1_p = &(UART1->C1);
- SD2.uart.c2_p = &(UART1->C2);
- SD2.uart.c3_p = &(UART1->C3);
- SD2.uart.c4_p = &(UART1->C4);
- SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
- SD2.uart.s2_p = &(UART1->S2);
- SD2.uart.d_p = &(UART1->D);
- SD2.uart.uart_p = UART1;
+ sd_lld_init_driver(&SD2, UART1);
#else /* ! KINETIS_SERIAL1_IS_LPUART */
/* little endian! */
+ sdObjectInit(&SD2, NULL, notify);
SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -406,19 +463,20 @@ void sd_lld_init(void) { #endif /* KINETIS_SERIAL_USE_UART1 */
#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart.bdh_p = &(UART2->BDH);
- SD3.uart.bdl_p = &(UART2->BDL);
- SD3.uart.c1_p = &(UART2->C1);
- SD3.uart.c2_p = &(UART2->C2);
- SD3.uart.c3_p = &(UART2->C3);
- SD3.uart.c4_p = &(UART2->C4);
- SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
- SD3.uart.s2_p = &(UART2->S2);
- SD3.uart.d_p = &(UART2->D);
- SD3.uart.uart_p = UART2;
+ sd_lld_init_driver(&SD3, UART2);
#endif /* KINETIS_SERIAL_USE_UART2 */
+
+#if KINETIS_SERIAL_USE_UART3
+ sd_lld_init_driver(&SD4, UART3);
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+ sd_lld_init_driver(&SD5, UART4);
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+ sd_lld_init_driver(&SD6, UART5);
+#endif /* KINETIS_SERIAL_USE_UART5 */
}
/**
@@ -505,6 +563,33 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { }
#endif /* KINETIS_SERIAL_USE_UART2 */
+#if KINETIS_SERIAL_USE_UART3
+ if (sdp == &SD4) {
+ SIM->SCGC4 |= SIM_SCGC4_UART3;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART3Status_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+ nvicEnableVector(UART3Error_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+ if (sdp == &SD5) {
+ SIM->SCGC1 |= SIM_SCGC1_UART4;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART4Status_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+ nvicEnableVector(UART4Error_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+ if (sdp == &SD6) {
+ SIM->SCGC1 |= SIM_SCGC1_UART5;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART5Status_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+ nvicEnableVector(UART5Error_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART5 */
+
}
/* Configures the peripheral.*/
@@ -575,6 +660,30 @@ void sd_lld_stop(SerialDriver *sdp) { SIM->SCGC4 &= ~SIM_SCGC4_UART2;
}
#endif
+
+#if KINETIS_SERIAL_USE_UART3
+ if (sdp == &SD4) {
+ nvicDisableVector(UART3Status_IRQn);
+ nvicDisableVector(UART3Error_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART3;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART4
+ if (sdp == &SD5) {
+ nvicDisableVector(UART4Status_IRQn);
+ nvicDisableVector(UART4Error_IRQn);
+ SIM->SCGC1 &= ~SIM_SCGC1_UART4;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART5
+ if (sdp == &SD6) {
+ nvicDisableVector(UART5Status_IRQn);
+ nvicDisableVector(UART5Error_IRQn);
+ SIM->SCGC1 &= ~SIM_SCGC1_UART5;
+ }
+#endif
}
}
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h index f11c063..3cb6d2b 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h @@ -60,6 +60,27 @@ #if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
#define KINETIS_SERIAL_USE_UART2 FALSE
#endif
+/**
+ * @brief SD4 driver enable switch.
+ * @details If set to @p TRUE the support for SD4 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART3 FALSE
+#endif
+/**
+ * @brief SD5 driver enable switch.
+ * @details If set to @p TRUE the support for SD5 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART4 FALSE
+#endif
+/**
+ * @brief SD6 driver enable switch.
+ * @details If set to @p TRUE the support for SD6 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART5 FALSE
+#endif
/**
* @brief UART0 interrupt priority level setting.
@@ -83,6 +104,27 @@ #endif
/**
+ * @brief UART3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART3_PRIORITY 12
+#endif
+
+/**
+ * @brief UART4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART4_PRIORITY 12
+#endif
+
+/**
+ * @brief UART5 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART5_PRIORITY 12
+#endif
+
+/**
* @brief UART0 clock source.
*/
#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
@@ -115,8 +157,21 @@ #error "UART2 not present in the selected device"
#endif
+#if KINETIS_SERIAL_USE_UART3 && !KINETIS_HAS_SERIAL3
+#error "UART3 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !KINETIS_HAS_SERIAL4
+#error "UART4 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !KINETIS_HAS_SERIAL5
+#error "UART5 not present in the selected device"
+#endif
+
#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
- KINETIS_SERIAL_USE_UART2)
+ KINETIS_SERIAL_USE_UART2 || KINETIS_SERIAL_USE_UART3 || \
+ KINETIS_SERIAL_USE_UART4 || KINETIS_SERIAL_USE_UART5)
#error "Serial driver activated but no UART peripheral assigned"
#endif
@@ -203,6 +258,18 @@ extern SerialDriver SD2; extern SerialDriver SD3;
#endif
+#if KINETIS_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c index e8d9778..a01b92e 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c @@ -158,7 +158,7 @@ void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n) USBInEndpointState *isp = epc->in_state;
bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
-
+
if (n > (size_t)epc->in_maxsize)
n = (size_t)epc->in_maxsize;
@@ -244,19 +244,16 @@ OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) { {
case BDT_PID_SETUP: // SETUP
{
- /* Clear any pending IN stuff */
- _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
- _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
- /* Also in the chibios state machine */
+ /* Clear receiving in the chibios state machine */
(usbp)->receiving &= ~1;
- /* After a SETUP, IN is always DATA1 */
- usbp->epc[ep]->in_state->data_bank = DATA1;
-
- /* Call SETUP function (ChibiOS core), which sends back stuff */
+ /* Call SETUP function (ChibiOS core), which prepares
+ * for send or receive and releases the buffer
+ */
_usb_isr_invoke_setup_cb(usbp, ep);
- /* Buffer is released by the above callback. */
- /* from Paul: "unfreeze the USB, now that we're ready" */
- USB0->CTL = USBx_CTL_USBENSOFEN;
+ /* When a setup packet is received, tx is suspended,
+ * so it needs to be resumed here.
+ */
+ USB0->CTL &= ~USBx_CTL_TXSUSPENDTOKENBUSY;
} break;
case BDT_PID_IN: // IN
{
@@ -398,9 +395,10 @@ void usb_lld_init(void) { #if KINETIS_USB_USE_USB0
+ /* Set USB clock source to MCGPLLCLK, MCGFLLCLK, USB1 PFD, or IRC48M */
SIM->SOPT2 |= SIM_SOPT2_USBSRC;
-#if defined(K20x5) || defined(K20x7)
+#if defined(K20x5) || defined(K20x7) || defined(MK66F18)
#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
@@ -409,6 +407,8 @@ void usb_lld_init(void) { #elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+#if !defined(MK66F18)
+ /* Note: We don't need this for MK66F18, we can use IRC48M clock for USB */
#define KINETIS_USBCLK_FREQUENCY 48000000UL
uint32_t i,j;
for(i=0; i < 2; i++) {
@@ -421,11 +421,18 @@ void usb_lld_init(void) { }
usbfrac_match_found:
osalDbgAssert(i<2 && j <8,"USB Init error");
+#endif
#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
#error USB clock setting not implemented for this KINETIS_MCG_MODE
#endif /* KINETIS_MCG_MODE == ... */
+#if defined(MK66F18)
+ /* Switch from default MCGPLLCLK to IRC48M for USB */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+ SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
+#endif
+
#elif defined(KL25) || defined (KL26) || defined(KL27)
/* No extra clock dividers for USB clock */
@@ -455,9 +462,15 @@ void usb_lld_start(USBDriver *usbp) { _bdt[i].addr=0;
}
+#if defined(MK66F18)
+ /* Disable the USB current limiter */
+ SIM->USBPHYCTL |= SIM_USBPHYCTL_USBDISILIM;
+#endif
+
/* Enable Clock */
#if KINETIS_USB0_IS_USBOTG
SIM->SCGC4 |= SIM_SCGC4_USBOTG;
+
#else /* KINETIS_USB0_IS_USBOTG */
SIM->SCGC4 |= SIM_SCGC4_USBFS;
#endif /* KINETIS_USB0_IS_USBOTG */
@@ -728,9 +741,23 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { }
/* Release the buffer
* Setup packet is always DATA0
- * Initialize buffers so current expects DATA0 & opposite DATA1 */
+ * Release the current DATA0 buffer
+ */
bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
- _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ /* If DATA1 was expected, then the states are out of sync.
+ * So reset the other buffer too, and set it as DATA1.
+ * This should not happen in normal cases, but is possible in
+ * error situations. NOTE: it's possible that this is too late
+ * and the next packet has already been received and dropped, but
+ * there's nothing that we can do about that anymore at this point.
+ */
+ if (os->data_bank == DATA1)
+ {
+ bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)];
+ bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ }
+ /* After a SETUP, both in and out are always DATA1 */
+ usbp->epc[ep]->in_state->data_bank = DATA1;
os->data_bank = DATA1;
}
@@ -762,8 +789,22 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { * @notapi
*/
void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
- (void)ep;
+ if (ep == 0 && usbp->ep0state == USB_EP0_IN_SENDING_STS) {
+ /* When a status packet is about to be sent on endpoint 0 the
+ * next packet will be a setup packet, which means that the
+ * buffer we expect after this should be DATA0, and the following
+ * DATA1. Since no out packets should be in flight at this time
+ * it's safe to initialize the buffers according to the expectations
+ * here.
+ */
+ const USBEndpointConfig* epc = usbp->epc[ep];
+ bd_t * bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even)];
+ bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even^ODD)];
+
+ bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+ epc->out_state->data_bank = DATA0;
+ }
usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
}
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h index 961490e..bd4eb39 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h @@ -76,6 +76,13 @@ #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
#endif
+/**
+ * @brief Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -97,6 +104,10 @@ #error "KINETIS_USB_IRQ_VECTOR not defined"
#endif
+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)
+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -394,6 +405,18 @@ struct USBDriver { #endif /* KINETIS_USB0_IS_USBOTG */
#endif
+/**
+ * @brief Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp) \
+ do{ \
+ USB0->CTL |= USBx_CTL_RESUME; \
+ osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \
+ USB0->CTL &= ~USBx_CTL_RESUME; \
+ } while (false)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_lld.c new file mode 100644 index 0000000..c9cd224 --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.c @@ -0,0 +1,243 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK66F18/hal_lld.c
+ * @brief Kinetis MK66F18 HAL Driver subsystem low level driver source template.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used,section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+ 0xFF, /* NV_BACKKEY3: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY2: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY1: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY0: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY7: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY6: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY5: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY4: KEY=0xFF */
+ 0xFF, /* NV_FPROT3: PROT=0xFF */
+ 0xFF, /* NV_FPROT2: PROT=0xFF */
+ 0xFF, /* NV_FPROT1: PROT=0xFF */
+ 0xFF, /* NV_FPROT0: PROT=0xFF */
+ 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+ 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+ NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ 0xFF,
+ 0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ * @todo Use a macro to define the system clock frequency.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+#if defined(MK66F18)
+ /* Disable the MPU by default */
+ SYSMPU->CESR &= ~SYSMPU_CESR_VLD_MASK;
+#endif
+
+}
+
+/**
+ * @brief MK66F18 clock initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ * @todo This function needs to be more generic.
+ *
+ * @special
+ */
+void MK66F18_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+ /* Disable the watchdog */
+ WDOG->UNLOCK = 0xC520;
+ WDOG->UNLOCK = 0xD928;
+ WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
+
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+ /* Set clock dividers */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+#if defined(MK66F18)
+ SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3-1) |
+#endif
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] = 0;
+ PORTA->PCR[19] = 0;
+
+ /*
+ * Start in FEI mode
+ */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* TODO: need to add more flexible calculation, specially regarding
+ * divisors which may not be available depending on the XTAL
+ * frequency, which would required other registers to be modified.
+ */
+ /* Enable OSC, low power mode */
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
+ else
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
+
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
+
+ /* Wait for crystal oscillator to begin */
+ while (!(MCG->S & MCG_S_OSCINIT0));
+
+ /* Wait for the FLL to use the oscillator */
+ while (MCG->S & MCG_S_IREFST);
+
+ /* Wait for the MCGOUTCLK to use the oscillator */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
+
+ /*
+ * Now in FBE mode
+ */
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /*
+ * Config PLL input for 2 MHz
+ * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+ */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
+
+ /*
+ * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+ */
+ for(i = 24; i < 56; i++)
+ {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+ {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
+
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+ /* Wait for PLL to start using crystal as its input, and to lock */
+ while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
+
+ /*
+ * Now in PBE mode
+ */
+ /* Set the PLL dividers for the different clocks */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+
+ /* Configure peripherals to use MCGPLLCLK */
+ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
+
+ /* Switch to PLL as clock source */
+ MCG->C1 = MCG_C1_CLKS(0);
+
+ /* Wait for PLL clock to be used */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
+
+ /*
+ * Now in PEE mode
+ */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_lld.h new file mode 100644 index 0000000..4faf575 --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.h @@ -0,0 +1,322 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK66F18/hal_lld.h
+ * @brief Kinetis MK66F18 HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H_
+#define HAL_LLD_H_
+
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
+/**
+ * @brief Clock divider for core/system clocks (OUTDIV1).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for bus clock (OUTDIV2).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz bus clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV2 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for FlexBus clock (OUTDIV3).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV3) || defined(__DOXYGEN__)
+ #if defined(KINETIS_FLEXBUSCLK_FREQUENCY) && KINETIS_FLEXBUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV3 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLEXBUSCLK_FREQUENCY)
+ #else
+ /* If no FlexBus frequency provided, use bus speed divider */
+ #define KINETIS_CLKDIV1_OUTDIV3 KINETIS_CLKDIV1_OUTDIV2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for flash clock (OUTDIV4).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 24 MHz flash clock
+ * from a 96 MHz PLL output
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 4
+ #endif
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
+#endif
+
+/**
+ * @brief MCU bus clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
+#endif
+
+/**
+ * @brief MCU flash clock frequency.
+ */
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+ #error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+ #error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+ #error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+ #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+ #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+ #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+ KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV3) && \
+ KINETIS_CLKDIV1_OUTDIV3 >= 1 && KINETIS_CLKDIV1_OUTDIV3 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV3 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void MK66F18_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c new file mode 100644 index 0000000..f39823d --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c @@ -0,0 +1,390 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK66F18/pwm_lld.c
+ * @brief KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer FTM0 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer FTM1 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer FTM2 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->ftm->SC;
+ pwmp->ftm->SC = sr&(~FTM_SC_TOF);
+
+ if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
+ ((sr & FTM_SC_TOIE) != 0) &&
+ (pwmp->config->callback != NULL)) {
+ pwmp->config->callback(pwmp);
+ }
+
+ uint8_t n=0;
+ for(n=0;n<pwmp->channels;n++) {
+ sr = pwmp->ftm->CHANNEL[n].CnSC;
+ pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
+ if (((sr & FTM_CnSC_CHF) != 0) &&
+ ((sr & FTM_CnSC_CHIE) != 0) &&
+ (pwmp->config->channels[n].callback != NULL)) {
+ pwmp->config->channels[n].callback(pwmp);
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0
+/**
+ * @brief FTM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM0 */
+
+#if KINETIS_PWM_USE_FTM1
+/**
+ * @brief FTM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM1 */
+
+#if KINETIS_PWM_USE_FTM2
+/**
+ * @brief FTM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_FTM0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = KINETIS_FTM0_CHANNELS;
+ PWMD1.ftm = FTM0;
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = KINETIS_FTM1_CHANNELS;
+ PWMD2.ftm = FTM1;
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = KINETIS_FTM2_CHANNELS;
+ PWMD3.ftm = FTM2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ uint16_t psc;
+ uint8_t i=0;
+
+ if (pwmp->state == PWM_STOP) {
+ /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM0;
+ nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM1;
+ nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 |= SIM_SCGC3_FTM2;
+ nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
+ }
+#endif
+ }
+ pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
+ pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
+ |FTM_SYNC_SWSYNC_MASK;
+ pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
+ | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
+ pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
+
+ pwmp->ftm->CNTIN = 0x0000;
+ //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
+ pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
+
+ /* Prescaler value calculation.*/
+ psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+ //~ /* Prescaler must be power of two between 1 and 128.*/
+ osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+ //~ /* Prescaler register value determination.
+ //~ Prescaler register value conveniently corresponds to bit position,
+ //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+ for (i = 0; i < 8; i++) {
+ if (psc == (unsigned)(1 << i)) {
+ break;
+ }
+ }
+
+ /* Set prescaler and clock mode.
+ This also sets the following:
+ CPWMS up-counting mode
+ Timer overflow interrupt disabled
+ DMA disabled.*/
+ pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
+ /* Configure period */
+ pwmp->ftm->MOD = pwmp->period-1;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ /* If in ready state then disables the PWM clock.*/
+ if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
+ nvicDisableVector(FTM0_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
+ nvicDisableVector(FTM1_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
+ nvicDisableVector(FTM2_IRQn);
+ }
+#endif
+ /* Disable FTM counter.*/
+ pwmp->ftm->SC = 0;
+ pwmp->ftm->MOD = 0;
+ }
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+ uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+ switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ mode |= FTM_CnSC_ELSB;
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+ mode |= FTM_CnSC_ELSA;
+ break;
+ }
+
+ if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
+ mode |= FTM_CnSC_CHIE;
+
+ pwmp->ftm->CHANNEL[channel].CnSC = mode;
+ pwmp->ftm->CHANNEL[channel].CnV = width;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ pwmp->ftm->CHANNEL[channel].CnSC = 0;
+ pwmp->ftm->CHANNEL[channel].CnV = 0;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC |= FTM_SC_TOIE;
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC &= ~FTM_SC_TOIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h new file mode 100644 index 0000000..9332e34 --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h @@ -0,0 +1,270 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK66F18/pwm_lld.h
+ * @brief KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef HAL_PWM_LLD_H_
+#define HAL_PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 8
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_FTM0)
+ #define KINETIS_PWM_USE_FTM0 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM1)
+ #define KINETIS_PWM_USE_FTM1 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM2)
+ #define KINETIS_PWM_USE_FTM2 FALSE
+#endif
+
+/**
+ * @brief FTM0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM0_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM1_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM2_PRIORITY 12
+#endif
+
+/** @} */
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ * enabled.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
+#error "PWM driver activated but no FTM peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the FTM registers block.
+ */
+ FTM_TypeDef *ftm;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ do { \
+ (pwmp)->ftm->MOD = ((period) - 1); \
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
+ } while(0)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* HAL_PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c new file mode 100644 index 0000000..29ab4e8 --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c @@ -0,0 +1,539 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/spi_lld.c
+ * @brief KINETIS SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
+#define KINETIS_SPI0_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
+#define KINETIS_SPI0_TX_DMA_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
+#define KINETIS_SPI1_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
+#define KINETIS_SPI1_TX_DMA_CHANNEL 1
+#endif
+
+#if KINETIS_SPI_USE_SPI0
+#define DMAMUX_SPI_RX_SOURCE 16
+#define DMAMUX_SPI_TX_SOURCE 17
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+#define DMAMUX_SPI_RX_SOURCE 18
+#define DMAMUX_SPI_TX_SOURCE 19
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief SPI0 driver identifier.*/
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/** @brief SPI1 driver identifier.*/
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/* Use a dummy byte as the source/destination when a buffer is not provided */
+/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
+static volatile uint16_t dmaRxDummy;
+static uint16_t dmaTxDummy = 0xFFFF;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void spi_start_xfer(SPIDriver *spip, bool polling)
+{
+ /*
+ * Enable the DSPI peripheral in master mode.
+ * Clear the TX and RX FIFOs.
+ * */
+ spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
+
+ /* If we are not polling then enable DMA */
+ if (!polling) {
+
+ /* Enable receive dma and transmit dma */
+ spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
+ SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
+
+ /* Configure RX DMA */
+ if (spip->rxbuf) {
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
+ } else {
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
+ }
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+ /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
+ DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+ /* Configure TX DMA */
+ if (spip->txbuf) {
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
+ } else {
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
+ }
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+ /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
+ DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
+ }
+}
+
+static void spi_stop_xfer(SPIDriver *spip)
+{
+ /* Halt the DSPI peripheral */
+ spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
+
+ /* Clear all the flags which are currently set. */
+ spip->spi->SR |= spip->spi->SR;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID1);
+
+ _spi_isr_code(&SPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID2);
+
+ _spi_isr_code(&SPID2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+#if KINETIS_SPI_USE_SPI0
+ spiObjectInit(&SPID1);
+#endif
+#if KINETIS_SPI_USE_SPI1
+ spiObjectInit(&SPID2);
+#endif
+}
+
+/**
+ * @brief Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (spip->state == SPI_STOP) {
+
+#if KINETIS_SPI_USE_SPI0
+ if (&SPID1 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI0;
+
+ SPID1.spi = SPI0;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI1;
+
+ SPID2.spi = SPI1;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
+ nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
+
+ SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
+ SIM->SCGC7 |= SIM_SCGC7_DMA;
+
+ /* Clear DMA error flags */
+ DMA->ERR = 0x0F;
+
+#if KINETIS_SPI_USE_SPI0
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+ }
+}
+
+/**
+ * @brief Deactivates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+ /* If in ready state then disables the SPI clock.*/
+ if (spip->state == SPI_READY) {
+
+ nvicDisableVector(DMA0_IRQn);
+
+ SIM->SCGC7 &= ~SIM_SCGC7_DMA;
+ SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
+
+#if KINETIS_SPI_USE_SPI0
+ if (&SPID1 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+
+ /* Disable the clock for SPI0 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+
+ /* Disable the clock for SPI1 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
+#endif
+ }
+}
+
+/**
+ * @brief Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+ palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+ palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ * idle words on the SPI bus and ignores the received data.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+ spip->count = n;
+ spip->rxbuf = NULL;
+ spip->txbuf = NULL;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ * operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[in] txbuf the pointer to the transmit buffer
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf) {
+
+ spip->count = n;
+ spip->rxbuf = rxbuf;
+ spip->txbuf = txbuf;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+ spip->count = n;
+ spip->rxbuf = NULL;
+ spip->txbuf = (void *)txbuf;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+ spip->count = n;
+ spip->rxbuf = rxbuf;
+ spip->txbuf = NULL;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ * synchronization method. This function is useful when exchanging
+ * small amount of data on high speed channels, usually in this
+ * situation is much more efficient just wait for completion using
+ * polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] frame the data frame to send over the SPI bus
+ * @return The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+
+ spi_start_xfer(spip, true);
+
+ spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
+
+ while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
+ ;
+
+ frame = spip->spi->POPR;
+
+ spi_stop_xfer(spip);
+
+ return frame;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h new file mode 100644 index 0000000..0cf108e --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h @@ -0,0 +1,261 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/spi_lld.h
+ * @brief KINETIS SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef HAL_SPI_LLD_H_
+#define HAL_SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SPI0 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI0 FALSE
+#endif
+
+/**
+ * @brief SPI0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief SPI1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
+#error "SPI0 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
+#error "Only one SPI peripheral can be enabled"
+#endif
+
+#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
+#error "SPI driver activated but no SPI peripheral assigned"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI0"
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief SPI notification callback type.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object triggering the
+ * callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ spicallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief The chip select line port - when not using pcs.
+ */
+ ioportid_t ssport;
+ /**
+ * @brief The chip select line pad number - when not using pcs.
+ */
+ uint16_t sspad;
+ /**
+ * @brief SPI initialization data.
+ */
+ uint32_t tar0;
+} SPIConfig;
+
+/**
+ * @brief Structure representing a SPI driver.
+ */
+struct SPIDriver {
+ /**
+ * @brief Driver state.
+ */
+ spistate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const SPIConfig *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+ SPI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief Number of bytes/words of data to transfer.
+ */
+ size_t count;
+ /**
+ * @brief Word size in bytes.
+ */
+ size_t word_size;
+ /**
+ * @brief Pointer to the buffer with data to send.
+ */
+ const uint8_t *txbuf;
+ /**
+ * @brief Pointer to the buffer to put received data.
+ */
+ uint8_t *rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/* TAR settings for n bits at SYSCLK / 2 */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
+ SPIx_CTARn_FMSZ((n) - 1) | \
+ SPIx_CTARn_CPOL | \
+ SPIx_CTARn_CPHA | \
+ SPIx_CTARn_DBR | \
+ SPIx_CTARn_PBR(0) | \
+ SPIx_CTARn_BR(0) | \
+ SPIx_CTARn_CSSCK(0) | \
+ SPIx_CTARn_ASC(0) | \
+ SPIx_CTARn_DT(0)
+
+/* TAR settings for n bits at SYSCLK / 4096 for debugging */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
+ SPIx_CTARn_FMSZ(((n) - 1)) | \
+ SPIx_CTARn_CPOL | \
+ SPIx_CTARn_CPHA | \
+ SPIx_CTARn_PBR(0) | \
+ SPIx_CTARn_BR(0xB) | \
+ SPIx_CTARn_CSSCK(0xB) | \
+ SPIx_CTARn_ASC(0x7) | \
+ SPIx_CTARn_DT(0xB)
+
+#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
+
+#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void spi_lld_init(void);
+ void spi_lld_start(SPIDriver *spip);
+ void spi_lld_stop(SPIDriver *spip);
+ void spi_lld_select(SPIDriver *spip);
+ void spi_lld_unselect(SPIDriver *spip);
+ void spi_lld_ignore(SPIDriver *spip, size_t n);
+ void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf);
+ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* HAL_SPI_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h new file mode 100644 index 0000000..a04012c --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h @@ -0,0 +1,172 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file MK66F18/kinetis_registry.h
+ * @brief MK66F18 capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef KINETIS_REGISTRY_H_
+#define KINETIS_REGISTRY_H_
+
+#if !defined(MK66F18) || defined(__DOXYGEN__)
+#define MK66F18
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 180000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 60000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 28000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR VectorDC
+#define KINETIS_HAS_ADC1 TRUE
+#define KINETIS_ADC1_IRQ_VECTOR Vector164
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINETIS_DAC0_IRQ_VECTOR Vector120
+#define KINETIS_HAS_DAC1 TRUE
+#define KINETIS_DAC1_IRQ_VECTOR Vector160
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_DMA4_IRQ_VECTOR Vector50
+#define KINETIS_DMA5_IRQ_VECTOR Vector54
+#define KINETIS_DMA6_IRQ_VECTOR Vector58
+#define KINETIS_DMA7_IRQ_VECTOR Vector5C
+#define KINETIS_DMA8_IRQ_VECTOR Vector60
+#define KINETIS_DMA9_IRQ_VECTOR Vector64
+#define KINETIS_DMA10_IRQ_VECTOR Vector68
+#define KINETIS_DMA11_IRQ_VECTOR Vector6C
+#define KINETIS_DMA12_IRQ_VECTOR Vector70
+#define KINETIS_DMA13_IRQ_VECTOR Vector74
+#define KINETIS_DMA14_IRQ_VECTOR Vector78
+#define KINETIS_DMA15_IRQ_VECTOR Vector7C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector80
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR Vector12C
+#define KINETIS_PORTB_IRQ_VECTOR Vector130
+#define KINETIS_PORTC_IRQ_VECTOR Vector134
+#define KINETIS_PORTD_IRQ_VECTOR Vector138
+#define KINETIS_PORTE_IRQ_VECTOR Vector13C
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR VectorA0
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR VectorA4
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR VectorBC
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR VectorC4
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR VectorCC
+#define KINETIS_HAS_SERIAL3 TRUE
+#define KINETIS_SERIAL3_IRQ_VECTOR VectorD4
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorC0
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR VectorC8
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR VectorD0
+#define KINETIS_SERIAL3_ERROR_IRQ_VECTOR VectorD8
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_UARTLP FALSE
+#define KINETIS_SERIAL2_IS_LPUART FALSE
+#define KINETIS_SERIAL2_IS_UARTLP FALSE
+#define KINETIS_SERIAL3_IS_LPUART FALSE
+#define KINETIS_SERIAL3_IS_UARTLP FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR VectorAC
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+#define KINETIS_FTM3_CHANNELS 8
+
+#define KINETIS_HAS_FTM0 TRUE
+#define KINETIS_FTM0_IRQ_VECTOR VectorE8
+#define KINETIS_HAS_FTM1 TRUE
+#define KINETIS_FTM1_IRQ_VECTOR VectorEC
+#define KINETIS_HAS_FTM2 TRUE
+#define KINETIS_FTM2_IRQ_VECTOR VectorF0
+#define KINETIS_HAS_FTM3 TRUE
+#define KINETIS_FTM3_IRQ_VECTOR Vector15C
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR Vector100
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR Vector104
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR Vector108
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR Vector10C
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR Vector114
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR Vector128
+
+/* SDHC (SDC, MMC, SDIO) attributes */
+#define KINETIS_HAS_SDHC TRUE
+#define KINETIS_SDHC_IRQ_VECTOR Vector184
+
+/** @} */
+
+#endif /* KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/platform.dox b/os/hal/ports/KINETIS/MK66F18/platform.dox new file mode 100644 index 0000000..beb8f61 --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/platform.dox @@ -0,0 +1,365 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/* TODO Still need to edit this entire file */
+
+/**
+ * @defgroup MK66FX1M0_DRIVERS MK66FX1M0 Drivers
+ * @details This section describes all the supported drivers on the MK66FX1M0
+ * platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup MK66FX1M0_HAL MK66FX1M0 Initialization Support
+ * @details The MK66FX1M0 HAL support is responsible for system initialization.
+ *
+ * @section mk66fx1m0_hal_1 Supported HW resources
+ * - PLL1.
+ * - PLL2.
+ * - RCC.
+ * - Flash.
+ * .
+ * @section mk66fx1m0_hal_2 MK66FX1M0 HAL driver implementation features
+ * - PLL startup and stabilization.
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * - Flash wait states initialization based on the selected clock options.
+ * - SYSTICK initialization based on current clock and kernel required rate.
+ * - DMA support initialization.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_ADC MK66FX1M0 ADC Support
+ * @details The MK66FX1M0 ADC driver supports the ADC peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk66fx1m0_adc_1 Supported HW resources
+ * - ADC1.
+ * - ADC2.
+ * - ADC3.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_adc_2 MK66FX1M0 ADC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Streaming conversion using DMA for maximum performance.
+ * - Programmable ADC interrupt priority level.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - DMA and ADC errors detection.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_CAN MK66FX1M0 CAN Support
+ * @details The MK66FX1M0 CAN driver uses the CAN peripherals.
+ *
+ * @section mk66fx1m0_can_1 Supported HW resources
+ * - bxCAN1.
+ * .
+ * @section mk66fx1m0_can_2 MK66FX1M0 CAN driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Support for bxCAN sleep mode.
+ * - Programmable bxCAN interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_EXT MK66FX1M0 EXT Support
+ * @details The MK66FX1M0 EXT driver uses the EXTI peripheral.
+ *
+ * @section mk66fx1m0_ext_1 Supported HW resources
+ * - EXTI.
+ * .
+ * @section mk66fx1m0_ext_2 MK66FX1M0 EXT driver implementation features
+ * - Each EXTI channel can be independently enabled and programmed.
+ * - Programmable EXTI interrupts priority level.
+ * - Capability to work as event sources (WFE) rather than interrupt sources.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_GPT MK66FX1M0 GPT Support
+ * @details The MK66FX1M0 GPT driver uses the TIMx peripherals.
+ *
+ * @section mk66fx1m0_gpt_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk66fx1m0_gpt_2 MK66FX1M0 GPT driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_ICU MK66FX1M0 ICU Support
+ * @details The MK66FX1M0 ICU driver uses the TIMx peripherals.
+ *
+ * @section mk66fx1m0_icu_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk66fx1m0_icu_2 MK66FX1M0 ICU driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_MAC MK66FX1M0 MAC Support
+ * @details The MK66FX1M0 MAC driver supports the ETH peripheral.
+ *
+ * @section mk66fx1m0_mac_1 Supported HW resources
+ * - ETH.
+ * - PHY (external).
+ * .
+ * @section mk66fx1m0_mac_2 MK66FX1M0 MAC driver implementation features
+ * - Dedicated DMA operations.
+ * - Support for checksum off-loading.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_PAL MK66FX1M0 PAL Support
+ * @details The MK66FX1M0 PAL driver uses the GPIO peripherals.
+ *
+ * @section mk66fx1m0_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOE.
+ * - GPIOF.
+ * - GPIOG.
+ * - GPIOH.
+ * - GPIOI.
+ * .
+ * @section mk66fx1m0_pal_2 MK66FX1M0 PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 16 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section mk66fx1m0_pal_3 Supported PAL setup modes
+ * The MK66FX1M0 PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_INPUT_PULLDOWN.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * - @p PAL_MODE_ALTERNATE (non standard).
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section mk66fx1m0_pal_4 Suboptimal behavior
+ * The MK66FX1M0 GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Pad/port toggling operations are not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_PWM MK66FX1M0 PWM Support
+ * @details The MK66FX1M0 PWM driver uses the TIMx peripherals.
+ *
+ * @section mk66fx1m0_pwm_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk66fx1m0_pwm_2 MK66FX1M0 PWM driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Four independent PWM channels per timer.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_SDC MK66FX1M0 SDC Support
+ * @details The MK66FX1M0 SDC driver uses the SDIO peripheral.
+ *
+ * @section mk66fx1m0_sdc_1 Supported HW resources
+ * - SDIO.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_sdc_2 MK66FX1M0 SDC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_SERIAL MK66FX1M0 Serial Support
+ * @details The MK66FX1M0 Serial driver uses the USART/UART peripherals in a
+ * buffered, interrupt driven, implementation.
+ *
+ * @section mk66fx1m0_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - UART4.
+ * - UART5.
+ * - USART6.
+ * .
+ * @section mk66fx1m0_serial_2 MK66FX1M0 Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * - Programmable priority levels for each UART/USART.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_SPI MK66FX1M0 SPI Support
+ * @details The SPI driver supports the MK66FX1M0 SPI peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk66fx1m0_spi_1 Supported HW resources
+ * - SPI1.
+ * - SPI2.
+ * - SPI3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_spi_2 MK66FX1M0 SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each SPI can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each SPI.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_UART MK66FX1M0 UART Support
+ * @details The UART driver supports the MK66FX1M0 USART peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk66fx1m0_uart_1 Supported HW resources
+ * The UART driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_uart_2 MK66FX1M0 UART driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each UART/USART.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_PLATFORM_DRIVERS MK66FX1M0 Platform Drivers
+ * @details Platform support drivers. Platform drivers do not implement HAL
+ * standard driver templates, their role is to support platform
+ * specific functionalities.
+ *
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_DMA MK66FX1M0 DMA Support
+ * @details This DMA helper driver is used by the other drivers in order to
+ * access the shared DMA resources in a consistent way.
+ *
+ * @section mk66fx1m0_dma_1 Supported HW resources
+ * The DMA driver can support any of the following hardware resources:
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_dma_2 MK66FX1M0 DMA driver implementation features
+ * - Exports helper functions/macros to the other drivers that share the
+ * DMA resource.
+ * - Automatic DMA clock stop when not in use by any driver.
+ * - DMA streams and interrupt vectors sharing among multiple drivers.
+ * .
+ * @ingroup MK66FX1M0_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_ISR MK66FX1M0 ISR Support
+ * @details This ISR helper driver is used by the other drivers in order to
+ * map ISR names to physical vector names.
+ *
+ * @ingroup MK66FX1M0_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_RCC MK66FX1M0 RCC Support
+ * @details This RCC helper driver is used by the other drivers in order to
+ * access the shared RCC resources in a consistent way.
+ *
+ * @section mk66fx1m0_rcc_1 Supported HW resources
+ * - RCC.
+ * .
+ * @section mk66fx1m0_rcc_2 MK66FX1M0 RCC driver implementation features
+ * - Peripherals reset.
+ * - Peripherals clock enable.
+ * - Peripherals clock disable.
+ * .
+ * @ingroup MK66FX1M0_PLATFORM_DRIVERS
+ */
diff --git a/os/hal/ports/KINETIS/MK66F18/platform.mk b/os/hal/ports/KINETIS/MK66F18/platform.mk new file mode 100644 index 0000000..0e6be12 --- /dev/null +++ b/os/hal/ports/KINETIS/MK66F18/platform.mk @@ -0,0 +1,19 @@ +# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index a2cf026..180a383 100755 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -121,9 +121,14 @@ static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) { /* Stop everything.*/ dmaStreamDisable(crcp->dma); - /* Portable CRC ISR code defined in the high level driver, note, it is - a macro.*/ - _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val); + if (crcp->rem_data_size) { + /* Start DMA follow up transfer for next data chunk */ + crc_lld_start_calc(crcp, crcp->rem_data_size, + (const void *)crcp->dma->channel->CPAR+0xffff); + } else { + /* Portable CRC ISR code defined in the high level driver, note, it is a macro.*/ + _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val); + } } #endif @@ -155,7 +160,7 @@ void crc_lld_start(CRCDriver *crcp) { if (crcp->config == NULL) crcp->config = &default_config; - rccEnableCRC(FALSE); + rccEnableCRC(); #if STM32_CRC_PROGRAMMABLE == TRUE crcp->crc->INIT = crcp->config->initial_val; @@ -234,7 +239,7 @@ void crc_lld_stop(CRCDriver *crcp) { #else (void)crcp; #endif - rccDisableCRC(FALSE); + rccDisableCRC(); } /** @@ -308,12 +313,17 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) { #if CRC_USE_DMA == TRUE void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) { + /* The STM32 DMA can only handle max 65535 bytes per transfer + * because it's data count register has only 16 bit. */ + size_t sz = (n > 0xffff) ? 0xffff : n; + crcp->rem_data_size = n-sz; + dmaStreamSetPeripheral(crcp->dma, buf); dmaStreamSetMemory0(crcp->dma, &crcp->crc->DR); #if STM32_CRC_PROGRAMMABLE == TRUE - dmaStreamSetTransactionSize(crcp->dma, n); + dmaStreamSetTransactionSize(crcp->dma, sz); #else - dmaStreamSetTransactionSize(crcp->dma, (n / 4)); + dmaStreamSetTransactionSize(crcp->dma, (sz / 4)); #endif dmaStreamSetMode(crcp->dma, crcp->dmamode); diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h index 213d346..e879103 100644 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h @@ -203,6 +203,12 @@ struct CRCDriver { */ thread_reference_t thread; /** + * @brief Remaining data size. + * @note The DMA can handle only 65535 bytes per transfer because + * it's data count register is only 16 bits wide. + */ + size_t rem_data_size; + /** * @brief CRC DMA stream */ const stm32_dma_stream_t *dma; diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index b4c2938..71c6ada 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -97,7 +97,10 @@ void fsmc_init(void) { #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if STM32_USE_FSMC_SDRAM FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif @@ -156,7 +159,7 @@ void fsmc_stop(FSMCDriver *fsmcp) { #if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif - rccDisableFSMC(FALSE); + rccDisableFSMC(); } #endif /* STM32_FSMC_USE_FSMC1 */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h index 51b9428..80c5d26 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h @@ -36,7 +36,10 @@ */ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if !defined(FSMC_Bank1_R_BASE) #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c index ac83477..6d727c8 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c @@ -28,7 +28,11 @@ #include "hal.h" #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h index b419168..c9f9de0 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h @@ -29,7 +29,11 @@ #define HAL_FMC_SDRAM_H_ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx)) + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #include "hal_fsmc.h" diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c index fbd6f56..da13ca5 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c @@ -148,7 +148,10 @@ void fsmcSramStop(SRAMDriver *sramp) { uint32_t mask = FSMC_BCR_MBKEN; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) mask |= FSMC_BCR_CCLKEN; #endif sramp->sram->BCR &= ~mask; diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c index c04278e..ed4c5b8 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c @@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) { if (&EICUD1 == eicup) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); + rccDisableTIM1(); } #endif #if STM32_EICU_USE_TIM2 if (&EICUD2 == eicup) { nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); + rccDisableTIM2(); } #endif #if STM32_EICU_USE_TIM3 if (&EICUD3 == eicup) { nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); + rccDisableTIM3(); } #endif #if STM32_EICU_USE_TIM4 if (&EICUD4 == eicup) { nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); + rccDisableTIM4(); } #endif #if STM32_EICU_USE_TIM5 if (&EICUD5 == eicup) { nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); + rccDisableTIM5(); } #endif #if STM32_EICU_USE_TIM8 if (&EICUD8 == eicup) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); + rccDisableTIM8(); } #endif #if STM32_EICU_USE_TIM9 if (&EICUD9 == eicup) { nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); + rccDisableTIM9(); } #endif #if STM32_EICU_USE_TIM12 if (&EICUD12 == eicup) { nvicDisableVector(STM32_TIM12_NUMBER); - rccDisableTIM12(FALSE); + rccDisableTIM12(); } #endif } #if STM32_EICU_USE_TIM10 if (&EICUD10 == eicup) { nvicDisableVector(STM32_TIM10_NUMBER); - rccDisableTIM10(FALSE); + rccDisableTIM10(); } #endif #if STM32_EICU_USE_TIM11 if (&EICUD11 == eicup) { nvicDisableVector(STM32_TIM11_NUMBER); - rccDisableTIM11(FALSE); + rccDisableTIM11(); } #endif #if STM32_EICU_USE_TIM13 if (&EICUD13 == eicup) { nvicDisableVector(STM32_TIM13_NUMBER); - rccDisableTIM13(FALSE); + rccDisableTIM13(); } #endif #if STM32_EICU_USE_TIM14 if (&EICUD14 == eicup) { nvicDisableVector(STM32_TIM14_NUMBER); - rccDisableTIM14(FALSE); + rccDisableTIM14(); } #endif } diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index 6138481..e07b946 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -235,33 +235,33 @@ void qei_lld_stop(QEIDriver *qeip) { /* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
}
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c index 37a48fd..d95c6a3 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c @@ -713,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) { if (&TIMCAPD1 == timcapp) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); + rccDisableTIM1(); } #endif #if STM32_TIMCAP_USE_TIM2 if (&TIMCAPD2 == timcapp) { nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); + rccDisableTIM2(); } #endif #if STM32_TIMCAP_USE_TIM3 if (&TIMCAPD3 == timcapp) { nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); + rccDisableTIM3(); } #endif #if STM32_TIMCAP_USE_TIM4 if (&TIMCAPD4 == timcapp) { nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); + rccDisableTIM4(); } #endif #if STM32_TIMCAP_USE_TIM5 if (&TIMCAPD5 == timcapp) { nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); + rccDisableTIM5(); } #endif #if STM32_TIMCAP_USE_TIM8 if (&TIMCAPD8 == timcapp) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); + rccDisableTIM8(); } #endif #if STM32_TIMCAP_USE_TIM9 if (&TIMCAPD9 == timcapp) { nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); + rccDisableTIM9(); } #endif } diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c index 0403eae..226f1bb 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c @@ -1673,9 +1673,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy * despite reporting a successful por enable. */ uerr("Detected enabled port; resetting OTG core"); otg->GAHBCFG = 0; - osalThreadSleepS(MS2ST(20)); + osalThreadSleepS(OSAL_MS2I(20)); _usbh_start(usbh); /* this effectively resets the core */ - osalThreadSleepS(MS2ST(100)); /* during this delay, the core generates connect ISR */ + osalThreadSleepS(OSAL_MS2I(100)); /* during this delay, the core generates connect ISR */ uinfo("OTG reset ended"); if (otg->HPRT & HPRT_PCSTS) { /* if the device is still connected, don't report a C_CONNECTION flag, which would cause @@ -1688,9 +1688,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG); while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0); otg->HPRT = hprt | HPRT_PRST; - osalThreadSleepS(MS2ST(15)); + osalThreadSleepS(OSAL_MS2I(15)); otg->HPRT = hprt; - osalThreadSleepS(MS2ST(10)); + osalThreadSleepS(OSAL_MS2I(10)); usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET; osalSysUnlock(); } break; diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index 377acdf..0102162 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -2,7 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk new file mode 100644 index 0000000..b9bbfea --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -0,0 +1,21 @@ +include ${CHIBIOS}/os/hal/ports/STM32/STM32L4xx/platform.mk
+
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
diff --git a/os/hal/ports/TIVA/LLD/GPIO/driver.mk b/os/hal/ports/TIVA/LLD/GPIO/driver.mk index 121ef57..486fe73 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/driver.mk +++ b/os/hal/ports/TIVA/LLD/GPIO/driver.mk @@ -2,12 +2,8 @@ ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c endif -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c -endif else PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c endif PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c deleted file mode 100644 index 40f06f9..0000000 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c +++ /dev/null @@ -1,981 +0,0 @@ -/* - Copyright (C) 2014..2017 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIO/hal_ext_lld.c - * @brief Tiva EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Generic interrupt serving code for multiple pins per interrupt - * handler. - */ -#define ext_lld_serve_port_interrupt(gpio, start) \ - do { \ - uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ - \ - HWREG(gpio + GPIO_O_ICR) = mis; \ - \ - if (mis & (1 << 0)) { \ - EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ - } \ - if (mis & (1 << 1)) { \ - EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ - } \ - if (mis & (1 << 2)) { \ - EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ - } \ - if (mis & (1 << 3)) { \ - EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ - } \ - if (mis & (1 << 4)) { \ - EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ - } \ - if (mis & (1 << 5)) { \ - EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ - } \ - if (mis & (1 << 6)) { \ - EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ - } \ - if (mis & (1 << 7)) { \ - EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ - } \ - } while (0); - -/** - * @brief Generic interrupt serving code for single pin per interrupt - * handler. - */ -#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ - do { \ - gpiop->ICR = (1 << pin); \ - EXTD1.config->channels[start].cb(&EXTD1, start); \ - } while (0); - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -const ioportid_t gpio_table[] = -{ -#if TIVA_HAS_GPIOA - GPIOA, -#endif -#if TIVA_HAS_GPIOB - GPIOB, -#endif -#if TIVA_HAS_GPIOC - GPIOC, -#endif -#if TIVA_HAS_GPIOD - GPIOD, -#endif -#if TIVA_HAS_GPIOE - GPIOE, -#endif -#if TIVA_HAS_GPIOF - GPIOF, -#endif -#if TIVA_HAS_GPIOG - GPIOG, -#endif -#if TIVA_HAS_GPIOH - GPIOH, -#endif -#if TIVA_HAS_GPIOJ - GPIOJ, -#endif -#if TIVA_HAS_GPIOK - GPIOK, -#endif -#if TIVA_HAS_GPIOL - GPIOL, -#endif -#if TIVA_HAS_GPIOM - GPIOM, -#endif -#if TIVA_HAS_GPION - GPION, -#endif -#if TIVA_HAS_GPIOP - GPIOP, -#endif -#if TIVA_HAS_GPIOQ - GPIOQ, -#endif -#if TIVA_HAS_GPIOR - GPIOR, -#endif -#if TIVA_HAS_GPIOS - GPIOS, -#endif -#if TIVA_HAS_GPIOT - GPIOT, -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Enables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_enable(void) -{ -#if TIVA_HAS_GPIOA - nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOB - nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOC - nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOD - nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOE - nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOF - nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOG - nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOH - nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOJ - nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOK - nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOL - nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOM - nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPION - nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOP - nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOQ - nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOR - nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOS - nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOT - nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_disable(void) -{ -#if TIVA_HAS_GPIOA - nvicDisableVector(TIVA_GPIOA_NUMBER); -#endif -#if TIVA_HAS_GPIOB - nvicDisableVector(TIVA_GPIOB_NUMBER); -#endif -#if TIVA_HAS_GPIOC - nvicDisableVector(TIVA_GPIOC_NUMBER); -#endif -#if TIVA_HAS_GPIOD - nvicDisableVector(TIVA_GPIOD_NUMBER); -#endif -#if TIVA_HAS_GPIOE - nvicDisableVector(TIVA_GPIOE_NUMBER); -#endif -#if TIVA_HAS_GPIOF - nvicDisableVector(TIVA_GPIOF_NUMBER); -#endif -#if TIVA_HAS_GPIOG - nvicDisableVector(TIVA_GPIOG_NUMBER); -#endif -#if TIVA_HAS_GPIOH - nvicDisableVector(TIVA_GPIOH_NUMBER); -#endif -#if TIVA_HAS_GPIOJ - nvicDisableVector(TIVA_GPIOJ_NUMBER); -#endif -#if TIVA_HAS_GPIOK - nvicDisableVector(TIVA_GPIOK_NUMBER); -#endif -#if TIVA_HAS_GPIOL - nvicDisableVector(TIVA_GPIOL_NUMBER); -#endif -#if TIVA_HAS_GPIOM - nvicDisableVector(TIVA_GPIOM_NUMBER); -#endif -#if TIVA_HAS_GPION - nvicDisableVector(TIVA_GPION_NUMBER); -#endif -#if TIVA_HAS_GPIOP - nvicDisableVector(TIVA_GPIOP0_NUMBER); - nvicDisableVector(TIVA_GPIOP1_NUMBER); - nvicDisableVector(TIVA_GPIOP2_NUMBER); - nvicDisableVector(TIVA_GPIOP3_NUMBER); - nvicDisableVector(TIVA_GPIOP4_NUMBER); - nvicDisableVector(TIVA_GPIOP5_NUMBER); - nvicDisableVector(TIVA_GPIOP6_NUMBER); - nvicDisableVector(TIVA_GPIOP7_NUMBER); -#endif -#if TIVA_HAS_GPIOQ - nvicDisableVector(TIVA_GPIOQ0_NUMBER); - nvicDisableVector(TIVA_GPIOQ1_NUMBER); - nvicDisableVector(TIVA_GPIOQ2_NUMBER); - nvicDisableVector(TIVA_GPIOQ3_NUMBER); - nvicDisableVector(TIVA_GPIOQ4_NUMBER); - nvicDisableVector(TIVA_GPIOQ5_NUMBER); - nvicDisableVector(TIVA_GPIOQ6_NUMBER); - nvicDisableVector(TIVA_GPIOQ7_NUMBER); -#endif -#if TIVA_HAS_GPIOR - nvicDisableVector(TIVA_GPIOR_NUMBER); -#endif -#if TIVA_HAS_GPIOS - nvicDisableVector(TIVA_GPIOS_NUMBER); -#endif -#if TIVA_HAS_GPIOT - nvicDisableVector(TIVA_GPIOT_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -/** - * @brief GPIOA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOA, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -/** - * @brief GPIOB interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOB, 8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -/** - * @brief GPIOC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOC, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -/** - * @brief GPIOD interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOD, 24); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -/** - * @brief GPIOE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOE, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -/** - * @brief GPIOF interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOF, 40); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** - * @brief GPIOG interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOG, 48); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** - * @brief GPIOH interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOH, 56); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** - * @brief GPIOJ interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOJ, 64); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** - * @brief GPIOK interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOK, 72); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** - * @brief GPIOL interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOL, 80); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** - * @brief GPIOM interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOM, 88); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** - * @brief GPION interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPION, 96); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** - * @brief GPIOP0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** - * @brief GPIOQ0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** - * @brief GPIOR interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOR, 120); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** - * @brief GPIOS interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOS, 128); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** - * @brief GPIOT interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOT, 132); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) -{ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) -{ - uint8_t i; - - if (extp->state == EXT_STOP) { - ext_lld_irq_enable(); - } - - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) { - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { - ext_lld_channel_enable(extp, i); - } - else { - ext_lld_channel_disable(extp, i); - } - } -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) -{ - if (extp->state == EXT_ACTIVE) { - ext_lld_irq_disable(); - } - -#if TIVA_HAS_GPIOA - HWREG(GPIOA + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOB - HWREG(GPIOB + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOC - HWREG(GPIOC + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOD - HWREG(GPIOD + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOE - HWREG(GPIOE + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOF - HWREG(GPIOF + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOG - HWREG(GPIOG + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOH - HWREG(GPIOH + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOJ - HWREG(GPIOJ + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOK - HWREG(GPIOK + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOL - HWREG(GPIOL + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOM - HWREG(GPIOM + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPION - HWREG(GPION + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOP - HWREG(GPIOP + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOQ - HWREG(GPIOQ + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOR - HWREG(GPIOR + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOS - HWREG(GPIOS + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOT - HWREG(GPIOT + GPIO_O_IM) = 0; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) -{ - uint32_t gpio; - uint8_t pin; - uint32_t im; - - pin = channel & 0x07; - gpio = gpio_table[channel >> 3]; - - /* Disable interrupts */ - im = HWREG(gpio + GPIO_O_IM); - HWREG(gpio + GPIO_O_IM) = 0; - - /* Configure pin to be edge-sensitive.*/ - HWREG(gpio + GPIO_O_IS) &= ~(1 << pin); - - /* Programming edge registers.*/ - if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_BOTH_EDGES) { - HWREG(gpio + GPIO_O_IBE) |= (1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_FALLING_EDGE) { - HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); - HWREG(gpio + GPIO_O_IEV) &= ~(1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_RISING_EDGE) { - HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); - HWREG(gpio + GPIO_O_IEV) |= (1 << pin); - } - - /* Programming interrupt and event registers.*/ - if ((extp->config->channels[channel].cb != NULL) && - ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != - EXT_CH_MODE_DISABLED)) { - im |= (1 << pin); - } - else { - im &= ~(1 << pin); - } - - /* Restore interrupts */ - HWREG(gpio + GPIO_O_IM) = im; -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) -{ - (void)extp; - uint32_t gpio; - uint8_t pin; - - pin = channel & 0x07; - gpio = gpio_table[channel >> 3]; - - HWREG(gpio + GPIO_O_IM) &= ~(1 << pin); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h deleted file mode 100644 index 731f455..0000000 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - Copyright (C) 2014..2017 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIO/hal_ext_lld.h - * @brief Tiva EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef HAL_EXT_LLD_H -#define HAL_EXT_LLD_H - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of EXT per port. - */ -#define EXT_MAX_CHANNELS TIVA_GPIO_PINS - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPIOA interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOB interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOC interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOD interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOE interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOF interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOG interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOH interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOJ interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOK interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOL interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOM interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPION interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPION_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 -#endif -/** @} */ - -/** - * @brief GPIOQ0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOR interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOS interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOT interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOA" -#endif - -#if TIVA_HAS_GPIOB && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOB" -#endif - -#if TIVA_HAS_GPIOC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOC" -#endif - -#if TIVA_HAS_GPIOD && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOD" -#endif - -#if TIVA_HAS_GPIOE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOE" -#endif - -#if TIVA_HAS_GPIOF && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOF" -#endif - -#if TIVA_HAS_GPIOG && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOG" -#endif - -#if TIVA_HAS_GPIOH && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOH" -#endif - -#if TIVA_HAS_GPIOJ && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOJ" -#endif - -#if TIVA_HAS_GPIOK && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOK" -#endif - -#if TIVA_HAS_GPIOL && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOL" -#endif - -#if TIVA_HAS_GPIOM && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOM" -#endif - -#if TIVA_HAS_GPION && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPION" -#endif - -#if TIVA_HAS_GPIOP0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP0" -#endif - -#if TIVA_HAS_GPIOP1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP1" -#endif - -#if TIVA_HAS_GPIOP2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP2" -#endif - -#if TIVA_HAS_GPIOP3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP3" -#endif - -#if TIVA_HAS_GPIOP4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP4" -#endif - -#if TIVA_HAS_GPIOP5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP5" -#endif - -#if TIVA_HAS_GPIOP6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP6" -#endif - -#if TIVA_HAS_GPIOP7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP7" -#endif - -#if TIVA_HAS_GPIOQ0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ0" -#endif - -#if TIVA_HAS_GPIOQ1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ1" -#endif - -#if TIVA_HAS_GPIOQ2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ2" -#endif - -#if TIVA_HAS_GPIOQ3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ3" -#endif - -#if TIVA_HAS_GPIOQ4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ4" -#endif - -#if TIVA_HAS_GPIOQ5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ5" -#endif - -#if TIVA_HAS_GPIOQ6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ6" -#endif - -#if TIVA_HAS_GPIOQ7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ7" -#endif - -#if TIVA_HAS_GPIOR && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOR" -#endif - -#if TIVA_HAS_GPIOS && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOS" -#endif - -#if TIVA_HAS_GPIOT && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* HAL_EXT_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c index 41fb3cd..7a222e4 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c @@ -32,196 +32,121 @@ #if TIVA_HAS_GPIOA || defined(__DOXYGEN__) #define GPIOA_BIT (1 << 0) -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA_AHB_BIT (1 << 0) -#else -#define GPIOA_AHB_BIT 0 -#endif #else #define GPIOA_BIT 0 -#define GPIOA_AHB_BIT 0 #endif #if TIVA_HAS_GPIOB || defined(__DOXYGEN__) #define GPIOB_BIT (1 << 1) -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB_AHB_BIT (1 << 1) -#else -#define GPIOB_AHB_BIT 0 -#endif #else #define GPIOB_BIT 0 -#define GPIOB_AHB_BIT 0 #endif #if TIVA_HAS_GPIOC || defined(__DOXYGEN__) #define GPIOC_BIT (1 << 2) -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC_AHB_BIT (1 << 2) -#else -#define GPIOC_AHB_BIT 0 -#endif #else #define GPIOC_BIT 0 -#define GPIOC_AHB_BIT 0 #endif #if TIVA_HAS_GPIOD || defined(__DOXYGEN__) #define GPIOD_BIT (1 << 3) -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD_AHB_BIT (1 << 3) -#else -#define GPIOD_AHB_BIT 0 -#endif #else #define GPIOD_BIT 0 -#define GPIOD_AHB_BIT 0 #endif #if TIVA_HAS_GPIOE || defined(__DOXYGEN__) #define GPIOE_BIT (1 << 4) -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE_AHB_BIT (1 << 4) -#else -#define GPIOE_AHB_BIT 0 -#endif #else #define GPIOE_BIT 0 -#define GPIOE_AHB_BIT 0 #endif #if TIVA_HAS_GPIOF || defined(__DOXYGEN__) #define GPIOF_BIT (1 << 5) -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF_AHB_BIT (1 << 5) -#else -#define GPIOF_AHB_BIT 0 -#endif #else #define GPIOF_BIT 0 -#define GPIOF_AHB_BIT 0 #endif #if TIVA_HAS_GPIOG || defined(__DOXYGEN__) #define GPIOG_BIT (1 << 6) -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG_AHB_BIT (1 << 6) -#else -#define GPIOG_AHB_BIT 0 -#endif #else #define GPIOG_BIT 0 -#define GPIOG_AHB_BIT 0 #endif #if TIVA_HAS_GPIOH || defined(__DOXYGEN__) #define GPIOH_BIT (1 << 7) -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH_AHB_BIT (1 << 7) -#else -#define GPIOH_AHB_BIT 0 -#endif #else #define GPIOH_BIT 0 -#define GPIOH_AHB_BIT 0 #endif #if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) #define GPIOJ_BIT (1 << 8) -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ_AHB_BIT (1 << 8) -#else -#define GPIOJ_AHB_BIT 0 -#endif #else #define GPIOJ_BIT 0 -#define GPIOJ_AHB_BIT 0 #endif #if TIVA_HAS_GPIOK || defined(__DOXYGEN__) #define GPIOK_BIT (1 << 9) -#define GPIOK_AHB_BIT (1 << 9) #else #define GPIOK_BIT 0 -#define GPIOK_AHB_BIT 0 #endif #if TIVA_HAS_GPIOL || defined(__DOXYGEN__) #define GPIOL_BIT (1 << 10) -#define GPIOL_AHB_BIT (1 << 10) #else #define GPIOL_BIT 0 -#define GPIOL_AHB_BIT 0 #endif #if TIVA_HAS_GPIOM || defined(__DOXYGEN__) #define GPIOM_BIT (1 << 11) -#define GPIOM_AHB_BIT (1 << 11) #else #define GPIOM_BIT 0 -#define GPIOM_AHB_BIT 0 #endif #if TIVA_HAS_GPION || defined(__DOXYGEN__) #define GPION_BIT (1 << 12) -#define GPION_AHB_BIT (1 << 12) #else #define GPION_BIT 0 -#define GPION_AHB_BIT 0 #endif #if TIVA_HAS_GPIOP || defined(__DOXYGEN__) #define GPIOP_BIT (1 << 13) -#define GPIOP_AHB_BIT (1 << 13) #else #define GPIOP_BIT 0 -#define GPIOP_AHB_BIT 0 #endif #if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) #define GPIOQ_BIT (1 << 14) -#define GPIOQ_AHB_BIT (1 << 14) #else #define GPIOQ_BIT 0 -#define GPIOQ_AHB_BIT 0 #endif #if TIVA_HAS_GPIOR || defined(__DOXYGEN__) #define GPIOR_BIT (1 << 15) -#define GPIOR_AHB_BIT (1 << 15) #else #define GPIOR_BIT 0 -#define GPIOR_AHB_BIT 0 #endif #if TIVA_HAS_GPIOS || defined(__DOXYGEN__) #define GPIOS_BIT (1 << 16) -#define GPIOS_AHB_BIT (1 << 16) #else #define GPIOS_BIT 0 -#define GPIOS_AHB_BIT 0 #endif #if TIVA_HAS_GPIOT || defined(__DOXYGEN__) #define GPIOT_BIT (1 << 17) -#define GPIOT_AHB_BIT (1 << 17) #else #define GPIOT_BIT 0 -#define GPIOT_AHB_BIT 0 #endif #define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ - GPIOS_BIT | GPIOR_BIT) + GPIOS_BIT | GPIOT_BIT) -#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ - GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ - GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ - GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ - GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ - GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) +#define GPIOHBCTL_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT) #define GPIOC_JTAG_MASK (0x0F) #define GPIOD_NMI_MASK (0x80) @@ -231,6 +156,11 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** + * @brief Event records for all GPIO channels. + */ +palevent_t _pal_events[TIVA_GPIO_PINS]; + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -276,10 +206,608 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask) HWREG(port + GPIO_O_CR) = mask; } +#if PAL_USE_CALLBACKS || PAL_USE_WAIT +/** + * @brief Enables GPIO IRQ sources. + */ +static void gpio_irq_enable(void) +{ +#if TIVA_HAS_GPIOA + nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_PAL_GPIOA_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOB + nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_PAL_GPIOB_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOC + nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_PAL_GPIOC_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOD + nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_PAL_GPIOD_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOE + nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_PAL_GPIOE_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOF + nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_PAL_GPIOF_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOG + nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_PAL_GPIOG_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOH + nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_PAL_GPIOH_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOJ + nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_PAL_GPIOJ_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOK + nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_PAL_GPIOK_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOL + nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_PAL_GPIOL_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOM + nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_PAL_GPIOM_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPION + nvicEnableVector(TIVA_GPION_NUMBER, TIVA_PAL_GPION_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOP + nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_PAL_GPIOP0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_PAL_GPIOP1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_PAL_GPIOP2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_PAL_GPIOP3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_PAL_GPIOP4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_PAL_GPIOP5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_PAL_GPIOP6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_PAL_GPIOP7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOQ + nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_PAL_GPIOQ0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_PAL_GPIOQ1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_PAL_GPIOQ2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_PAL_GPIOQ3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_PAL_GPIOQ4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_PAL_GPIOQ5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_PAL_GPIOQ6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_PAL_GPIOQ7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOR + nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_PAL_GPIOR_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOS + nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_PAL_GPIOS_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOT + nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_PAL_GPIOT_IRQ_PRIORITY); +#endif +} +#endif + +#define gpio_serve_irq(mask, pin, channel) { \ + \ + if ((mask) & (1U << (pin))) { \ + _pal_isr_code(channel); \ + } \ +} + +/** + * @brief Generic interrupt serving code for multiple pins per interrupt + * handler. + */ +#define ext_lld_serve_port_interrupt(gpio, start) \ + do { \ + uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ + \ + HWREG(gpio + GPIO_O_ICR) = mis; \ + \ + gpio_serve_irq(mis, 0, start + 0); \ + gpio_serve_irq(mis, 1, start + 1); \ + gpio_serve_irq(mis, 2, start + 2); \ + gpio_serve_irq(mis, 3, start + 3); \ + gpio_serve_irq(mis, 4, start + 4); \ + gpio_serve_irq(mis, 5, start + 5); \ + gpio_serve_irq(mis, 6, start + 6); \ + gpio_serve_irq(mis, 7, start + 7); \ + } while (0); + +/** + * @brief Generic interrupt serving code for single pin per interrupt + * handler. + */ +#define ext_lld_serve_pin_interrupt(gpio, start, pin) \ + do { \ + HWREG(gpio + GPIO_O_ICR) = (1 << pin); \ + gpio_serve_irq((1 << pin), pin, start) \ + } while (0); + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIOA interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOA, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIOB interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOB, 8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIOC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOC, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIOD interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOD, 24); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIOE interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOE, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIOF interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOF, 40); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIOG interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOG, 48); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIOH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOH, 56); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** + * @brief GPIOJ interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOJ, 64); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** + * @brief GPIOK interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOK, 72); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** + * @brief GPIOL interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOL, 80); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** + * @brief GPIOM interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOM, 88); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** + * @brief GPION interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPION, 96); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** + * @brief GPIOP0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 104, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 105, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 106, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 107, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 108, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 109, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 110, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 111, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** + * @brief GPIOQ0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 112, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 113, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 114, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 115, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 116, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 117, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 118, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 119, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** + * @brief GPIOR interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOR, 120); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** + * @brief GPIOS interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOS, 128); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** + * @brief GPIOT interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOT, 132); + + OSAL_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -294,6 +822,14 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask) */ void _pal_lld_init(const PALConfig *config) { +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < TIVA_GPIO_PINS; i++) { + _pal_init_event(i); + } +#endif + /* * Enables all GPIO clocks. */ @@ -366,6 +902,9 @@ void _pal_lld_init(const PALConfig *config) #if TIVA_HAS_GPIOT || defined(__DOXYGEN__) gpio_init(GPIOT, &config->PTData); #endif +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + gpio_irq_enable(); +#endif } /** @@ -436,6 +975,159 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) } } +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) +{ + //uint8_t portidx; + uint32_t padmask; + + //portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU; + padmask = (1 << pad); + + /* Disable interrupt before changing edge configuration.*/ + HWREG(port + GPIO_O_IM) &= ~padmask; + + /* Configure pin to be edge-sensitive.*/ + HWREG(port + GPIO_O_IS) &= ~(1 << pad); + + /* Configure edges */ + switch(mode & PAL_EVENT_MODE_EDGES_MASK) { + case PAL_EVENT_MODE_BOTH_EDGES: + HWREG(port + GPIO_O_IBE) |= padmask; + break; + case PAL_EVENT_MODE_RISING_EDGE: + HWREG(port + GPIO_O_IBE) &= ~padmask; + HWREG(port + GPIO_O_IEV) &= ~padmask; + break; + case PAL_EVENT_MODE_FALLING_EDGE: + HWREG(port + GPIO_O_IBE) &= ~padmask; + HWREG(port + GPIO_O_IEV) |= padmask; + break; + default: + /* Interrupt is already disabled */ + break; + } + + if (mode & PAL_EVENT_MODE_EDGES_MASK) { + /* Enable interrupt for this pad */ + HWREG(port + GPIO_O_IM) |= padmask; + } +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) +{ + uint8_t portidx; + uint8_t eventidx; + + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU; + + eventidx = portidx * 8 + pad; + + HWREG(port + GPIO_O_IM) &= ~(1 << pad); + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(eventidx); +#endif +} + +/** + * @brief Disables GPIO IRQ sources. + */ +void pal_lld_disable_irqs(void) +{ +#if TIVA_HAS_GPIOA + nvicDisableVector(TIVA_GPIOA_NUMBER); +#endif +#if TIVA_HAS_GPIOB + nvicDisableVector(TIVA_GPIOB_NUMBER); +#endif +#if TIVA_HAS_GPIOC + nvicDisableVector(TIVA_GPIOC_NUMBER); +#endif +#if TIVA_HAS_GPIOD + nvicDisableVector(TIVA_GPIOD_NUMBER); +#endif +#if TIVA_HAS_GPIOE + nvicDisableVector(TIVA_GPIOE_NUMBER); +#endif +#if TIVA_HAS_GPIOF + nvicDisableVector(TIVA_GPIOF_NUMBER); +#endif +#if TIVA_HAS_GPIOG + nvicDisableVector(TIVA_GPIOG_NUMBER); +#endif +#if TIVA_HAS_GPIOH + nvicDisableVector(TIVA_GPIOH_NUMBER); +#endif +#if TIVA_HAS_GPIOJ + nvicDisableVector(TIVA_GPIOJ_NUMBER); +#endif +#if TIVA_HAS_GPIOK + nvicDisableVector(TIVA_GPIOK_NUMBER); +#endif +#if TIVA_HAS_GPIOL + nvicDisableVector(TIVA_GPIOL_NUMBER); +#endif +#if TIVA_HAS_GPIOM + nvicDisableVector(TIVA_GPIOM_NUMBER); +#endif +#if TIVA_HAS_GPION + nvicDisableVector(TIVA_GPION_NUMBER); +#endif +#if TIVA_HAS_GPIOP + nvicDisableVector(TIVA_GPIOP0_NUMBER); + nvicDisableVector(TIVA_GPIOP1_NUMBER); + nvicDisableVector(TIVA_GPIOP2_NUMBER); + nvicDisableVector(TIVA_GPIOP3_NUMBER); + nvicDisableVector(TIVA_GPIOP4_NUMBER); + nvicDisableVector(TIVA_GPIOP5_NUMBER); + nvicDisableVector(TIVA_GPIOP6_NUMBER); + nvicDisableVector(TIVA_GPIOP7_NUMBER); +#endif +#if TIVA_HAS_GPIOQ + nvicDisableVector(TIVA_GPIOQ0_NUMBER); + nvicDisableVector(TIVA_GPIOQ1_NUMBER); + nvicDisableVector(TIVA_GPIOQ2_NUMBER); + nvicDisableVector(TIVA_GPIOQ3_NUMBER); + nvicDisableVector(TIVA_GPIOQ4_NUMBER); + nvicDisableVector(TIVA_GPIOQ5_NUMBER); + nvicDisableVector(TIVA_GPIOQ6_NUMBER); + nvicDisableVector(TIVA_GPIOQ7_NUMBER); +#endif +#if TIVA_HAS_GPIOR + nvicDisableVector(TIVA_GPIOR_NUMBER); +#endif +#if TIVA_HAS_GPIOS + nvicDisableVector(TIVA_GPIOS_NUMBER); +#endif +#if TIVA_HAS_GPIOT + nvicDisableVector(TIVA_GPIOT_NUMBER); +#endif +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ + #endif /* HAL_USE_PAL */ /** diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h index cf14bfb..e884a92 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -329,157 +329,267 @@ typedef uint32_t iomode_t; typedef uint32_t ioline_t; /** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** * @brief Port Identifier. */ typedef uint32_t ioportid_t; +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -#if defined(TM4C123x) +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPIOA interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOA_IRQ_PRIORITY 3 +#endif /** - * @brief GPIOA AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set - * to @p FALSE the APB bus is used to access GPIOA. + * @brief GPIOB interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOA_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOB_IRQ_PRIORITY 3 #endif /** - * @brief GPIOB AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set - * to @p FALSE the APB bus is used to access GPIOB. + * @brief GPIOC interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOB_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOC_IRQ_PRIORITY 3 #endif /** - * @brief GPIOC AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set - * to @p FALSE the APB bus is used to access GPIOC. + * @brief GPIOD interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOC_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOD_IRQ_PRIORITY 3 #endif /** - * @brief GPIOD AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set - * to @p FALSE the APB bus is used to access GPIOD. + * @brief GPIOE interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOD_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOE_IRQ_PRIORITY 3 #endif /** - * @brief GPIOE AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set - * to @p FALSE the APB bus is used to access GPIOE. + * @brief GPIOF interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOE_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOF_IRQ_PRIORITY 3 #endif /** - * @brief GPIOF AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set - * to @p FALSE the APB bus is used to access GPIOF. + * @brief GPIOG interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOF_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOG_IRQ_PRIORITY 3 #endif /** - * @brief GPIOG AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set - * to @p FALSE the APB bus is used to access GPIOG. + * @brief GPIOH interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOG_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOH_IRQ_PRIORITY 3 #endif /** - * @brief GPIOH AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set - * to @p FALSE the APB bus is used to access GPIOH. + * @brief GPIOJ interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOH_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOJ_IRQ_PRIORITY 3 #endif /** - * @brief GPIOJ AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set - * to @p FALSE the APB bus is used to access GPIOJ. + * @brief GPIOK interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOJ_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOK_IRQ_PRIORITY 3 #endif +/** + * @brief GPIOL interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOL_IRQ_PRIORITY 3 #endif -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +/** + * @brief GPIOM interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOM_IRQ_PRIORITY 3 +#endif -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA GPIO_PORTA_AHB_BASE -#else -#define GPIOA GPIO_PORTA_BASE +/** + * @brief GPION interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPION_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB GPIO_PORTB_AHB_BASE -#else -#define GPIOB GPIO_PORTB_BASE +/** + * @brief GPIOP0 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP0_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC GPIO_PORTC_AHB_BASE -#else -#define GPIOC GPIO_PORTC_BASE +/** + * @brief GPIOP1 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP1_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD GPIO_PORTD_AHB_BASE -#else -#define GPIOD GPIO_PORTD_BASE +/** + * @brief GPIOP2 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP2_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE GPIO_PORTE_AHB_BASE -#else -#define GPIOE GPIO_PORTE_BASE +/** + * @brief GPIOP3 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP3_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF GPIO_PORTF_AHB_BASE -#else -#define GPIOF GPIO_PORTF_BASE +/** + * @brief GPIOP4 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP4_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG GPIO_PORTG_AHB_BASE -#else -#define GPIOG GPIO_PORTG_BASE +/** + * @brief GPIOP5 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP5_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH GPIO_PORTH_AHB_BASE -#else -#define GPIOH GPIO_PORTH_BASE +/** + * @brief GPIOP6 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP6_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ GPIO_PORTJ_AHB_BASE -#else -#define GPIOJ GPIO_PORTJ_BASE +/** + * @brief GPIOP7 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP7_IRQ_PRIORITY 3 #endif +/** @} */ +/** + * @brief GPIOQ0 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ1 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ2 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ3 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ4 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ5 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ6 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ7 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOR interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOR_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOS interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOS_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOT interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOT_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#define GPIOA GPIO_PORTA_AHB_BASE +#define GPIOB GPIO_PORTB_AHB_BASE +#define GPIOC GPIO_PORTC_AHB_BASE +#define GPIOD GPIO_PORTD_AHB_BASE +#define GPIOE GPIO_PORTE_AHB_BASE +#define GPIOF GPIO_PORTF_AHB_BASE +#define GPIOG GPIO_PORTG_AHB_BASE +#define GPIOH GPIO_PORTH_AHB_BASE +#define GPIOJ GPIO_PORTJ_AHB_BASE #define GPIOK GPIO_PORTK_BASE #define GPIOL GPIO_PORTL_BASE #define GPIOM GPIO_PORTM_BASE @@ -490,6 +600,166 @@ typedef uint32_t ioportid_t; #define GPIOS GPIO_PORTS_BASE #define GPIOT GPIO_PORTT_BASE +#if TIVA_HAS_GPIOA && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOA" +#endif + +#if TIVA_HAS_GPIOB && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOB_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOB" +#endif + +#if TIVA_HAS_GPIOC && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOC" +#endif + +#if TIVA_HAS_GPIOD && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOD_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOD" +#endif + +#if TIVA_HAS_GPIOE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOE_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOE" +#endif + +#if TIVA_HAS_GPIOF && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOF_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOF" +#endif + +#if TIVA_HAS_GPIOG && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOG_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOG" +#endif + +#if TIVA_HAS_GPIOH && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOH_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOH" +#endif + +#if TIVA_HAS_GPIOJ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOJ_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOJ" +#endif + +#if TIVA_HAS_GPIOK && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOK_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOK" +#endif + +#if TIVA_HAS_GPIOL && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOL_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOL" +#endif + +#if TIVA_HAS_GPIOM && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOM_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOM" +#endif + +#if TIVA_HAS_GPION && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPION_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPION" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP0" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP1" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP2" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP3" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP4" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP5" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP6" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP7" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ0" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ1" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ2" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ3" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ4" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ5" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ6" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ7" +#endif + +#if TIVA_HAS_GPIOR && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOR_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOR" +#endif + +#if TIVA_HAS_GPIOS && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOS_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOS" +#endif + +#if TIVA_HAS_GPIOT && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOT" +#endif + /*===========================================================================*/ /* I/O Ports Identifiers. */ /*===========================================================================*/ @@ -761,7 +1031,7 @@ typedef uint32_t ioportid_t; * @notapi */ #define pal_lld_writepad(port, pad, bit) \ - (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = (bit)) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (bit)) /** * @brief Sets a pad logical state to @p PAL_HIGH. @@ -791,12 +1061,59 @@ typedef uint32_t ioportid_t; #define pal_lld_clearpad(port, pad) \ (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[((((((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + pad)]; + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[((((((uint32_t)PAL_PORT(line) - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + PAL_PAD(line))] + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ #if !defined(__DOXYGEN__) extern const PALConfig pal_default_config; +extern palevent_t _pal_events[TIVA_GPIO_PINS]; #endif #ifdef __cplusplus @@ -806,6 +1123,13 @@ extern "C" { void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode); +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); + void pal_lld_disable_irqs(void); +#endif #ifdef __cplusplus } #endif diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index baa7112..0f9576a 100644 --- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -37,32 +37,32 @@ #if TIVA_ST_TIMER_NUMBER == 0 #define ST_HANDLER TIVA_WGPT0A_HANDLER #define ST_NUMBER TIVA_WGPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0))) #elif TIVA_ST_TIMER_NUMBER == 1 #define ST_HANDLER TIVA_WGPT1A_HANDLER #define ST_NUMBER TIVA_WGPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1))) #elif TIVA_ST_TIMER_NUMBER == 2 #define ST_HANDLER TIVA_WGPT2A_HANDLER #define ST_NUMBER TIVA_WGPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2))) #elif TIVA_ST_TIMER_NUMBER == 3 #define ST_HANDLER TIVA_WGPT3A_HANDLER #define ST_NUMBER TIVA_WGPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3))) #elif TIVA_ST_TIMER_NUMBER == 4 #define ST_HANDLER TIVA_WGPT4A_HANDLER #define ST_NUMBER TIVA_WGPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4))) #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_WGPT5A_HANDLER @@ -74,7 +74,7 @@ #error "TIVA_ST_USE_TIMER specifies an unsupported timer" #endif -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFF #error "the selected ST frequency is not obtainable because TIM timer prescaler limits" #endif @@ -83,38 +83,38 @@ #if TIVA_ST_TIMER_NUMBER == 0 #define ST_HANDLER TIVA_GPT0A_HANDLER #define ST_NUMBER TIVA_GPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0))) #elif TIVA_ST_TIMER_NUMBER == 1 #define ST_HANDLER TIVA_GPT1A_HANDLER #define ST_NUMBER TIVA_GPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1))) #elif TIVA_ST_TIMER_NUMBER == 2 #define ST_HANDLER TIVA_GPT2A_HANDLER #define ST_NUMBER TIVA_GPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2))) #elif TIVA_ST_TIMER_NUMBER == 3 #define ST_HANDLER TIVA_GPT3A_HANDLER #define ST_NUMBER TIVA_GPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3))) #elif TIVA_ST_TIMER_NUMBER == 4 #define ST_HANDLER TIVA_GPT4A_HANDLER #define ST_NUMBER TIVA_GPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4))) #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_GPT5A_HANDLER #define ST_NUMBER TIVA_GPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5))) #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c index fd7395f..7ba7bad 100644 --- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -778,7 +778,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ @@ -792,7 +792,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) return MSG_TIMEOUT; osalSysUnlock(); @@ -852,7 +852,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ @@ -866,7 +866,8 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; osalSysUnlock(); diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index 126959f..2255110 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -258,7 +258,7 @@ void spi_lld_start(SPIDriver *spip) nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); } #endif -#if TIVASPI_USE_SSI2 +#if TIVA_SPI_USE_SSI2 if (&SPID2 == spip) { bool b; b = udmaChannelAllocate(spip->dmarxnr); diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 4dcf6db..c93c189 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -156,7 +156,7 @@ #error "Invalid IRQ priority assigned to SSI2" #endif -#if TM4C123x_SPI_USE_SSI3 && \ +#if TIVA_SPI_USE_SSI3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI3" #endif diff --git a/os/hal/ports/TIVA/LLD/UART/driver.mk b/os/hal/ports/TIVA/LLD/UART/driver.mk index e23dc82..e42f34a 100644 --- a/os/hal/ports/TIVA/LLD/UART/driver.mk +++ b/os/hal/ports/TIVA/LLD/UART/driver.mk @@ -2,8 +2,12 @@ ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c endif +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c +endif else PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c endif PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c new file mode 100644 index 0000000..374ea6d --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c @@ -0,0 +1,826 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.c + * @brief Tiva low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief UART0 UART driver identifier.*/ +#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief UART1 UART driver identifier.*/ +#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief UART2 UART driver identifier.*/ +#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/** @brief UART3 UART driver identifier.*/ +#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__) +UARTDriver UARTD4; +#endif + +/** @brief UART4 UART driver identifier.*/ +#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__) +UARTDriver UARTD5; +#endif + +/** @brief UART5 UART driver identifier.*/ +#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__) +UARTDriver UARTD6; +#endif + +/** @brief UART6 UART driver identifier.*/ +#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__) +UARTDriver UARTD7; +#endif + +/** @brief UART7 UART driver identifier.*/ +#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__) +UARTDriver UARTD8; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] err UART LSR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint32_t err) +{ + uartflags_t sts = 0; + + if (err & UART_MIS_FEMIS) + sts |= UART_FRAMING_ERROR; + if (err & UART_MIS_PEMIS) + sts |= UART_PARITY_ERROR; + if (err & UART_MIS_BEMIS) + sts |= UART_BREAK_DETECTED; + if (err & UART_MIS_OEMIS) + sts |= UART_OVERRUN_ERROR; + + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_enter_rx_idle_loop(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + dmaChannelDisable(uartp->dmarxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmarxnr].dstendp = (volatile void *)&uartp->rxbuf; + primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(1) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmarxnr); + dmaChannelPrimary(uartp->dmarxnr); + dmaChannelPriorityDefault(uartp->dmarxnr); + dmaChannelEnableRequest(uartp->dmarxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmarxnr); +} + +/** + * @brief UART de-initialization. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_stop(UARTDriver *uartp) +{ + /* Stops RX and TX DMA channels.*/ + dmaChannelDisable(uartp->dmarxnr); + dmaChannelDisable(uartp->dmatxnr); + + /* Stops USART operations.*/ + HWREG(uartp->uart + UART_O_CTL) &= ~UART_CTL_UARTEN; +} + +/** + * @brief UART initialization. + * + * @param[in] uartp pointer to a @p UARTDriver object + */ +static void uart_init(UARTDriver *uartp) +{ + uint32_t u = uartp->uart; + const UARTConfig *config = uartp->config; + uint32_t brd; + uint32_t speed = config->speed; + uint32_t clock_source; + + if (uartp->config->ctl & UART_CTL_HSE) { + /* High speed mode is enabled, half the baud rate to compensate + * for high speed mode.*/ + speed = (speed + 1) / 2; + } + + if ((config->cc & UART_CC_CS_M) == UART_CC_CS_SYSCLK) { + /* UART is clocked using the SYSCLK.*/ + clock_source = TIVA_SYSCLK * 8; + } + else { + /* UART is clocked using the PIOSC.*/ + clock_source = 16000000 * 8; + } + + /* Calculate the baud rate divisor */ + brd = ((clock_source / speed) + 1) / 2; + + /* Disable UART.*/ + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; + + /* Set baud rate.*/ + HWREG(u + UART_O_IBRD) = brd / 64; + HWREG(u + UART_O_FBRD) = brd % 64; + + /* Line control/*/ + HWREG(u + UART_O_LCRH) = config->lcrh; + + /* Select clock source.*/ + HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M; + + /* FIFO configuration.*/ + HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M); + + /* Enable interrupts.*/ + HWREG(u + UART_O_IM) = UART_IM_TXIM | UART_IM_OEIM | UART_IM_BEIM | UART_IM_PEIM | UART_IM_FEIM; + + /* Enable DMA for the UART */ + HWREG(u + UART_O_DMACTL) = UART_DMACTL_TXDMAE | UART_DMACTL_RXDMAE | UART_DMACTL_DMAERR; + + /* Note that some bits are enforced.*/ + HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN | UART_CTL_EOT; + + /* Starting the receiver idle loop.*/ + uart_enter_rx_idle_loop(uartp); +} + +/** + * @brief UART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_serve_interrupt(UARTDriver *uartp) +{ + uint32_t dmachis = HWREG(UDMA_CHIS); + uint32_t mis = HWREG(uartp->uart + UART_O_MIS); + + if (mis & UART_MIS_TXMIS) { + /* End of transfer */ + _uart_tx2_isr_code(uartp); + } + + if (mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_PEMIS | UART_MIS_FEMIS)) { + /* Error occurred */ + _uart_rx_error_isr_code(uartp, translate_errors(mis)); + } + + if (dmachis & (1 << uartp->dmarxnr)) { + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + _uart_rx_idle_code(uartp); + uart_enter_rx_idle_loop(uartp); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + _uart_rx_complete_isr_code(uartp); + } + } + + if (dmachis & (1 << uartp->dmatxnr)) { + /* A callback is generated, if enabled, after a completed transfer.*/ + _uart_tx1_isr_code(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__) +#if !defined(TIVA_UART0_HANDLER) +#error "TIVA_UART0_HANDLER not defined" +#endif +/** + * @brief UART0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__) +#if !defined(TIVA_UART1_HANDLER) +#error "TIVA_UART1_HANDLER not defined" +#endif +/** + * @brief UART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__) +#if !defined(TIVA_UART2_HANDLER) +#error "TIVA_UART2_HANDLER not defined" +#endif +/** + * @brief UART2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__) +#if !defined(TIVA_UART3_HANDLER) +#error "TIVA_UART3_HANDLER not defined" +#endif +/** + * @brief UART3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__) +#if !defined(TIVA_UART4_HANDLER) +#error "TIVA_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__) +#if !defined(TIVA_UART5_HANDLER) +#error "TIVA_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__) +#if !defined(TIVA_UART6_HANDLER) +#error "TIVA_UART6_HANDLER not defined" +#endif +/** + * @brief UART6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__) +#if !defined(TIVA_UART7_HANDLER) +#error "TIVA_UART7_HANDLER not defined" +#endif +/** + * @brief UART7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) +{ +#if TIVA_UART_USE_UART0 + uartObjectInit(&UARTD1); + UARTD1.uart = UART0_BASE; + UARTD1.dmarxnr = TIVA_UART_UART0_RX_UDMA_CHANNEL; + UARTD1.dmatxnr = TIVA_UART_UART0_TX_UDMA_CHANNEL; + UARTD1.rxchnmap = TIVA_UART_UART0_RX_UDMA_MAPPING; + UARTD1.txchnmap = TIVA_UART_UART0_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART1 + uartObjectInit(&UARTD2); + UARTD2.uart = UART1_BASE; + UARTD2.dmarxnr = TIVA_UART_UART1_RX_UDMA_CHANNEL; + UARTD2.dmatxnr = TIVA_UART_UART1_TX_UDMA_CHANNEL; + UARTD2.rxchnmap = TIVA_UART_UART1_RX_UDMA_MAPPING; + UARTD2.txchnmap = TIVA_UART_UART1_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART2 + uartObjectInit(&UARTD3); + UARTD2.uart = UART2_BASE; + UARTD2.dmarxnr = TIVA_UART_UART2_RX_UDMA_CHANNEL; + UARTD2.dmatxnr = TIVA_UART_UART2_TX_UDMA_CHANNEL; + UARTD2.rxchnmap = TIVA_UART_UART2_RX_UDMA_MAPPING; + UARTD2.txchnmap = TIVA_UART_UART2_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART3 + uartObjectInit(&UARTD4); + UARTD4.uart = UART3_BASE; + UARTD4.dmarxnr = TIVA_UART_UART3_RX_UDMA_CHANNEL; + UARTD4.dmatxnr = TIVA_UART_UART3_TX_UDMA_CHANNEL; + UARTD4.rxchnmap = TIVA_UART_UART3_RX_UDMA_MAPPING; + UARTD4.txchnmap = TIVA_UART_UART3_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART4 + uartObjectInit(&UARTD5); + UARTD5.uart = UART4_BASE; + UARTD5.dmarxnr = TIVA_UART_UART4_RX_UDMA_CHANNEL; + UARTD5.dmatxnr = TIVA_UART_UART4_TX_UDMA_CHANNEL; + UARTD5.rxchnmap = TIVA_UART_UART4_RX_UDMA_MAPPING; + UARTD5.txchnmap = TIVA_UART_UART4_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART5 + uartObjectInit(&UARTD6); + UARTD6.uart = UART5_BASE; + UARTD6.dmarxnr = TIVA_UART_UART5_RX_UDMA_CHANNEL; + UARTD6.dmatxnr = TIVA_UART_UART5_TX_UDMA_CHANNEL; + UARTD6.rxchnmap = TIVA_UART_UART5_RX_UDMA_MAPPING; + UARTD6.txchnmap = TIVA_UART_UART5_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART6 + uartObjectInit(&UARTD7); + UARTD7.uart = UART6_BASE; + UARTD7.dmarxnr = TIVA_UART_UART6_RX_UDMA_CHANNEL; + UARTD7.dmatxnr = TIVA_UART_UART6_TX_UDMA_CHANNEL; + UARTD7.rxchnmap = TIVA_UART_UART6_RX_UDMA_MAPPING; + UARTD7.txchnmap = TIVA_UART_UART6_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART7 + uartObjectInit(&UARTD8); + UARTD8.uart = UART7_BASE; + UARTD8.dmarxnr = TIVA_UART_UART7_RX_UDMA_CHANNEL; + UARTD8.dmatxnr = TIVA_UART_UART7_TX_UDMA_CHANNEL; + UARTD8.rxchnmap = TIVA_UART_UART7_RX_UDMA_MAPPING; + UARTD8.txchnmap = TIVA_UART_UART7_TX_UDMA_MAPPING; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if TIVA_UART_USE_UART0 + if (&UARTD1 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 0))) + ; + + nvicEnableVector(TIVA_UART0_NUMBER, TIVA_UART_UART0_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART1 + if (&UARTD2 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 1))) + ; + + nvicEnableVector(TIVA_UART1_NUMBER, TIVA_UART_UART1_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART2 + if (&UARTD3 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 2))) + ; + + nvicEnableVector(TIVA_UART2_NUMBER, TIVA_UART_UART2_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART3 + if (&UARTD4 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 3))) + ; + + nvicEnableVector(TIVA_UART3_NUMBER, TIVA_UART_UART3_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART4 + if (&UARTD5 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 4))) + ; + + nvicEnableVector(TIVA_UART4_NUMBER, TIVA_UART_UART4_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART5 + if (&UARTD6 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 5))) + ; + + nvicEnableVector(TIVA_UART5_NUMBER, TIVA_UART_UART5_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART6 + if (&UARTD7 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 6); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 6))) + ; + + nvicEnableVector(TIVA_UART6_NUMBER, TIVA_UART_UART6_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART7 + if (&UARTD8 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 7); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 7))) + ; + + nvicEnableVector(TIVA_UART7_NUMBER, TIVA_UART_UART7_PRIORITY); + } +#endif + + uartp->rxbuf = 0; + + HWREG(UDMA_CHMAP0 + (uartp->dmarxnr / 8) * 4) |= (uartp->rxchnmap << (uartp->dmarxnr % 8)); + HWREG(UDMA_CHMAP0 + (uartp->dmatxnr / 8) * 4) |= (uartp->txchnmap << (uartp->dmatxnr % 8)); + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + uart_init(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + uart_stop(uartp); + udmaChannelRelease(uartp->dmarxnr); + udmaChannelRelease(uartp->dmatxnr); + +#if TIVA_UART_USE_UART0 + if (&UARTD1 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); + return; + } +#endif +#if TIVA_UART_USE_UART1 + if (&UARTD2 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); + return; + } +#endif +#if TIVA_UART_USE_UART2 + if (&UARTD3 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); + return; + } +#endif +#if TIVA_UART_USE_UART3 + if (&UARTD4 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); + return; + } +#endif +#if TIVA_UART_USE_UART4 + if (&UARTD5 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); + return; + } +#endif +#if TIVA_UART_USE_UART5 + if (&UARTD6 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); + return; + } +#endif +#if TIVA_UART_USE_UART6 + if (&UARTD7 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); + return; + } +#endif +#if TIVA_UART_USE_UART7 + if (&UARTD8 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + /* TODO: This assert should be moved to the dma helper driver */ + osalDbgAssert((uint32_t)txbuf >= SRAM_BASE, "txbuf should be in SRAM region."); + + dmaChannelDisable(uartp->dmatxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmatxnr].srcendp = (volatile void *)txbuf+n-1; + primary[uartp->dmatxnr].dstendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmatxnr); + dmaChannelPrimary(uartp->dmatxnr); + dmaChannelPriorityDefault(uartp->dmatxnr); + dmaChannelEnableRequest(uartp->dmatxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmatxnr); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + uint16_t left; + + dmaChannelDisable(uartp->dmatxnr); + + left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4; + + return left; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + /* TODO: This assert should be moved to the dma helper driver */ + osalDbgAssert((uint32_t)rxbuf >= SRAM_BASE, "rxbuf should be in SRAM region."); + + dmaChannelDisable(uartp->dmarxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmarxnr].dstendp = (volatile void *)rxbuf+n-1; + primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmarxnr); + dmaChannelPrimary(uartp->dmarxnr); + dmaChannelPriorityDefault(uartp->dmarxnr); + dmaChannelEnableRequest(uartp->dmarxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmarxnr); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + uint16_t left; + + dmaChannelDisable(uartp->dmatxnr); + + left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4; + + uart_enter_rx_idle_loop(uartp); + + return left; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h new file mode 100644 index 0000000..1dc743b --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h @@ -0,0 +1,471 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.h + * @brief Tiva low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on UART0 enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART0) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART0 FALSE +#endif + +/** + * @brief UART driver on UART1 enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART1) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART1 FALSE +#endif + +/** + * @brief UART driver on UART2 enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART2) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART2 FALSE +#endif + +/** + * @brief UART driver on UART3 enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART3) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART3 FALSE +#endif + +/** + * @brief UART driver on UART4 enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART4) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART4 FALSE +#endif + +/** + * @brief UART driver on UART5 enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART5) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART5 FALSE +#endif + +/** + * @brief UART driver on UART6 enable switch. + * @details If set to @p TRUE the support for UART6 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART6) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART6 FALSE +#endif + +/** + * @brief UART driver on UART7 enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART7) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART7 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART0_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART1_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART2_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART3_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART4_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART5_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART6 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART6_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART7 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART7_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 && !TIVA_HAS_UART0 +#error "UART0 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART1 && !TIVA_HAS_UART1 +#error "UART1 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART2 && !TIVA_HAS_UART2 +#error "UART2 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART3 && !TIVA_HAS_UART3 +#error "UART3 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART4 && !TIVA_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART5 && !TIVA_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART6 && !TIVA_HAS_UART6 +#error "UART6 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART7 && !TIVA_HAS_UART7 +#error "UART7 not present in the selected device" +#endif + +#if !TIVA_UART_USE_UART0 && !TIVA_UART_USE_UART1 && !TIVA_UART_USE_UART2 && \ + !TIVA_UART_USE_UART3 && !TIVA_UART_USE_UART4 && !TIVA_UART_USE_UART5 && \ + !TIVA_UART_USE_UART6 && !TIVA_UART_USE_UART7 +#error "UART driver activated but no UART peripheral assigned" +#endif + +#if TIVA_UART_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if TIVA_UART_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if TIVA_UART_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +#if TIVA_UART_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + +#if TIVA_UART_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if TIVA_UART_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if TIVA_UART_USE_UART6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART6" +#endif + +#if TIVA_UART_USE_UART7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART7" +#endif + +#if !defined(TIVA_UDMA_REQUIRED) +#define TIVA_UDMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields. */ + /** + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. + */ + uint8_t ifls; + /** + * @brief Initialization value for the CC register. + */ + uint8_t cc; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the UART registers block. + */ + uint32_t uart; + /** + * @brief Receive DMA channel number. + */ + uint8_t dmarxnr; + /** + * @brief Transmit DMA channel number. + */ + uint8_t dmatxnr; + /** + * @brief Receive DMA channel map. + */ + uint8_t rxchnmap; + /** + * @brief Transmit DMA channel map. + */ + uint8_t txchnmap; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if TIVA_UART_USE_UART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if TIVA_UART_USE_UART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#if TIVA_UART_USE_UART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD4; +#endif + +#if TIVA_UART_USE_UART4 && !defined(__DOXYGEN__) +extern UARTDriver UARTD5; +#endif + +#if TIVA_UART_USE_UART5 && !defined(__DOXYGEN__) +extern UARTDriver UARTD6; +#endif + +#if TIVA_UART_USE_UART6 && !defined(__DOXYGEN__) +extern UARTDriver UARTD7; +#endif + +#if TIVA_UART_USE_UART7 && !defined(__DOXYGEN__) +extern UARTDriver UARTD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index 5937b88..5d38a67 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -203,7 +203,7 @@ #error "Invalid value for TIVA_BYPASS_VALUE defined" #endif -#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE) +#if (TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && (TIVA_MOSC_ENABLE == FALSE) #error "Main Oscillator selected but not enabled" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index de482d0..8e447ec 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -7,7 +7,14 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) +else endif # Drivers compatible with the platform. @@ -20,3 +27,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index 8e4c9fa..9702796 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -7,7 +7,14 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) +else endif # Drivers compatible with the platform. @@ -21,3 +28,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h index 163d59c..cd8344d 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h @@ -77,6 +77,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 120 #endif #if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ @@ -100,6 +101,7 @@ #define TIVA_HAS_GPIOR TRUE #define TIVA_HAS_GPIOS TRUE #define TIVA_HAS_GPIOT TRUE +#define TIVA_GPIO_PINS 144 #endif /* EPI attributes.*/ diff --git a/os/hal/src/hal_ee24xx.c b/os/hal/src/hal_ee24xx.c index 632ffbb..725258c 100644 --- a/os/hal/src/hal_ee24xx.c +++ b/os/hal/src/hal_ee24xx.c @@ -105,7 +105,7 @@ static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) { tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000); tmo /= EEPROM_I2C_CLOCK; tmo += 10; /* some additional milliseconds to be safer */ - return MS2ST(tmo); + return TIME_MS2I(tmo); } /** @@ -202,7 +202,7 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t * msg_t status = MSG_RESET; - osalDbgAssert(len != 0, "something broken in hi level part"); + osalDbgAssert(len > 0, "len must be greater than 0"); status = eeprom_write(((I2CEepromFileStream *)ip)->cfg, eepfs_getposition(ip), data, len); @@ -214,15 +214,15 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t * /** * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion + * @details Only one EEPROM page can be written at once. So function * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations + * @note To achieve the maximum efficiency use write operations * aligned to EEPROM page boundaries. */ static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ + size_t len = 0; /* bytes to be written per transaction */ + uint32_t written = 0; /* total bytes successfully written */ uint16_t pagesize; uint32_t firstpage; uint32_t lastpage; @@ -242,12 +242,10 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) { lastpage = (((EepromFileStream *)ip)->cfg->barrier_low + eepfs_getposition(ip) + n - 1) / pagesize; - written = 0; - /* data fitted in single page */ + /* data fits in single page */ if (firstpage == lastpage) { len = n; __fitted_write(ip, bp, len, &written); - bp += len; return written; } @@ -255,17 +253,19 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) { /* write first piece of data to first page boundary */ len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); len -= ((EepromFileStream *)ip)->cfg->barrier_low; - __fitted_write(ip, bp, len, &written); + if (__fitted_write(ip, bp, len, &written) != MSG_OK) + return written; bp += len; - /* now writes blocks at a size of pages (may be no one) */ + /* now write page sized blocks (zero or more) */ while ((n - written) > pagesize) { len = pagesize; - __fitted_write(ip, bp, len, &written); + if (__fitted_write(ip, bp, len, &written) != MSG_OK) + return written; bp += len; } - /* wrtie tail */ + /* write tail */ len = n - written; if (len == 0) return written; diff --git a/os/hal/src/hal_ee25xx.c b/os/hal/src/hal_ee25xx.c index 102aef8..8c35976 100644 --- a/os/hal/src/hal_ee25xx.c +++ b/os/hal/src/hal_ee25xx.c @@ -277,7 +277,7 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t msg_t status = MSG_RESET; - osalDbgAssert(len != 0, "something broken in hi level part"); + osalDbgAssert(len > 0, "len must be greater than 0"); status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg, eepfs_getposition(ip), data, len); @@ -290,15 +290,15 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t /** * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion + * @details Only one EEPROM page can be written at once. So function * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations + * @note To achieve the maximum efficiency use write operations * aligned to EEPROM page boundaries. */ static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ + size_t len = 0; /* bytes to be written per transaction */ + uint32_t written = 0; /* total bytes successfully written */ uint16_t pagesize; uint32_t firstpage; uint32_t lastpage; @@ -318,32 +318,30 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) { firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize; lastpage = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize; - written = 0; - /* data fitted in single page */ + /* data fits in single page */ if (firstpage == lastpage) { len = n; __fitted_write(ip, bp, len, &written); - bp += len; return written; } + else { /* write first piece of data to first page boundary */ len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); len -= cfg->barrier_low; - __fitted_write(ip, bp, len, &written); + if (__fitted_write(ip, bp, len, &written) != MSG_OK) + return written; bp += len; - /* now writes blocks at a size of pages (may be no one) */ + /* now write page sized blocks (zero or more) */ while ((n - written) > pagesize) { len = pagesize; - if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts... + if (__fitted_write(ip, bp, len, &written) != MSG_OK) return written; - bp += len; } - - /* wrtie tail */ + /* write tail */ len = n - written; if (len == 0) return written; diff --git a/os/hal/src/usbh/hal_usbh_aoa.c b/os/hal/src/usbh/hal_usbh_aoa.c index cb3fd18..a10ff2f 100644 --- a/os/hal/src/usbh/hal_usbh_aoa.c +++ b/os/hal/src/usbh/hal_usbh_aoa.c @@ -545,7 +545,7 @@ static void _vt(void *p) { if ((aoacp->iq_counter == 0) && !usbhURBIsBusy(&aoacp->iq_urb)) { _submitInI(aoacp); } - chVTSetI(&aoacp->vt, MS2ST(16), _vt, aoacp); + chVTSetI(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp); } osalSysUnlockFromISR(); } @@ -578,7 +578,7 @@ void usbhaoaChannelStart(USBHAOADriver *aoap) { usbhURBSubmit(&aoacp->iq_urb); chVTObjectInit(&aoacp->vt); - chVTSet(&aoacp->vt, MS2ST(16), _vt, aoacp); + chVTSet(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp); aoacp->state = USBHAOA_CHANNEL_STATE_READY; diff --git a/os/hal/src/usbh/hal_usbh_ftdi.c b/os/hal/src/usbh/hal_usbh_ftdi.c index 6fb556d..6966028 100644 --- a/os/hal/src/usbh/hal_usbh_ftdi.c +++ b/os/hal/src/usbh/hal_usbh_ftdi.c @@ -332,7 +332,7 @@ static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp, wLength }; - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000)); + return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, OSAL_MS2I(1000)); } static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) { @@ -394,7 +394,7 @@ static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudr wIndex, 0 }; - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000)); + return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, OSAL_MS2I(1000)); } @@ -610,7 +610,7 @@ static void _vt(void *p) { if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) { _submitInI(ftdipp); } - chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp); + chVTSetI(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp); osalSysUnlockFromISR(); } @@ -690,7 +690,7 @@ void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config usbhURBSubmit(&ftdipp->iq_urb); chVTObjectInit(&ftdipp->vt); - chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp); + chVTSet(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp); ftdipp->state = USBHFTDIP_STATE_READY; osalMutexUnlock(&ftdipp->ftdip->mtx); diff --git a/os/hal/src/usbh/hal_usbh_msd.c b/os/hal/src/usbh/hal_usbh_msd.c index 069c47b..7233a0b 100644 --- a/os/hal/src/usbh/hal_usbh_msd.c +++ b/os/hal/src/usbh/hal_usbh_msd.c @@ -304,7 +304,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt /* control phase */ status = usbhBulkTransfer(&lunp->msdp->epout, tran->cbw, - sizeof(*tran->cbw), &actual_len, MS2ST(1000)); + sizeof(*tran->cbw), &actual_len, OSAL_MS2I(1000)); if (status == USBH_URBSTATUS_CANCELLED) { uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED"); @@ -327,7 +327,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt ep, data, tran->cbw->dCBWDataTransferLength, - &data_actual_len, MS2ST(20000)); + &data_actual_len, OSAL_MS2I(20000)); if (status == USBH_URBSTATUS_CANCELLED) { uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED"); @@ -349,7 +349,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt /* status phase */ status = usbhBulkTransfer(&lunp->msdp->epin, &csw, - sizeof(csw), &actual_len, MS2ST(1000)); + sizeof(csw), &actual_len, OSAL_MS2I(1000)); if (status == USBH_URBSTATUS_STALL) { uwarn("\tMSD: Status phase: USBH_URBSTATUS_STALL, clear halt and retry"); @@ -358,7 +358,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt if (status == USBH_URBSTATUS_OK) { status = usbhBulkTransfer(&lunp->msdp->epin, &csw, - sizeof(csw), &actual_len, MS2ST(1000)); + sizeof(csw), &actual_len, OSAL_MS2I(1000)); } } |