Merge branch 'tiva_spi_dma'

10 files changed, 1476 insertions, 47 deletions

diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
index f77501b..e8b7abd 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h
@@ -92,10 +92,10 @@
  */
 #define GPIOA_UART0_RX          0
 #define GPIOA_UART0_TX          1
-#define GPIOA_PIN2              2
+#define GPIOA_SSI0_CLK          2
 #define GPIOA_PIN3              3
-#define GPIOA_PIN4              4
-#define GPIOA_PIN5              5
+#define GPIOA_SSI0_RX           4
+#define GPIOA_SSI0_TX           5
 #define GPIOA_PIN6              6
 #define GPIOA_PIN7              7
 
@@ -191,115 +191,115 @@
  */
 #define VAL_GPIOA_DATA          (PIN_DATA_LOW(GPIOA_UART0_RX) |              \
                                  PIN_DATA_LOW(GPIOA_UART0_TX) |              \
-                                 PIN_DATA_LOW(GPIOA_PIN2) |                  \
+                                 PIN_DATA_LOW(GPIOA_SSI0_CLK) |                  \
                                  PIN_DATA_LOW(GPIOA_PIN3) |                  \
-                                 PIN_DATA_LOW(GPIOA_PIN4) |                  \
-                                 PIN_DATA_LOW(GPIOA_PIN5) |                  \
+                                 PIN_DATA_LOW(GPIOA_SSI0_RX) |                  \
+                                 PIN_DATA_LOW(GPIOA_SSI0_TX) |                  \
                                  PIN_DATA_LOW(GPIOA_PIN6) |                  \
                                  PIN_DATA_LOW(GPIOA_PIN7))
 
 #define VAL_GPIOA_DIR           (PIN_DIR_IN(GPIOA_UART0_RX) |                \
                                  PIN_DIR_IN(GPIOA_UART0_TX) |                \
-                                 PIN_DIR_IN(GPIOA_PIN2) |                    \
+                                 PIN_DIR_IN(GPIOA_SSI0_CLK) |                    \
                                  PIN_DIR_IN(GPIOA_PIN3) |                    \
-                                 PIN_DIR_IN(GPIOA_PIN4) |                    \
-                                 PIN_DIR_IN(GPIOA_PIN5) |                    \
+                                 PIN_DIR_IN(GPIOA_SSI0_RX) |                    \
+                                 PIN_DIR_IN(GPIOA_SSI0_TX) |                    \
                                  PIN_DIR_IN(GPIOA_PIN6) |                    \
                                  PIN_DIR_IN(GPIOA_PIN7))
 
 #define VAL_GPIOA_AFSEL         (PIN_AFSEL_GPIO(GPIOA_UART0_RX) |            \
                                  PIN_AFSEL_GPIO(GPIOA_UART0_TX) |            \
-                                 PIN_AFSEL_GPIO(GPIOA_PIN2) |                \
+                                 PIN_AFSEL_GPIO(GPIOA_SSI0_CLK) |                \
                                  PIN_AFSEL_GPIO(GPIOA_PIN3) |                \
-                                 PIN_AFSEL_GPIO(GPIOA_PIN4) |                \
-                                 PIN_AFSEL_GPIO(GPIOA_PIN5) |                \
+                                 PIN_AFSEL_GPIO(GPIOA_SSI0_RX) |                \
+                                 PIN_AFSEL_GPIO(GPIOA_SSI0_TX) |                \
                                  PIN_AFSEL_GPIO(GPIOA_PIN6) |                \
                                  PIN_AFSEL_GPIO(GPIOA_PIN7))
 
 #define VAL_GPIOA_ODR           (PIN_ODR_DISABLE(GPIOA_UART0_RX) |           \
                                  PIN_ODR_DISABLE(GPIOA_UART0_TX) |           \
-                                 PIN_ODR_DISABLE(GPIOA_PIN2) |               \
+                                 PIN_ODR_DISABLE(GPIOA_SSI0_CLK) |               \
                                  PIN_ODR_DISABLE(GPIOA_PIN3) |               \
-                                 PIN_ODR_DISABLE(GPIOA_PIN4) |               \
-                                 PIN_ODR_DISABLE(GPIOA_PIN5) |               \
+                                 PIN_ODR_DISABLE(GPIOA_SSI0_RX) |               \
+                                 PIN_ODR_DISABLE(GPIOA_SSI0_TX) |               \
                                  PIN_ODR_DISABLE(GPIOA_PIN6) |               \
                                  PIN_ODR_DISABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_PUR           (PIN_PxR_DISABLE(GPIOA_UART0_RX) |           \
                                  PIN_PxR_DISABLE(GPIOA_UART0_TX) |           \
-                                 PIN_PxR_DISABLE(GPIOA_PIN2) |               \
+                                 PIN_PxR_DISABLE(GPIOA_SSI0_CLK) |               \
                                  PIN_PxR_DISABLE(GPIOA_PIN3) |               \
-                                 PIN_PxR_DISABLE(GPIOA_PIN4) |               \
-                                 PIN_PxR_DISABLE(GPIOA_PIN5) |               \
+                                 PIN_PxR_DISABLE(GPIOA_SSI0_RX) |               \
+                                 PIN_PxR_DISABLE(GPIOA_SSI0_TX) |               \
                                  PIN_PxR_DISABLE(GPIOA_PIN6) |               \
                                  PIN_PxR_DISABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_PDR           (PIN_PxR_DISABLE(GPIOA_UART0_RX) |           \
                                  PIN_PxR_DISABLE(GPIOA_UART0_TX) |           \
-                                 PIN_PxR_DISABLE(GPIOA_PIN2) |               \
+                                 PIN_PxR_DISABLE(GPIOA_SSI0_CLK) |               \
                                  PIN_PxR_DISABLE(GPIOA_PIN3) |               \
-                                 PIN_PxR_DISABLE(GPIOA_PIN4) |               \
-                                 PIN_PxR_DISABLE(GPIOA_PIN5) |               \
+                                 PIN_PxR_DISABLE(GPIOA_SSI0_RX) |               \
+                                 PIN_PxR_DISABLE(GPIOA_SSI0_TX) |               \
                                  PIN_PxR_DISABLE(GPIOA_PIN6) |               \
                                  PIN_PxR_DISABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_DEN           (PIN_DEN_ENABLE(GPIOA_UART0_RX) |            \
                                  PIN_DEN_ENABLE(GPIOA_UART0_TX) |            \
-                                 PIN_DEN_ENABLE(GPIOA_PIN2) |                \
+                                 PIN_DEN_ENABLE(GPIOA_SSI0_CLK) |                \
                                  PIN_DEN_ENABLE(GPIOA_PIN3) |                \
-                                 PIN_DEN_ENABLE(GPIOA_PIN4) |                \
-                                 PIN_DEN_ENABLE(GPIOA_PIN5) |                \
+                                 PIN_DEN_ENABLE(GPIOA_SSI0_RX) |                \
+                                 PIN_DEN_ENABLE(GPIOA_SSI0_TX) |                \
                                  PIN_DEN_ENABLE(GPIOA_PIN6) |                \
                                  PIN_DEN_ENABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_AMSEL         (PIN_AMSEL_DISABLE(GPIOA_UART0_RX) |         \
                                  PIN_AMSEL_DISABLE(GPIOA_UART0_TX) |         \
-                                 PIN_AMSEL_DISABLE(GPIOA_PIN2) |             \
+                                 PIN_AMSEL_DISABLE(GPIOA_SSI0_CLK) |             \
                                  PIN_AMSEL_DISABLE(GPIOA_PIN3))
 
 #define VAL_GPIOA_DR2R          (PIN_DRxR_ENABLE(GPIOA_UART0_RX) |           \
                                  PIN_DRxR_ENABLE(GPIOA_UART0_TX) |           \
-                                 PIN_DRxR_ENABLE(GPIOA_PIN2) |               \
+                                 PIN_DRxR_ENABLE(GPIOA_SSI0_CLK) |               \
                                  PIN_DRxR_ENABLE(GPIOA_PIN3) |               \
-                                 PIN_DRxR_ENABLE(GPIOA_PIN4) |               \
-                                 PIN_DRxR_ENABLE(GPIOA_PIN5) |               \
+                                 PIN_DRxR_ENABLE(GPIOA_SSI0_RX) |               \
+                                 PIN_DRxR_ENABLE(GPIOA_SSI0_TX) |               \
                                  PIN_DRxR_ENABLE(GPIOA_PIN6) |               \
                                  PIN_DRxR_ENABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_DR4R          (PIN_DRxR_DISABLE(GPIOA_UART0_RX) |          \
                                  PIN_DRxR_DISABLE(GPIOA_UART0_TX) |          \
-                                 PIN_DRxR_DISABLE(GPIOA_PIN2) |              \
+                                 PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) |              \
                                  PIN_DRxR_DISABLE(GPIOA_PIN3) |              \
-                                 PIN_DRxR_DISABLE(GPIOA_PIN4) |              \
-                                 PIN_DRxR_DISABLE(GPIOA_PIN5) |              \
+                                 PIN_DRxR_DISABLE(GPIOA_SSI0_RX) |              \
+                                 PIN_DRxR_DISABLE(GPIOA_SSI0_TX) |              \
                                  PIN_DRxR_DISABLE(GPIOA_PIN6) |              \
                                  PIN_DRxR_DISABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_DR8R          (PIN_DRxR_DISABLE(GPIOA_UART0_RX) |          \
                                  PIN_DRxR_DISABLE(GPIOA_UART0_TX) |          \
-                                 PIN_DRxR_DISABLE(GPIOA_PIN2) |              \
+                                 PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) |              \
                                  PIN_DRxR_DISABLE(GPIOA_PIN3) |              \
-                                 PIN_DRxR_DISABLE(GPIOA_PIN4) |              \
-                                 PIN_DRxR_DISABLE(GPIOA_PIN5) |              \
+                                 PIN_DRxR_DISABLE(GPIOA_SSI0_RX) |              \
+                                 PIN_DRxR_DISABLE(GPIOA_SSI0_TX) |              \
                                  PIN_DRxR_DISABLE(GPIOA_PIN6) |              \
                                  PIN_DRxR_DISABLE(GPIOA_PIN7))
 
 
 #define VAL_GPIOA_SLR           (PIN_SLR_DISABLE(GPIOA_UART0_RX) |           \
                                  PIN_SLR_DISABLE(GPIOA_UART0_TX) |           \
-                                 PIN_SLR_DISABLE(GPIOA_PIN2) |               \
+                                 PIN_SLR_DISABLE(GPIOA_SSI0_CLK) |               \
                                  PIN_SLR_DISABLE(GPIOA_PIN3) |               \
-                                 PIN_SLR_DISABLE(GPIOA_PIN4) |               \
-                                 PIN_SLR_DISABLE(GPIOA_PIN5) |               \
+                                 PIN_SLR_DISABLE(GPIOA_SSI0_RX) |               \
+                                 PIN_SLR_DISABLE(GPIOA_SSI0_TX) |               \
                                  PIN_SLR_DISABLE(GPIOA_PIN6) |               \
                                  PIN_SLR_DISABLE(GPIOA_PIN7))
 
 #define VAL_GPIOA_PCTL          (PIN_PCTL_MODE(GPIOA_UART0_RX, 0) |          \
                                  PIN_PCTL_MODE(GPIOA_UART0_TX, 0) |          \
-                                 PIN_PCTL_MODE(GPIOA_PIN2, 0) |              \
+                                 PIN_PCTL_MODE(GPIOA_SSI0_CLK, 0) |              \
                                  PIN_PCTL_MODE(GPIOA_PIN3, 0) |              \
-                                 PIN_PCTL_MODE(GPIOA_PIN4, 0) |              \
-                                 PIN_PCTL_MODE(GPIOA_PIN5, 0) |              \
+                                 PIN_PCTL_MODE(GPIOA_SSI0_RX, 0) |              \
+                                 PIN_PCTL_MODE(GPIOA_SSI0_TX, 0) |              \
                                  PIN_PCTL_MODE(GPIOA_PIN6, 0) |              \
                                  PIN_PCTL_MODE(GPIOA_PIN7, 0))
 
diff --git a/os/hal/ports/TIVA/LLD/spi_lld.c b/os/hal/ports/TIVA/LLD/spi_lld.c
new file mode 100644
index 0000000..cd1c3cf
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/spi_lld.c
@@ -0,0 +1,685 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/spi_lld.c
+ * @brief   TM4C123x/TM4C129x SPI subsystem low level driver.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   SPI1 driver identifier.
+ */
+#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/**
+ * @brief   SPI2 driver identifier.
+ */
+#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/**
+ * @brief   SPI3 driver identifier.
+ */
+#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__)
+SPIDriver SPID3;
+#endif
+
+/**
+ * @brief   SPI4 driver identifier.
+ */
+#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__)
+SPIDriver SPID4;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+static uint16_t dummytx;
+static uint16_t dummyrx;
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Common IRQ handler.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ */
+static void spi_serve_interrupt(SPIDriver *spip)
+{
+  SSI_TypeDef *ssi = spip->ssi;
+  uint32_t mis = ssi->MIS;
+  uint32_t dmachis = UDMA->CHIS;
+
+  /* SPI error handling.*/
+  if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) {
+    TIVA_SPI_SSI_ERROR_HOOK(spip);
+  }
+
+  if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) ==
+      ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) {
+    /* Clear DMA Channel interrupts.*/
+    UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr);
+
+    /* Portable SPI ISR code defined in the high level driver, note, it is a
+       macro.*/
+    _spi_isr_code(spip);
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__)
+/**
+ * @brief   SSI0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_SSI0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  spi_serve_interrupt(&SPID1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__)
+/**
+ * @brief   SSI1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_SSI1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  spi_serve_interrupt(&SPID2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__)
+/**
+ * @brief   SSI2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_SSI2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  spi_serve_interrupt(&SPID3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__)
+/**
+ * @brief   SSI3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_SSI3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  spi_serve_interrupt(&SPID4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) 
+{
+  dummytx = 0xFFFF;
+
+#if TIVA_SPI_USE_SSI0
+  spiObjectInit(&SPID1);
+  SPID1.ssi = SSI0;
+  SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL;
+  SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL;
+  SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING;
+  SPID1.txchnmap = TIVA_SPI_SSI0_TX_UDMA_MAPPING;
+#endif
+
+#if TIVA_SPI_USE_SSI1
+  spiObjectInit(&SPID2);
+  SPID2.ssi = SSI1;
+  SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL;
+  SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL;
+  SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING;
+  SPID2.txchnmap = TIVA_SPI_SSI1_TX_UDMA_MAPPING;
+#endif
+
+#if TIVA_SPI_USE_SSI2
+  spiObjectInit(&SPID3);
+  SPID3.ssi = SSI2;
+  SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL;
+  SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL;
+  SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING;
+  SPID3.txchnmap = TIVA_SPI_SSI2_TX_UDMA_MAPPING;
+#endif
+
+#if TIVA_SPI_USE_SSI3
+  spiObjectInit(&SPID4);
+  SPID4.ssi = SSI3;
+  SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL;
+  SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL;
+  SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING;
+  SPID4.txchnmap = TIVA_SPI_SSI3_TX_UDMA_MAPPING;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip)
+{
+  if (spip->state == SPI_STOP) {
+    /* Clock activation.*/
+#if TIVA_SPI_USE_SSI0
+    if (&SPID1 == spip) {
+      bool b;
+      b = udmaChannelAllocate(spip->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(spip->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      /* Enable SSI0 module.*/
+      SYSCTL->RCGCSSI |= (1 << 0);
+      while (!(SYSCTL->PRSSI & (1 << 0)))
+        ;
+
+      nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY);
+    }
+#endif
+#if TIVA_SPI_USE_SSI1
+    if (&SPID2 == spip) {
+      bool b;
+      b = udmaChannelAllocate(spip->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(spip->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      /* Enable SSI0 module.*/
+      SYSCTL->RCGCSSI |= (1 << 1);
+      while (!(SYSCTL->PRSSI & (1 << 1)))
+        ;
+
+      nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY);
+    }
+#endif
+#if TIVASPI_USE_SSI2
+    if (&SPID2 == spip) {
+      bool b;
+      b = udmaChannelAllocate(spip->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(spip->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      /* Enable SSI0 module.*/
+      SYSCTL->RCGCSSI |= (1 << 2);
+      while (!(SYSCTL->PRSSI & (1 << 2)))
+        ;
+
+      nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY);
+    }
+#endif
+#if TIVA_SPI_USE_SSI3
+    if (&SPID2 == spip) {
+      bool b;
+      b = udmaChannelAllocate(spip->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(spip->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      /* Enable SSI0 module.*/
+      SYSCTL->RCGCSSI |= (1 << 3);
+      while (!(SYSCTL->PRSSI & (1 << 3)))
+        ;
+
+      nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY);
+    }
+#endif
+
+    UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8));
+    UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8));
+  }
+  /* Set master operation mode.*/
+  spip->ssi->CR1 = 0;
+
+  /* Clock configuration - System Clock.*/
+  spip->ssi->CC = 0;
+
+  /* Clear pending interrupts.*/
+  spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC;
+
+  /* Enable Receive Time-Out and Receive Overrun Interrupts.*/
+  spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM;
+
+  /* Configure the clock prescale divisor.*/
+  spip->ssi->CPSR = spip->config->cpsr;
+
+  /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/
+  spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0);
+
+  /* Enable SSI.*/
+  spip->ssi->CR1 |= TIVA_CR1_SSE;
+
+  /* Enable RX and TX DMA channels.*/
+  spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE);
+}
+
+/**
+ * @brief   Deactivates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip)
+{
+  if (spip->state != SPI_STOP) {
+    spip->ssi->CR1 = 0;
+    spip->ssi->CR0 = 0;
+    spip->ssi->CPSR = 0;
+
+    udmaChannelRelease(spip->dmarxnr);
+    udmaChannelRelease(spip->dmatxnr);
+
+#if TIVA_SPI_USE_SSI0
+    if (&SPID1 == spip) {
+      nvicDisableVector(TIVA_SSI0_NUMBER);
+    }
+#endif
+#if TIVA_SPI_USE_SSI1
+    if (&SPID2 == spip) {
+      nvicDisableVector(TIVA_SSI1_NUMBER);
+    }
+#endif
+#if TIVA_SPI_USE_SSI2
+    if (&SPID3 == spip) {
+      nvicDisableVector(TIVA_SSI2_NUMBER);
+    }
+#endif
+#if TIVA_SPI_USE_SSI3
+    if (&SPID4 == spip) {
+      nvicDisableVector(TIVA_SSI3_NUMBER);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip)
+{
+  palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip)
+{
+  palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Ignores data on the SPI bus.
+ * @details This function transmits a series of idle words on the SPI bus and
+ *          ignores the received data. This function can be invoked even
+ *          when a slave select signal has not been yet asserted.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+    /* Configure for 8-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = &dummyrx;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+  else {
+    /* Configure for 16-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = &dummyrx;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+
+  dmaChannelSingleBurst(spip->dmatxnr);
+  dmaChannelPrimary(spip->dmatxnr);
+  dmaChannelPriorityDefault(spip->dmatxnr);
+  dmaChannelEnableRequest(spip->dmatxnr);
+
+  dmaChannelSingleBurst(spip->dmarxnr);
+  dmaChannelPrimary(spip->dmarxnr);
+  dmaChannelPriorityDefault(spip->dmarxnr);
+  dmaChannelEnableRequest(spip->dmarxnr);
+
+  /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/
+  dmaChannelEnable(spip->dmarxnr);
+  dmaChannelEnable(spip->dmatxnr);
+}
+
+/**
+ * @brief   Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ *          operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be exchanged
+ * @param[in] txbuf     the pointer to the transmit buffer
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+    /* Configure for 8-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = rxbuf+n-1;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+  else {
+    /* Configure for 16-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+
+  dmaChannelSingleBurst(spip->dmatxnr);
+  dmaChannelPrimary(spip->dmatxnr);
+  dmaChannelPriorityDefault(spip->dmatxnr);
+  dmaChannelEnableRequest(spip->dmatxnr);
+
+  dmaChannelSingleBurst(spip->dmarxnr);
+  dmaChannelPrimary(spip->dmarxnr);
+  dmaChannelPriorityDefault(spip->dmarxnr);
+  dmaChannelEnableRequest(spip->dmarxnr);
+
+  /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/
+  dmaChannelEnable(spip->dmarxnr);
+  dmaChannelEnable(spip->dmatxnr);
+}
+
+/**
+ * @brief   Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+    /* Configure for 8-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = &dummyrx;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+  else {
+    /* Configure for 16-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].srcendp = &dummyrx;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+
+  dmaChannelSingleBurst(spip->dmatxnr);
+  dmaChannelPrimary(spip->dmatxnr);
+  dmaChannelPriorityDefault(spip->dmatxnr);
+  dmaChannelEnableRequest(spip->dmatxnr);
+
+  dmaChannelSingleBurst(spip->dmarxnr);
+  dmaChannelPrimary(spip->dmarxnr);
+  dmaChannelPriorityDefault(spip->dmarxnr);
+  dmaChannelEnableRequest(spip->dmarxnr);
+
+  /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/
+  dmaChannelEnable(spip->dmarxnr);
+  dmaChannelEnable(spip->dmatxnr);
+}
+
+/**
+ * @brief   Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to receive
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) 
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) {
+    /* Configure for 8-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = rxbuf+n-1;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
+                                   UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+  else {
+    /* Configure for 16-bit transfers.*/
+    primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx;
+    primary[spip->dmatxnr].dstendp = &spip->ssi->DR;
+    primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+
+    primary[spip->dmarxnr].srcendp = &spip->ssi->DR;
+    primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1;
+    primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 |
+                                   UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 |
+                                   UDMA_CHCTL_ARBSIZE_4 |
+                                   UDMA_CHCTL_XFERSIZE(n) |
+                                   UDMA_CHCTL_XFERMODE_BASIC;
+  }
+
+  dmaChannelSingleBurst(spip->dmatxnr);
+  dmaChannelPrimary(spip->dmatxnr);
+  dmaChannelPriorityDefault(spip->dmatxnr);
+  dmaChannelEnableRequest(spip->dmatxnr);
+
+  dmaChannelSingleBurst(spip->dmarxnr);
+  dmaChannelPrimary(spip->dmarxnr);
+  dmaChannelPriorityDefault(spip->dmarxnr);
+  dmaChannelEnableRequest(spip->dmarxnr);
+
+  /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/
+  dmaChannelEnable(spip->dmarxnr);
+  dmaChannelEnable(spip->dmatxnr);
+}
+
+/**
+ * @brief   Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ *          synchronization method. This function is useful when exchanging
+ *          small amount of data on high speed channels, usually in this
+ *          situation is much more efficient just wait for completion using
+ *          polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] frame     the data frame to send over the SPI bus
+ * @return              The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame)
+{
+  spip->ssi->DR = (uint32_t)frame;
+  while ((spip->ssi->SR & TIVA_SR_RNE) == 0)
+    ;
+  return (uint16_t)spip->ssi->DR;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/spi_lld.h b/os/hal/ports/TIVA/LLD/spi_lld.h
new file mode 100644
index 0000000..c757a22
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/spi_lld.h
@@ -0,0 +1,388 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/spi_lld.h
+ * @brief   TM4C123x/TM4C129x SPI subsystem low level driver.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef _SPI_LLD_H_
+#define _SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Control 0
+ * @{
+ */
+#define TIVA_CR0_DSS_MASK       0x0F
+#define TIVA_CR0_DSS(n)         ((n-1) << 0)
+
+#define TIVA_CR0_FRF_MASK       (3 << 4)
+#define TIVA_CR0_FRF(n)         ((n) << 4)
+
+#define TIVA_CR0_SPO            (1 << 6)
+#define TIVA_CR0_SPH            (1 << 7)
+
+#define TIVA_CR0_SRC_MASK       (0xFF << 8)
+#define TIVA_CR0_SRC(n)         ((n) << 8)
+/** @} */
+
+/**
+ * @name    Control 1
+ * @{
+ */
+#define TIVA_CR1_LBM            (1 << 0)
+#define TIVA_CR1_SSE            (1 << 1)
+#define TIVA_CR1_MS             (1 << 2)
+#define TIVA_CR1_SOD            (1 << 3)
+#define TIVA_CR1_EOT            (1 << 4)
+/** @} */
+
+/**
+ * @name    Status
+ * @{
+ */
+#define TIVA_SR_TFE             (1 << 0)
+#define TIVA_SR_TNF             (1 << 1)
+#define TIVA_SR_RNE             (1 << 2)
+#define TIVA_SR_RFF             (1 << 3)
+#define TIVA_SR_BSY             (1 << 4)
+/** @} */
+
+/**
+ * @name    Interrupt Mask
+ * @{
+ */
+#define TIVA_IM_RORIM           (1 << 0)
+#define TIVA_IM_RTIM            (1 << 1)
+#define TIVA_IM_RXIM            (1 << 2)
+#define TIVA_IM_TXIM            (1 << 3)
+/** @} */
+
+/**
+ * @name    Interrupt Status
+ * @{
+ */
+#define TIVA_IS_RORIS           (1 << 0)
+#define TIVA_IS_RTIS            (1 << 1)
+#define TIVA_IS_RXIS            (1 << 2)
+#define TIVA_IS_TXIS            (1 << 3)
+/** @} */
+
+/**
+ * @name    Masked Interrupt Status
+ * @{
+ */
+#define TIVA_MIS_RORMIS         (1 << 0)
+#define TIVA_MIS_RTMIS          (1 << 1)
+#define TIVA_MIS_RXMIS          (1 << 2)
+#define TIVA_MIS_TXMIS          (1 << 3)
+/** @} */
+
+/**
+ * @name    Interrupt Clear
+ * @{
+ */
+#define TIVA_ICR_RORIC          (1 << 0)
+#define TIVA_ICR_RTIC           (1 << 1)
+/** @} */
+
+/**
+ * @name    DMA Control
+ * @{
+ */
+#define TIVA_DMACTL_RXDMAE      (1 << 0)
+#define TIVA_DMACTL_TXDMAE      (1 << 1)
+/** @}
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+ 
+/**
+ * @brief   SSI0 driver enable switch.
+ * @details If set to @p TRUE the support for SSI0 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_SPI_USE_SSI0) || defined(__DOXYGEN__)
+#define TIVA_SPI_USE_SSI0                   FALSE
+#endif
+
+/**
+ * @brief   SSI1 driver enable switch.
+ * @details If set to @p TRUE the support for SSI1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_SPI_USE_SSI1) || defined(__DOXYGEN__)
+#define TIVA_SPI_USE_SSI1                   FALSE
+#endif
+
+/**
+ * @brief   SSI2 driver enable switch.
+ * @details If set to @p TRUE the support for SSI2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_SPI_USE_SSI2) || defined(__DOXYGEN__)
+#define TIVA_SPI_USE_SSI2                   FALSE
+#endif
+
+/**
+ * @brief   SSI3 driver enable switch.
+ * @details If set to @p TRUE the support for SSI3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_SPI_USE_SSI3) || defined(__DOXYGEN__)
+#define TIVA_SPI_USE_SSI3                   FALSE
+#endif
+
+/**
+ * @brief   SPID1 interrupt priority level setting.
+ */
+#if !defined(TIVA_SPI_SSI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SPI_SSI0_IRQ_PRIORITY          5
+#endif
+
+/**
+ * @brief   SPID2 interrupt priority level setting.
+ */
+#if !defined(TIVA_SPI_SSI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SPI_SSI1_IRQ_PRIORITY          5
+#endif
+
+/**
+ * @brief   SPID3 interrupt priority level setting.
+ */
+#if !defined(TIVA_SPI_SSI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SPI_SSI2_IRQ_PRIORITY          5
+#endif
+
+/**
+ * @brief   SPID4 interrupt priority level setting.
+ */
+#if !defined(TIVA_SPI_SSI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SPI_SSI3_IRQ_PRIORITY          5
+#endif
+
+/**
+ * @brief   SPI error hook.
+ */
+#if !defined(TIVA_SPI_SSI_ERROR_HOOK) || defined(__DOXYGEN__)
+#define TIVA_SPI_SSI_ERROR_HOOK(spip)       osalSysHalt("SSI failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if TIVA_SPI_USE_SSI0 && !TIVA_HAS_SSI0
+#error "SSI0 not present in the selected device"
+#endif
+
+#if TIVA_SPI_USE_SSI1 && !TIVA_HAS_SSI1
+#error "SSI1 not present in the selected device"
+#endif
+
+#if TIVA_SPI_USE_SSI2 && !TIVA_HAS_SSI2
+#error "SSI2 not present in the selected device"
+#endif
+
+#if TIVA_SPI_USE_SSI3 && !TIVA_HAS_SSI03
+#error "SSI3 not present in the selected device"
+#endif
+
+#if !TIVA_SPI_USE_SSI0 && !TIVA_SPI_USE_SSI1 && !TIVA_SPI_USE_SSI2 && \
+  !TIVA_SPI_USE_SSI3
+#error "SPI driver activated but no SSI peripheral assigned"
+#endif
+
+#if TIVA_SPI_USE_SSI0 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SSI0"
+#endif
+
+#if TIVA_SPI_USE_SSI1 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SSI1"
+#endif
+
+#if TIVA_SPI_USE_SSI2 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SSI2"
+#endif
+
+#if TM4C123x_SPI_USE_SSI3 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SSI3"
+#endif
+
+#if !defined(TIVA_UDMA_REQUIRED)
+#define TIVA_UDMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief   SPI notification callback type.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object triggering the
+ *                      callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Operation complete callback or @p NULL.
+   */
+  spicallback_t         end_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief The chip select line port.
+   */
+  ioportid_t            ssport;
+  /**
+   * @brief The chip select line pad number.
+   */
+  uint16_t              sspad;
+  /**
+   * @brief SSI CR0 initialization data.
+   */
+  uint16_t              cr0;
+  /**
+   * @brief SSI CPSR initialization data.
+   */
+  uint32_t              cpsr;
+} SPIConfig;
+
+/**
+ * @brief   Structure representing a SPI driver.
+ */
+struct SPIDriver {
+  /**
+   * @brief Driver state.
+   */
+  spistate_t            state;
+  /**
+   * @brief Current configuration data.
+   */
+  const SPIConfig       *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t     thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the bus.
+   */
+  mutex_t                 mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+  SPI_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the SSI registers block.
+   */
+  SSI_TypeDef           *ssi;
+  /**
+   * @brief Receive DMA channel number.
+   */
+  uint8_t               dmarxnr;
+  /**
+   * @brief Transmit DMA channel number.
+   */
+  uint8_t               dmatxnr;
+  /**
+   * @brief Receive DMA channel map.
+   */
+  uint8_t               rxchnmap;
+  /**
+   * @brief Transmit DMA channel map.
+   */
+  uint8_t               txchnmap;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_SPI_USE_SSI0 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if TIVA_SPI_USE_SSI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#if TIVA_SPI_USE_SSI2 && !defined(__DOXYGEN__)
+extern SPIDriver SPID3;
+#endif
+
+#if TIVA_SPI_USE_SSI3 && !defined(__DOXYGEN__)
+extern SPIDriver SPID4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void spi_lld_init(void);
+  void spi_lld_start(SPIDriver *spip);
+  void spi_lld_stop(SPIDriver *spip);
+  void spi_lld_select(SPIDriver *spip);
+  void spi_lld_unselect(SPIDriver *spip);
+  void spi_lld_ignore(SPIDriver *spip, size_t n);
+  void spi_lld_exchange(SPIDriver *spip, size_t n,
+                        const void *txbuf, void *rxbuf);
+  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* _SPI_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/tiva_udma.c
new file mode 100644
index 0000000..e4f210e
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/tiva_udma.c
@@ -0,0 +1,141 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(TIVA_UDMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+udmaControlTable_t udmaControlTable;
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+static uint32_t udma_channel_mask;
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !defined(TIVA_UDMA_SW_HANDLER)
+#error "TIVA_UDMA_SW_HANDLER not defined"
+#endif
+/**
+ * @brief   UDMA software interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UDMA_SW_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  /* TODO Process software transfer interrupts.*/
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_UDMA_ERR_HANDLER)
+#error "TIVA_UDMA_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief   UDMA error interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  /* TODO Do we need to halt the system on a DMA error?*/
+
+  if (UDMA->ERRCLR) {
+    UDMA->ERRCLR = 1;
+  }
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Initialize UDMA.
+ *
+ * @init
+ */
+void udmaInit(void)
+{
+  udma_channel_mask = 0;
+
+  /* Enable UDMA module.*/
+  SYSCTL->RCGCDMA = 1;
+  while (!(SYSCTL->PRDMA & (1 << 0)))
+    ;
+
+  nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY);
+
+  /* Enable UDMA controller.*/
+  UDMA->CFG = 1;
+
+  /* Set address of control table.*/
+  UDMA->CTLBASE = (uint32_t)udmaControlTable.primary;
+}
+
+/**
+ * @brief   Allocates a DMA channel.
+ *
+ * @special
+ */
+bool udmaChannelAllocate(uint8_t dmach)
+{
+  /* Checks if the channel is already taken.*/
+  if ((udma_channel_mask & (1 << dmach)) != 0)
+    return TRUE;
+
+  /* Mark channel as used */
+  udma_channel_mask |= (1 << dmach);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA channel.
+ *
+ * @special
+ */
+void udmaChannelRelease(uint8_t dmach)
+{
+  /* Marks the channel as not used.*/
+  udma_channel_mask &= ~(1 << dmach);
+}
+
+#endif
diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/tiva_udma.h
new file mode 100644
index 0000000..2581c90
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/tiva_udma.h
@@ -0,0 +1,195 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef TIVA_UDMA_H_
+#define TIVA_UDMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    CHCTL register defines.
+ * @{
+ */
+#define UDMA_CHCTL_DSTINC_MASK          0xC0000000
+#define UDMA_CHCTL_DSTINC_0             0xC0000000
+#define UDMA_CHCTL_DSTINC_8             0x00000000
+#define UDMA_CHCTL_DSTINC_16            0x40000000
+#define UDMA_CHCTL_DSTINC_32            0x80000000
+#define UDMA_CHCTL_DSTSIZE_MASK         0x30000000
+#define UDMA_CHCTL_DSTSIZE_8            0x00000000
+#define UDMA_CHCTL_DSTSIZE_16           0x10000000
+#define UDMA_CHCTL_DSTSIZE_32           0x20000000
+#define UDMA_CHCTL_SRCINC_MASK          0x0C000000
+#define UDMA_CHCTL_SRCINC_0             0x0C000000
+#define UDMA_CHCTL_SRCINC_8             0x00000000
+#define UDMA_CHCTL_SRCINC_16            0x04000000
+#define UDMA_CHCTL_SRCINC_32            0x08000000
+#define UDMA_CHCTL_SRCSIZE_MASK         0x03000000
+#define UDMA_CHCTL_SRCSIZE_8            0x00000000
+#define UDMA_CHCTL_SRCSIZE_16           0x01000000
+#define UDMA_CHCTL_SRCSIZE_32           0x02000000
+#define UDMA_CHCTL_ARBSIZE_MASK         0x0003C000
+#define UDMA_CHCTL_ARBSIZE_1            0x00000000
+#define UDMA_CHCTL_ARBSIZE_2            0x00004000
+#define UDMA_CHCTL_ARBSIZE_4            0x00008000
+#define UDMA_CHCTL_ARBSIZE_8            0x0000C000
+#define UDMA_CHCTL_ARBSIZE_16           0x00010000
+#define UDMA_CHCTL_ARBSIZE_32           0x00014000
+#define UDMA_CHCTL_ARBSIZE_64           0x00018000
+#define UDMA_CHCTL_ARBSIZE_128          0x0001C000
+#define UDMA_CHCTL_ARBSIZE_256          0x00020000
+#define UDMA_CHCTL_ARBSIZE_512          0x00024000
+#define UDMA_CHCTL_ARBSIZE_1024         0x00028000
+#define UDMA_CHCTL_XFERSIZE_MASK        0x00003FF0
+#define UDMA_CHCTL_XFERSIZE(n)          ((n-1) << 4)
+#define UDMA_CHCTL_NXTUSEBURST          0x00000008
+#define UDMA_CHCTL_XFERMODE_MASK        0x00000007
+#define UDMA_CHCTL_XFERMODE_STOP        0x00000000
+#define UDMA_CHCTL_XFERMODE_BASIC       0x00000001
+#define UDMA_CHCTL_XFERMODE_AUTO        0x00000002
+#define UDMA_CHCTL_XFERMODE_PINGPONG    0x00000003
+#define UDMA_CHCTL_XFERMODE_MSG         0x00000004
+#define UDMA_CHCTL_XFERMODE_AMSG        0x00000005
+#define UDMA_CHCTL_XFERMODE_PSG         0x00000006
+#define UDMA_CHCTL_XFERMODE_APSG        0x00000007
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   UDMA software interrupt priority level setting.
+ */
+#if !defined(TIVA_UDMA_SW_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UDMA_SW_IRQ_PRIORITY           5
+#endif
+
+/**
+ * @brief   UDMA error interrupt priority level setting.
+ */
+#if !defined(TIVA_UDMA_ERR_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UDMA_ERR_IRQ_PRIORITY          5
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   A structure that defines an entry in the channel control table.
+ * @note    These fields are used by the uDMA controller and normally it is not
+ *          necessary for software to directly read or write fields in the
+ *          table.
+ */
+typedef struct __attribute__((packed))
+{
+    /**
+     * @brief   The ending source address of the data transfer.
+     */
+    volatile void *srcendp;
+    /**
+     * @brief   The ending destination address of the data transfer.
+     */
+    volatile void *dstendp;
+    /**
+     * @brief   The channel control mode.
+     */
+    volatile uint32_t chctl;
+    /**
+     * @brief   An unused location.
+     */
+    volatile uint32_t unused;
+} tiva_udma_table_entry_t;
+
+typedef struct __attribute__((packed, aligned(1024)))
+{
+  union {
+    struct {
+      tiva_udma_table_entry_t primary[32];
+      tiva_udma_table_entry_t alternate[32];
+    };
+    uint8_t raw[1024];
+  };
+} udmaControlTable_t ;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+#define dmaChannelEnable(dmach) {\
+  UDMA->ENASET = (1 << dmach);\
+}
+
+#define dmaChannelDisable(dmach) { \
+  UDMA->ENACLR = (1 << dmach); \
+}
+
+#define dmaChannelPrimary(dmach) {\
+  UDMA->ALTCLR = (1 << dmach); \
+}
+
+#define dmaChannelAlternate(dmach) { \
+  UDMA->ALTSET = (1 << dmach); \
+}
+
+#define dmaChannelSingleBurst(dmach) { \
+  UDMA->USEBURSTCLR = (1 << dmach); \
+}
+
+#define dmaChannelBurstOnly(dmach) { \
+  UDMA->USEBURSTSET = (1 << dmach); \
+}
+
+#define dmaChannelPriorityHigh(dmach) { \
+  UDMA->PRIOSET = (1 << dmach); \
+}
+
+#define dmaChannelPriorityDefault(dmach) { \
+  UDMA->PRIOCLR = (1 << dmach); \
+}
+
+#define dmaChannelEnableRequest(dmach) {\
+  UDMA->REQMASKCLR = (1 << dmach); \
+}
+
+#define dmaChannelDisableRequest(dmach) {\
+  UDMA->REQMASKSET = (1 << dmach); \
+}
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+extern udmaControlTable_t udmaControlTable;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void udmaInit(void);
+  bool udmaChannelAllocate(uint8_t dmach);
+  void udmaChannelRelease(uint8_t dmach);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TIVA_UDMA_H_ */
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c
index 7a6046d..f259151 100644
--- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c
@@ -131,6 +131,10 @@ void tiva_clock_init(void)
 #if HAL_USE_PWM
   SYSCTL->RCC |= TIVA_PWM_FIELDS;
 #endif
+
+#if defined(TIVA_UDMA_REQUIRED)
+  udmaInit();
+#endif
 }
 
 /**
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
index d8b856f..72b53b4 100644
--- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
@@ -349,6 +349,7 @@
 /* Various helpers.*/
 #include "nvic.h"
 #include "tiva_isr.h"
+#include "tiva_udma.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk
index 3051cd3..0f54c5a 100644
--- a/os/hal/ports/TIVA/TM4C123x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C123x/platform.mk
@@ -6,7 +6,9 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
               ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \
               ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/i2c_lld.c \
               ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/gpt_lld.c \
-              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pwm_lld.c
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pwm_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/spi_lld.c \
+              ${CHISIOS}/community/os/hal/ports/TIVA/LLD/tiva_udma.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
index a7bd264..d640e07 100644
--- a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
+++ b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
@@ -34,6 +34,13 @@
  * @{
  */
 
+/* UDMA units.*/
+#define TIVA_UDMA_SW_HANDLER                VectorF8
+#define TIVA_UDMA_ERR_HANDLER               VectorFC
+
+#define TIVA_UDMA_SW_NUMBER                 46
+#define TIVA_UDMA_ERR_NUMBER                47
+
 /* GPIO units.*/
 #if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
   || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM)  \
diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
index dbae42c..b3444e9 100644
--- a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
+++ b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
@@ -505,7 +505,8 @@ typedef struct
  */
 typedef struct
 {
-  __IO uint32_t CR[2];          /**< Control 0, 1                            */
+  __IO uint32_t CR0;            /**< Control 0                               */
+  __IO uint32_t CR1;            /**< Control 1                               */
   __IO uint32_t DR;             /**< Data                                    */
   __I  uint32_t SR;             /**< Status                                  */
   __IO uint32_t CPSR;           /**< Clock Prescale                          */
@@ -742,11 +743,16 @@ typedef struct
   __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
   __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
   __O  uint32_t SWREQ;          /**< Channel Software Request                */
-  UDMA_SC_t USEBURST;           /**< Channel Useburst registers              */
-  UDMA_SC_t REQMASK;            /**< Channel Request Mask registers          */
-  UDMA_SC_t ENA;                /**< Channel Enable registers                */
-  UDMA_SC_t ALT;                /**< Channel Primary Alternate registers     */
-  UDMA_SC_t PRIO;               /**< Channel Priority registers              */
+  __IO uint32_t USEBURSTSET;    /**< Channel Useburst Set                    */
+  __O  uint32_t USEBURSTCLR;    /**< Channel Useburst Clear                  */
+  __IO uint32_t REQMASKSET;     /**< Channel Request Mask Set                */
+  __O  uint32_t REQMASKCLR;     /**< Channel Request Mask Clear              */
+  __IO uint32_t ENASET;         /**< Channel Enable Set                      */
+  __O  uint32_t ENACLR;         /**< Channel Enable Clear                    */
+  __IO uint32_t ALTSET;         /**< Channel Primary Alternate Set           */
+  __O  uint32_t ALTCLR;         /**< Channel Primary Alternate Clear         */
+  __IO uint32_t PRIOSET;        /**< Channel Priority Set                    */
+  __O  uint32_t PRIOCLR;        /**< Channel Priority Clear                  */
   __I  uint32_t _RESERVED0[3];  /**< Reserved                                */
   __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
   __I  uint32_t _RESERVED1[300];/**< Reserved                                */