Added Tiva HAL files.

25 files changed, 11336 insertions, 0 deletions

diff --git a/os/hal/ports/TIVA/LLD/gpt_lld.c b/os/hal/ports/TIVA/LLD/gpt_lld.c
new file mode 100644
index 0000000..c160687
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/gpt_lld.c
@@ -0,0 +1,708 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/gpt_lld.c
+ * @brief   TM4C123x/TM4C129x GPT subsystem low level driver source.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   GPTD1 driver identifier.
+ */
+#if TIVA_GPT_USE_GPT0 || defined(__DOXYGEN__)
+GPTDriver GPTD1;
+#endif
+
+/**
+ * @brief   GPTD2 driver identifier.
+ */
+#if TIVA_GPT_USE_GPT1 || defined(__DOXYGEN__)
+GPTDriver GPTD2;
+#endif
+
+/**
+ * @brief   GPTD3 driver identifier.
+ */
+#if TIVA_GPT_USE_GPT2 || defined(__DOXYGEN__)
+GPTDriver GPTD3;
+#endif
+
+/**
+ * @brief   GPTD4 driver identifier.
+ */
+#if TIVA_GPT_USE_GPT3 || defined(__DOXYGEN__)
+GPTDriver GPTD4;
+#endif
+
+/**
+ * @brief   GPTD5 driver identifier.
+ */
+#if TIVA_GPT_USE_GPT4 || defined(__DOXYGEN__)
+GPTDriver GPTD5;
+#endif
+
+/**
+ * @brief   GPTD6 driver identifier.
+ */
+#if TIVA_GPT_USE_GPT5 || defined(__DOXYGEN__)
+GPTDriver GPTD6;
+#endif
+
+/**
+ * @brief   GPTD7 driver identifier.
+ */
+#if TIVA_GPT_USE_WGPT0 || defined(__DOXYGEN__)
+GPTDriver GPTD7;
+#endif
+
+/**
+ * @brief   GPTD8 driver identifier.
+ */
+#if TIVA_GPT_USE_WGPT1 || defined(__DOXYGEN__)
+GPTDriver GPTD8;
+#endif
+
+/**
+ * @brief   GPTD9 driver identifier.
+ */
+#if TIVA_GPT_USE_WGPT2 || defined(__DOXYGEN__)
+GPTDriver GPTD9;
+#endif
+
+/**
+ * @brief   GPTD10 driver identifier.
+ */
+#if TIVA_GPT_USE_WGPT3 || defined(__DOXYGEN__)
+GPTDriver GPTD10;
+#endif
+
+/**
+ * @brief   GPTD11 driver identifier.
+ */
+#if TIVA_GPT_USE_WGPT4 || defined(__DOXYGEN__)
+GPTDriver GPTD11;
+#endif
+
+/**
+ * @brief   GPTD12 driver identifier.
+ */
+#if TIVA_GPT_USE_WGPT5 || defined(__DOXYGEN__)
+GPTDriver GPTD12;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared IRQ handler.
+ *
+ * @param[in] gptp      pointer to @p GPTDriver object
+ */
+static void gpt_lld_serve_interrupt(GPTDriver *gptp)
+{
+  gptp->gpt->ICR = 0xffffffff;
+
+  if (gptp->state == GPT_ONESHOT) {
+    gptp->state = GPT_READY;
+    gpt_lld_stop_timer(gptp);
+  }
+
+  gptp->config->callback(gptp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_GPT_USE_GPT0
+#if !defined(TIVA_GPT0A_HANDLER)
+#error "TIVA_GPT0A_HANDLER not defined"
+#endif
+/**
+ * @brief   GPT0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPT0A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_GPT1
+#if !defined(TIVA_GPT1A_HANDLER)
+#error "TIVA_GPT1A_HANDLER not defined"
+#endif
+/**
+ * @brief   GPT1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPT1A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_GPT2
+#if !defined(TIVA_GPT2A_HANDLER)
+#error "TIVA_GPT2A_HANDLER not defined"
+#endif
+/**
+ * @brief   GPT2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPT2A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_GPT3
+#if !defined(TIVA_GPT3A_HANDLER)
+#error "TIVA_GPT3A_HANDLER not defined"
+#endif
+/**
+ * @brief   GPT3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPT3A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_GPT4
+#if !defined(TIVA_GPT4A_HANDLER)
+#error "TIVA_GPT4A_HANDLER not defined"
+#endif
+/**
+ * @brief   GPT4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPT4A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_GPT5
+#if !defined(TIVA_GPT5A_HANDLER)
+#error "TIVA_GPT5A_HANDLER not defined"
+#endif
+/**
+ * @brief   GPT5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPT5A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_WGPT0
+#if !defined(TIVA_WGPT0A_HANDLER)
+#error "TIVA_WGPT0A_HANDLER not defined"
+#endif
+/**
+ * @brief   WGPT0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_WGPT0A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_WGPT1
+#if !defined(TIVA_WGPT1A_HANDLER)
+#error "TIVA_WGPT1A_HANDLER not defined"
+#endif
+/**
+ * @brief   WGPT1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_WGPT1A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_WGPT2
+#if !defined(TIVA_WGPT2A_HANDLER)
+#error "TIVA_WGPT2A_HANDLER not defined"
+#endif
+/**
+ * @brief   WGPT2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_WGPT2A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_WGPT3
+#if !defined(TIVA_WGPT3A_HANDLER)
+#error "TIVA_WGPT3A_HANDLER not defined"
+#endif
+/**
+ * @brief   WGPT3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_WGPT3A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD10);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_WGPT4
+#if !defined(TIVA_WGPT4A_HANDLER)
+#error "TIVA_WGPT4A_HANDLER not defined"
+#endif
+/**
+ * @brief   WGPT4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_WGPT4A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD11);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_GPT_USE_WGPT5
+#if !defined(TIVA_WGPT5A_HANDLER)
+#error "TIVA_WGPT5A_HANDLER not defined"
+#endif
+/**
+ * @brief   WGPT5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_WGPT5A_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  gpt_lld_serve_interrupt(&GPTD12);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level GPT driver initialization.
+ *
+ * @notapi
+ */
+void gpt_lld_init(void)
+{
+  /* Driver initialization.*/
+#if TIVA_GPT_USE_GPT0
+  GPTD1.gpt = GPT0;
+  gptObjectInit(&GPTD1);
+#endif
+
+#if TIVA_GPT_USE_GPT1
+  GPTD2.gpt = GPT1;
+  gptObjectInit(&GPTD2);
+#endif
+
+#if TIVA_GPT_USE_GPT2
+  GPTD3.gpt = GPT2;
+  gptObjectInit(&GPTD3);
+#endif
+
+#if TIVA_GPT_USE_GPT3
+  GPTD4.gpt = GPT3;
+  gptObjectInit(&GPTD4);
+#endif
+
+#if TIVA_GPT_USE_GPT4
+  GPTD5.gpt = GPT4;
+  gptObjectInit(&GPTD5);
+#endif
+
+#if TIVA_GPT_USE_GPT5
+  GPTD6.gpt = GPT5;
+  gptObjectInit(&GPTD6);
+#endif
+
+#if TIVA_GPT_USE_WGPT0
+  GPTD7.gpt = WGPT0;
+  gptObjectInit(&GPTD7);
+#endif
+
+#if TIVA_GPT_USE_WGPT1
+  GPTD8.gpt = WGPT1;
+  gptObjectInit(&GPTD8);
+#endif
+
+#if TIVA_GPT_USE_WGPT2
+  GPTD9.gpt = WGPT2;
+  gptObjectInit(&GPTD9);
+#endif
+
+#if TIVA_GPT_USE_WGPT3
+  GPTD10.gpt = WGPT3;
+  gptObjectInit(&GPTD10);
+#endif
+
+#if TIVA_GPT_USE_WGPT4
+  GPTD11.gpt = WGPT4;
+  gptObjectInit(&GPTD11);
+#endif
+
+#if TIVA_GPT_USE_WGPT5
+  GPTD12.gpt = WGPT5;
+  gptObjectInit(&GPTD12);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the GPT peripheral.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_start(GPTDriver *gptp)
+{
+  if (gptp->state == GPT_STOP) {
+    /* Clock activation.*/
+#if TIVA_GPT_USE_GPT0
+    if (&GPTD1 == gptp) {
+      SYSCTL->RCGCTIMER |= (1 << 0);
+      nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT1
+    if (&GPTD2 == gptp) {
+      SYSCTL->RCGCTIMER |= (1 << 1);
+      nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT2
+    if (&GPTD3 == gptp) {
+      SYSCTL->RCGCTIMER |= (1 << 2);
+      nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT3
+    if (&GPTD4 == gptp) {
+      SYSCTL->RCGCTIMER |= (1 << 3);
+      nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT4
+    if (&GPTD5 == gptp) {
+      SYSCTL->RCGCTIMER |= (1 << 4);
+      nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT5
+    if (&GPTD6 == gptp) {
+      SYSCTL->RCGCTIMER |= (1 << 5);
+      nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT0
+    if (&GPTD7 == gptp) {
+      SYSCTL->RCGCWTIMER |= (1 << 0);
+      nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT1
+    if (&GPTD8 == gptp) {
+      SYSCTL->RCGCWTIMER |= (1 << 1);
+      nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT2
+    if (&GPTD9 == gptp) {
+      SYSCTL->RCGCWTIMER |= (1 << 2);
+      nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT3
+    if (&GPTD10 == gptp) {
+      SYSCTL->RCGCWTIMER |= (1 << 3);
+      nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT4
+    if (&GPTD11 == gptp) {
+      SYSCTL->RCGCWTIMER |= (1 << 4);
+      nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT5
+    if (&GPTD12 == gptp) {
+      SYSCTL->RCGCWTIMER |= (1 << 5);
+      nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY);
+    }
+#endif
+  }
+
+  /* Timer configuration.*/
+  gptp->gpt->CTL = 0;
+  gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT;
+  gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1);
+}
+
+/**
+ * @brief   Deactivates the GPT peripheral.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop(GPTDriver *gptp)
+{
+  if (gptp->state == GPT_READY) {
+    gptp->gpt->IMR = 0;
+    gptp->gpt->TAILR = 0;
+    gptp->gpt->CTL = 0;
+
+#if TIVA_GPT_USE_GPT0
+    if (&GPTD1 == gptp) {
+      nvicDisableVector(TIVA_GPT0A_NUMBER);
+      SYSCTL->RCGCTIMER &= ~(1 << 0);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT1
+    if (&GPTD2 == gptp) {
+      nvicDisableVector(TIVA_GPT1A_NUMBER);
+      SYSCTL->RCGCTIMER &= ~(1 << 1);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT2
+    if (&GPTD3 == gptp) {
+      nvicDisableVector(TIVA_GPT2A_NUMBER);
+      SYSCTL->RCGCTIMER &= ~(1 << 2);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT3
+    if (&GPTD4 == gptp) {
+      nvicDisableVector(TIVA_GPT3A_NUMBER);
+      SYSCTL->RCGCTIMER &= ~(1 << 3);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT4
+    if (&GPTD5 == gptp) {
+      nvicDisableVector(TIVA_GPT4A_NUMBER);
+      SYSCTL->RCGCTIMER &= ~(1 << 4);
+    }
+#endif
+
+#if TIVA_GPT_USE_GPT5
+    if (&GPTD6 == gptp) {
+      nvicDisableVector(TIVA_GPT5A_NUMBER);
+      SYSCTL->RCGCTIMER &= ~(1 << 5);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT0
+    if (&GPTD7 == gptp) {
+      nvicDisableVector(TIVA_WGPT0A_NUMBER);
+      SYSCTL->RCGCWTIMER &= ~(1 << 0);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT1
+    if (&GPTD8 == gptp) {
+      nvicDisableVector(TIVA_WGPT1A_NUMBER);
+      SYSCTL->RCGCWTIMER &= ~(1 << 1);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT2
+    if (&GPTD9 == gptp) {
+      nvicDisableVector(TIVA_WGPT2A_NUMBER);
+      SYSCTL->RCGCWTIMER &= ~(1 << 2);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT3
+    if (&GPTD10 == gptp) {
+      nvicDisableVector(TIVA_WGPT3A_NUMBER);
+      SYSCTL->RCGCWTIMER &= ~(1 << 3);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT4
+    if (&GPTD11 == gptp) {
+      nvicDisableVector(TIVA_WGPT4A_NUMBER);
+      SYSCTL->RCGCWTIMER &= ~(1 << 4);
+    }
+#endif
+
+#if TIVA_GPT_USE_WGPT5
+    if (&GPTD12 == gptp) {
+      nvicDisableVector(TIVA_WGPT5A_NUMBER);
+      SYSCTL->RCGCWTIMER &= ~(1 << 5);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts the timer in continuous mode.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ * @param[in] interval  period in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval)
+{
+  gptp->gpt->TAILR = interval - 1;
+  gptp->gpt->ICR = 0xfffffff;
+  gptp->gpt->IMR = GPTM_IMR_TATOIM;
+  gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS;
+  gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL;
+}
+
+/**
+ * @brief   Stops the timer.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop_timer(GPTDriver *gptp)
+{
+  gptp->gpt->IMR = 0;
+  gptp->gpt->TAILR = 0;
+  gptp->gpt->CTL &= ~GPTM_CTL_TAEN;
+}
+
+/**
+ * @brief   Starts the timer in one shot mode and waits for completion.
+ * @details This function specifically polls the timer waiting for completion
+ *          in order to not have extra delays caused by interrupt servicing,
+ *          this function is only recommended for short delays.
+ *
+ * @param[in] gptp      pointer to the @p GPTDriver object
+ * @param[in] interval  time interval in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval)
+{
+  gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS;
+  gptp->gpt->TAILR = interval - 1;
+  gptp->gpt->ICR = 0xffffffff;
+  gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL;
+  while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM))
+    ;
+  gptp->gpt->ICR = 0xffffffff;
+}
+
+#endif /* HAL_USE_GPT */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/gpt_lld.h b/os/hal/ports/TIVA/LLD/gpt_lld.h
new file mode 100644
index 0000000..0e27017
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/gpt_lld.h
@@ -0,0 +1,501 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/gpt_lld.h
+ * @brief   TM4C123x/TM4C129x GPT subsystem low level driver header.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#ifndef _GPT_LLD_H_
+#define _GPT_LLD_H_
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+/**
+ * @brief   GPTD1 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_GPT0) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_GPT0                   FALSE
+#endif
+
+/**
+ * @brief   GPTD2 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_GPT1) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_GPT1                   FALSE
+#endif
+
+/**
+ * @brief   GPTD3 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_GPT2) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_GPT2                   FALSE
+#endif
+
+/**
+ * @brief   GPTD4 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_GPT3) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_GPT3                   FALSE
+#endif
+
+/**
+ * @brief   GPTD5 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_GPT4) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_GPT4                   FALSE
+#endif
+
+/**
+ * @brief   GPTD6 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_GPT5) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_GPT5                   FALSE
+#endif
+
+/**
+ * @brief   GPTD7 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_WGPT0) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_WGPT0                  FALSE
+#endif
+
+/**
+ * @brief   GPTD8 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_WGPT1) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_WGPT1                  FALSE
+#endif
+
+/**
+ * @brief   GPTD9 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_WGPT2) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_WGPT2                  FALSE
+#endif
+
+/**
+ * @brief   GPTD10 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_WGPT3) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_WGPT3                  FALSE
+#endif
+
+/**
+ * @brief   GPTD11 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_WGPT4) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_WGPT4                  FALSE
+#endif
+
+/**
+ * @brief   GPTD12 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_GPT_USE_WGPT5) || defined(__DOXYGEN__)
+#define TIVA_GPT_USE_WGPT5                  FALSE
+#endif
+
+/**
+ * @brief   GPTD1 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_GPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_GPT0A_IRQ_PRIORITY          7
+#endif
+
+/**
+ * @brief   GPTD2 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_GPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_GPT1A_IRQ_PRIORITY          7
+#endif
+
+/**
+ * @brief   GPTD3 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_GPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_GPT2A_IRQ_PRIORITY          7
+#endif
+
+/**
+ * @brief   GPTD4 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_GPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_GPT3A_IRQ_PRIORITY          7
+#endif
+
+/**
+ * @brief   GPTD5 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_GPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_GPT4A_IRQ_PRIORITY          7
+#endif
+
+/**
+ * @brief   GPTD6 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_GPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_GPT5A_IRQ_PRIORITY          7
+#endif
+
+/**
+ * @brief   GPTD7 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_WGPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_WGPT0A_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD8 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_WGPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_WGPT1A_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD9 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_WGPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_WGPT2A_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD10 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_WGPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_WGPT3A_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD11 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_WGPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_WGPT4A_IRQ_PRIORITY         7
+#endif
+
+/**
+ * @brief   GPTD12 interrupt priority level setting.
+ */
+#if !defined(TIVA_GPT_WGPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_GPT_WGPT5A_IRQ_PRIORITY         7
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if TIVA_GPT_USE_GPT0 && !TIVA_HAS_GPT0
+#error "GPT0 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_GPT1 && !TIVA_HAS_GPT1
+#error "GPT1 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_GPT2 && !TIVA_HAS_GPT2
+#error "GPT2 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_GPT3 && !TIVA_HAS_GPT3
+#error "GPT3 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_GPT4 && !TIVA_HAS_GPT4
+#error "GPT4 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_GPT5 && !TIVA_HAS_GPT5
+#error "GPT5 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_WGPT0 && !TIVA_HAS_WGPT0
+#error "WGPT0 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_WGPT1 && !TIVA_HAS_WGPT1
+#error "WGPT1 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_WGPT2 && !TIVA_HAS_WGPT2
+#error "WGPT2 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_WGPT3 && !TIVA_HAS_WGPT3
+#error "WGPT3 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_WGPT4 && !TIVA_HAS_WGPT4
+#error "WGPT4 not present in the selected device"
+#endif
+
+#if TIVA_GPT_USE_WGPT5 && !TIVA_HAS_WGPT5
+#error "WGPT5 not present in the selected device"
+#endif
+
+#if !TIVA_GPT_USE_GPT0 && !TIVA_GPT_USE_GPT1 && !TIVA_GPT_USE_GPT2 &&        \
+    !TIVA_GPT_USE_GPT3 && !TIVA_GPT_USE_GPT4 && !TIVA_GPT_USE_GPT5 &&        \
+    !TIVA_GPT_USE_WGPT0 && !TIVA_GPT_USE_WGPT1 && !TIVA_GPT_USE_WGPT2 &&     \
+    !TIVA_GPT_USE_WGPT3 && !TIVA_GPT_USE_WGPT4 && !TIVA_GPT_USE_WGPT5
+#error "GPT driver activated but no (W)GPT peripheral assigned"
+#endif
+
+#if TIVA_GPT_USE_GPT0 &&                                                     \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPT0"
+#endif
+
+#if TIVA_GPT_USE_GPT1 &&                                                     \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPT1"
+#endif
+
+#if TIVA_GPT_USE_GPT2 &&                                                     \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPT2"
+#endif
+
+#if TIVA_GPT_USE_GPT3 &&                                                     \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPT3"
+#endif
+
+#if TIVA_GPT_USE_GPT4 &&                                                     \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPT4"
+#endif
+
+#if TIVA_GPT_USE_GPT5 &&                                                     \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPT5"
+#endif
+
+#if TIVA_GPT_USE_WGPT0 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to WGPT0"
+#endif
+
+#if TIVA_GPT_USE_WGPT1 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to WGPT1"
+#endif
+
+#if TIVA_GPT_USE_WGPT2 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to WGPT2"
+#endif
+
+#if TIVA_GPT_USE_WGPT3 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to WGPT3"
+#endif
+
+#if TIVA_GPT_USE_WGPT4 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to WGPT4"
+#endif
+
+#if TIVA_GPT_USE_WGPT5 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to WGPT5"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   GPT frequency type.
+ */
+typedef uint32_t gptfreq_t;
+
+/**
+ * @brief   GPT counter type.
+ */
+typedef uint16_t gptcnt_t;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   Timer clock in Hz.
+   * @note    The low level can use assertions in order to catch invalid
+   *          frequency specifications.
+   */
+  gptfreq_t                 frequency;
+  /**
+   * @brief   Timer callback pointer.
+   * @note    This callback is invoked on GPT counter events.
+   */
+  gptcallback_t             callback;
+  /* End of the mandatory fields.*/
+} GPTConfig;
+
+/**
+ * @brief   Structure representing a GPT driver.
+ */
+struct GPTDriver {
+  /**
+   * @brief Driver state.
+   */
+  gptstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const GPTConfig           *config;
+#if defined(GPT_DRIVER_EXT_FIELDS)
+  GPT_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the GPT registers block.
+   */
+  GPT_TypeDef               *gpt;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Changes the interval of GPT peripheral.
+ * @details This function changes the interval of a running GPT unit.
+ * @pre     The GPT unit must have been activated using @p gptStart().
+ * @pre     The GPT unit must have been running in continuous mode using
+ *          @p gptStartContinuous().
+ * @post    The GPT unit interval is changed to the new value.
+ * @note    The function has effect at the next cycle start.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ * @param[in] interval  new cycle time in timer ticks
+ * @notapi
+ */
+#define gpt_lld_change_interval(gptp, interval) {                           \
+  gptp->gpt->TAILR = interval - 1;                                          \
+}
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_GPT_USE_GPT0 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD1;
+#endif
+
+#if TIVA_GPT_USE_GPT1 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD2;
+#endif
+
+#if TIVA_GPT_USE_GPT2 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD3;
+#endif
+
+#if TIVA_GPT_USE_GPT3 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD4;
+#endif
+
+#if TIVA_GPT_USE_GPT4 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD5;
+#endif
+
+#if TIVA_GPT_USE_GPT5 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD6;
+#endif
+
+#if TIVA_GPT_USE_WGPT0 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD7;
+#endif
+
+#if TIVA_GPT_USE_WGPT1 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD8;
+#endif
+
+#if TIVA_GPT_USE_WGPT2 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD9;
+#endif
+
+#if TIVA_GPT_USE_WGPT3 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD10;
+#endif
+
+#if TIVA_GPT_USE_WGPT4 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD11;
+#endif
+
+#if TIVA_GPT_USE_WGPT5 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD12;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void gpt_lld_init(void);
+  void gpt_lld_start(GPTDriver *gptp);
+  void gpt_lld_stop(GPTDriver *gptp);
+  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
+  void gpt_lld_stop_timer(GPTDriver *gptp);
+  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_GPT */
+
+#endif /* _GPT_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.c b/os/hal/ports/TIVA/LLD/i2c_lld.c
new file mode 100644
index 0000000..4019a3b
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/i2c_lld.c
@@ -0,0 +1,854 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/i2c_lld.c
+ * @brief   TM4C123x/TM4C129x I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief I2C0 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/**
+ * @brief I2C1 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/**
+ * @brief I2C2 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD3;
+#endif
+
+/**
+ * @brief I2C3 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__)
+I2CDriver I2CD4;
+#endif
+
+/**
+ * @brief I2C4 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__)
+I2CDriver I2CD5;
+#endif
+
+/**
+ * @brief I2C5 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__)
+I2CDriver I2CD6;
+#endif
+
+/**
+ * @brief I2C6 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__)
+I2CDriver I2CD7;
+#endif
+
+/**
+ * @brief I2C7 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__)
+I2CDriver I2CD8;
+#endif
+
+/**
+ * @brief I2C8 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__)
+I2CDriver I2CD9;
+#endif
+
+/**
+ * @brief I2C9 driver identifier.
+ */
+#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__)
+I2CDriver I2CD10;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   I2C shared ISR code.
+ *
+ * @param[in] i2cp  pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+static void i2c_lld_serve_interrupt(I2CDriver *i2cp)
+{
+  I2C_TypeDef *dp = i2cp->i2c;
+  uint32_t status;
+
+  // clear MIS bit in MICR by writing 1
+  dp->MICR = 1;
+
+  // read interrupt status
+  status = dp->MCS;
+
+  if (status & TIVA_MCS_ERROR) {
+    i2cp->errors |= I2C_BUS_ERROR;
+  }
+  if (status & TIVA_MCS_ARBLST) {
+    i2cp->errors |= I2C_ARBITRATION_LOST;
+  }
+
+  if (i2cp->errors == I2C_NO_ERROR) {
+    // no error detected
+    switch(i2cp->intstate) {
+      case STATE_IDLE: {
+        _i2c_wakeup_isr(i2cp);
+        break;
+      }
+      case STATE_WRITE_NEXT: {
+        if (i2cp->txbytes == 1) {
+          i2cp->intstate = STATE_WRITE_FINAL;
+        }
+        dp->MDR = *(i2cp->txbuf);
+        i2cp->txbuf++;
+        i2cp->txbytes--;
+        // start transmission
+        dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE;
+        break;
+      }
+      case STATE_WRITE_FINAL: {
+        if (i2cp->rxbytes == 0) {
+          i2cp->intstate = STATE_IDLE;
+        }
+        else if (i2cp->rxbytes == 1) {
+          i2cp->intstate = STATE_READ_ONE;
+        }
+        else {
+          i2cp->intstate = STATE_READ_FIRST;
+        }
+        dp->MDR = *(i2cp->txbuf);
+        i2cp->txbuf++;
+        // txbytes - 1
+        i2cp->txbytes--;
+        // start transmission
+        dp->MCS = TIVA_I2C_BURST_SEND_FINISH;
+        break;
+      }
+      case STATE_WAIT_ACK: {
+        break;
+      }
+      case STATE_SEND_ACK: {
+        break;
+      }
+      case STATE_READ_ONE: {
+        i2cp->intstate = STATE_READ_WAIT;
+        // Initializes driver fields, LSB = 1 -> read.
+         i2cp->addr |= 1;
+
+         // set slave address
+         dp->MSA = i2cp->addr;
+          i2cp->rxbytes--;
+         //start receiving
+         dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
+
+        break;
+      }
+      case STATE_READ_FIRST: {
+        if (i2cp->rxbytes == 2) {
+          i2cp->intstate = STATE_READ_FINAL;
+        }
+        else {
+          i2cp->intstate = STATE_READ_NEXT;
+        }
+
+        // Initializes driver fields, LSB = 1 -> read.
+         i2cp->addr |= 1;
+
+         // set slave address
+         dp->MSA = i2cp->addr;
+          i2cp->rxbytes--;
+         //start receiving
+         dp->MCS = TIVA_I2C_BURST_RECEIVE_START;
+
+        break;
+      }
+      case STATE_READ_NEXT: {
+        if(i2cp->rxbytes == 0) {
+          i2cp->intstate = STATE_READ_FINAL;
+        }
+        *(i2cp->rxbuf) = dp->MDR;
+        i2cp->rxbuf++;
+        i2cp->rxbytes--;
+        //start receiving
+        dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE;
+
+        break;
+      }
+      case STATE_READ_FINAL: {
+        i2cp->intstate = STATE_READ_WAIT;
+        *(i2cp->rxbuf) = dp->MDR;
+        i2cp->rxbuf++;
+          i2cp->rxbytes--;
+        //start receiving
+        dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH;
+
+        break;
+      }
+      case STATE_READ_WAIT: {
+        i2cp->intstate = STATE_IDLE;
+        *(i2cp->rxbuf) = dp->MDR;
+        i2cp->rxbuf++;
+        _i2c_wakeup_isr(i2cp);
+        break;
+      }
+    }
+  }
+  else {
+    // error detected
+    _i2c_wakeup_error_isr(i2cp);
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C0 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C0 */
+
+#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C1 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C1 */
+
+#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C2 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C2 */
+
+#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C3 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C3 */
+
+#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C4 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C4 */
+
+#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C5 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C5 */
+
+#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C6 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C6 */
+
+#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C7 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C7 */
+
+#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C8 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C8_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C8 */
+
+#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__)
+/**
+ * @brief   I2C9 interrupt handler.
+ *
+ * @notapi
+ */
+OSAL_IRQ_HANDLER(TIVA_I2C9_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  i2c_lld_serve_interrupt(&I2CD10);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* TIVA_I2C_USE_I2C9 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if TIVA_I2C_USE_I2C0
+  i2cObjectInit(&I2CD1);
+  I2CD1.thread = NULL;
+  I2CD1.i2c    = I2C0;
+#endif /* TIVA_I2C_USE_I2C0 */
+
+#if TIVA_I2C_USE_I2C1
+  i2cObjectInit(&I2CD2);
+  I2CD2.thread = NULL;
+  I2CD2.i2c    = I2C1;
+#endif /* TIVA_I2C_USE_I2C1 */
+
+#if TIVA_I2C_USE_I2C2
+  i2cObjectInit(&I2CD3);
+  I2CD3.thread = NULL;
+  I2CD3.i2c    = I2C2;
+#endif /* TIVA_I2C_USE_I2C2 */
+
+#if TIVA_I2C_USE_I2C3
+  i2cObjectInit(&I2CD4);
+  I2CD4.thread = NULL;
+  I2CD4.i2c    = I2C3;
+#endif /* TIVA_I2C_USE_I2C3 */
+
+#if TIVA_I2C_USE_I2C4
+  i2cObjectInit(&I2CD5);
+  I2CD5.thread = NULL;
+  I2CD5.i2c    = I2C4;
+#endif /* TIVA_I2C_USE_I2C4 */
+
+#if TIVA_I2C_USE_I2C5
+  i2cObjectInit(&I2CD6);
+  I2CD6.thread = NULL;
+  I2CD6.i2c    = I2C5;
+#endif /* TIVA_I2C_USE_I2C5 */
+
+#if TIVA_I2C_USE_I2C6
+  i2cObjectInit(&I2CD7);
+  I2CD7.thread = NULL;
+  I2CD7.i2c    = I2C6;
+#endif /* TIVA_I2C_USE_I2C6 */
+
+#if TIVA_I2C_USE_I2C7
+  i2cObjectInit(&I2CD8);
+  I2CD8.thread = NULL;
+  I2CD8.i2c    = I2C7;
+#endif /* TIVA_I2C_USE_I2C7 */
+
+#if TIVA_I2C_USE_I2C8
+  i2cObjectInit(&I2CD9);
+  I2CD9.thread = NULL;
+  I2CD9.i2c    = I2C8;
+#endif /* TIVA_I2C_USE_I2C8 */
+
+#if TIVA_I2C_USE_I2C9
+  i2cObjectInit(&I2CD10);
+  I2CD10.thread = NULL;
+  I2CD10.i2c    = I2C9;
+#endif /* TIVA_I2C_USE_I2C9 */
+}
+
+/**
+ * @brief   Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp)
+{
+  I2C_TypeDef *dp = i2cp->i2c;
+
+  /* If in stopped state then enables the I2C clocks.*/
+  if (i2cp->state == I2C_STOP) {
+#if TIVA_I2C_USE_I2C0
+    if (&I2CD1 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 0);
+      nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C0 */
+
+#if TIVA_I2C_USE_I2C1
+    if (&I2CD2 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 1);
+      nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C1 */
+
+#if TIVA_I2C_USE_I2C2
+    if (&I2CD3 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 2);
+      nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C2 */
+
+#if TIVA_I2C_USE_I2C3
+    if (&I2CD4 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 3);
+      nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C3 */
+
+#if TIVA_I2C_USE_I2C4
+    if (&I2CD5 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 4);
+      nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C4 */
+
+#if TIVA_I2C_USE_I2C5
+    if (&I2CD6 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 5);
+      nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C5 */
+
+#if TIVA_I2C_USE_I2C6
+    if (&I2CD7 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 6);
+      nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C6 */
+
+#if TIVA_I2C_USE_I2C7
+    if (&I2CD8 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 7);
+      nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C7 */
+
+#if TIVA_I2C_USE_I2C8
+    if (&I2CD9 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 8);
+      nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C7 */
+
+#if TIVA_I2C_USE_I2C9
+    if (&I2CD10 == i2cp) {
+      SYSCTL->RCGCI2C |= (1 << 9);
+      nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY);
+    }
+#endif /* TIVA_I2C_USE_I2C7 */
+  }
+
+  dp->MCR = 0x10;
+  dp->MTPR = MTPR_VALUE;
+}
+
+/**
+ * @brief   Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp)
+{
+  I2C_TypeDef *dp = i2cp->i2c;
+  /* If not in stopped state then disables the I2C clock.*/
+  if (i2cp->state != I2C_STOP) {
+
+    /* I2C disable.*/
+    // TODO: abort i2c operation
+    //i2c_lld_abort_operation(i2cp);
+
+#if TIVA_I2C_USE_I2C0
+    if (&I2CD1 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 0);
+      nvicDisableVector(TIVA_I2C0_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C0 */
+
+#if TIVA_I2C_USE_I2C1
+    if (&I2CD2 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 1);
+      nvicDisableVector(TIVA_I2C1_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C1 */
+
+#if TIVA_I2C_USE_I2C2
+    if (&I2CD3 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 2);
+      nvicDisableVector(TIVA_I2C2_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C2 */
+
+#if TIVA_I2C_USE_I2C3
+    if (&I2CD4 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 3);
+      nvicDisableVector(TIVA_I2C3_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C3 */
+
+#if TIVA_I2C_USE_I2C4
+    if (&I2CD5 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 4);
+      nvicDisableVector(TIVA_I2C4_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C4 */
+
+#if TIVA_I2C_USE_I2C5
+    if (&I2CD6 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 5);
+      nvicDisableVector(TIVA_I2C5_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C5 */
+
+#if TIVA_I2C_USE_I2C6
+    if (&I2CD7 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 6);
+      nvicDisableVector(TIVA_I2C6_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C6 */
+
+#if TIVA_I2C_USE_I2C7
+    if (&I2CD8 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 7);
+      nvicDisableVector(TIVA_I2C7_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C7 */
+
+#if TIVA_I2C_USE_I2C8
+    if (&I2CD9 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 8);
+      nvicDisableVector(TIVA_I2C8_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C8 */
+
+#if TIVA_I2C_USE_I2C9
+    if (&I2CD10 == i2cp) {
+      SYSCTL->RCGCI2C &= ~(1 << 9);
+      nvicDisableVector(TIVA_I2C9_NUMBER);
+    }
+#endif /* TIVA_I2C_USE_I2C9 */
+
+  dp->MCR = 0;
+  dp->MTPR = 0;
+  }
+}
+
+/**
+ * @brief   Receives data via the I2C bus as master.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] addr      slave device address
+ * @param[out] rxbuf    pointer to the receive buffer
+ * @param[in] rxbytes   number of bytes to be received
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval RDY_OK       if the function succeeded.
+ * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
+ *                      be retrieved using @p i2cGetErrors().
+ * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
+ *                      timeout the driver must be stopped and restarted
+ *                      because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                     uint8_t *rxbuf, size_t rxbytes,
+                                     systime_t timeout)
+{
+  I2C_TypeDef *dp = i2cp->i2c;
+  systime_t start, end;
+
+  i2cp->rxbuf = rxbuf;
+  i2cp->rxbytes = rxbytes;
+
+  /* Resetting error flags for this transfer.*/
+  i2cp->errors = I2C_NO_ERROR;
+
+  /* Initializes driver fields, LSB = 1 -> receive.*/
+  i2cp->addr = (addr << 1) | 0x01;
+
+  /* Releases the lock from high level driver.*/
+  osalSysUnlock();
+
+  /* Calculating the time window for the timeout on the busy bus condition.*/
+  start = osalOsGetSystemTimeX();
+  end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT);
+
+  /* Waits until BUSY flag is reset or, alternatively, for a timeout
+     condition.*/
+  while (true) {
+    osalSysLock();
+
+    /* If the bus is not busy then the operation can continue, note, the
+       loop is exited in the locked state.*/
+    if ((dp->MCS & TIVA_MCS_BUSY) == 0)
+      break;
+
+    /* If the system time went outside the allowed window then a timeout
+       condition is returned.*/
+    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+      return MSG_TIMEOUT;
+
+    osalSysUnlock();
+  }
+
+  /* set slave address */
+  dp->MSA = addr;
+
+  /* Starts the operation.*/
+  dp->MCS = TIVA_I2C_SINGLE_RECEIVE;
+
+  /* Waits for the operation completion or a timeout.*/
+  return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+}
+
+/**
+ * @brief   Transmits data via the I2C bus as master.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ * @param[in] addr      slave device address
+ * @param[in] txbuf     pointer to the transmit buffer
+ * @param[in] txbytes   number of bytes to be transmitted
+ * @param[out] rxbuf    pointer to the receive buffer
+ * @param[in] rxbytes   number of bytes to be received
+ * @param[in] timeout   the number of ticks before the operation timeouts,
+ *                      the following special values are allowed:
+ *                      - @a TIME_INFINITE no timeout.
+ *                      .
+ * @return              The operation status.
+ * @retval RDY_OK       if the function succeeded.
+ * @retval RDY_RESET    if one or more I2C errors occurred, the errors can
+ *                      be retrieved using @p i2cGetErrors().
+ * @retval RDY_TIMEOUT  if a timeout occurred before operation end. <b>After a
+ *                      timeout the driver must be stopped and restarted
+ *                      because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                      const uint8_t *txbuf, size_t txbytes,
+                                      uint8_t *rxbuf, size_t rxbytes,
+                                      systime_t timeout)
+{
+  I2C_TypeDef *dp = i2cp->i2c;
+  systime_t start, end;
+
+  i2cp->rxbuf = rxbuf;
+  i2cp->rxbytes = rxbytes;
+  i2cp->txbuf = txbuf;
+  i2cp->txbytes = txbytes;
+
+  /* Resetting error flags for this transfer.*/
+  i2cp->errors = I2C_NO_ERROR;
+
+  /* Releases the lock from high level driver.*/
+  osalSysUnlock();
+
+  /* Calculating the time window for the timeout on the busy bus condition.*/
+  start = osalOsGetSystemTimeX();
+  end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT);
+
+  /* Waits until BUSY flag is reset or, alternatively, for a timeout
+     condition.*/
+  while (true) {
+    osalSysLock();
+
+    /* If the bus is not busy then the operation can continue, note, the
+       loop is exited in the locked state.*/
+    if ((dp->MCS & TIVA_MCS_BUSY) == 0)
+      break;
+
+    /* If the system time went outside the allowed window then a timeout
+       condition is returned.*/
+    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+      return MSG_TIMEOUT;
+
+    osalSysUnlock();
+  }
+
+  /* Initializes driver fields, LSB = 0 -> write.*/
+  i2cp->addr = addr << 1 | 0;
+
+  /* set slave address */
+  dp->MSA = i2cp->addr;
+
+  /* enable interrupts */
+  dp->MIMR = TIVA_MIMR_IM;
+
+  /* put data in register */
+  dp->MDR = *(i2cp->txbuf);
+
+  /* check if 1 or more bytes */
+  if (i2cp->txbytes == 1) {
+    if (i2cp->rxbytes == 1) {
+      // one byte read
+      i2cp->intstate = STATE_READ_ONE;
+    }
+    else {
+      // multiple byte read
+      i2cp->intstate = STATE_READ_FIRST;
+    }
+    // single byte send
+    dp->MCS = TIVA_I2C_SIGNLE_SEND;
+  }
+  else {
+    if (i2cp->txbytes == 2) {
+      // 2 bytes
+      i2cp->intstate = STATE_WRITE_FINAL;
+    }
+    else {
+      // more then 2 bytes
+      i2cp->intstate = STATE_WRITE_NEXT;
+    }
+    // multiple bytes start send
+    dp->MCS = TIVA_I2C_BURST_SEND_START;
+  }
+
+  i2cp->txbuf++;
+  i2cp->txbytes--;
+
+  /* Waits for the operation completion or a timeout.*/
+  return osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/i2c_lld.h b/os/hal/ports/TIVA/LLD/i2c_lld.h
new file mode 100644
index 0000000..9b7b743
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/i2c_lld.h
@@ -0,0 +1,527 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/i2c_lld.h
+ * @brief   TM4C123x/TM4C129x I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef _I2C_LLD_H_
+#define _I2C_LLD_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define MTPR_VALUE          ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1)
+
+#define TIVA_MSA_RS         (1 << 0)
+#define TIVA_MSA_SA         (127 << 1)
+
+#define TIVA_MCS_BUSY       (1 << 0)
+#define TIVA_MCS_ERROR      (1 << 1)
+#define TIVA_MCS_ADRACK     (1 << 2)
+#define TIVA_MCS_DATACK     (1 << 3)
+#define TIVA_MCS_ARBLST     (1 << 4)
+#define TIVA_MCS_IDLE       (1 << 5)
+#define TIVA_MCS_BUSBSY     (1 << 6)
+#define TIVA_MCS_CLKTO      (1 << 7)
+
+#define TIVA_MCS_RUN        (1 << 0)
+#define TIVA_MCS_START      (1 << 1)
+#define TIVA_MCS_STOP       (1 << 2)
+#define TIVA_MCS_ACK        (1 << 3)
+#define TIVA_MCS_HS         (1 << 4)
+
+#define TIVA_I2C_SIGNLE_SEND                (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_START           (TIVA_MCS_RUN | TIVA_MCS_START)
+#define TIVA_I2C_BURST_SEND_CONTINUE        (TIVA_MCS_RUN)
+#define TIVA_I2C_BURST_SEND_FINISH          (TIVA_MCS_RUN | TIVA_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_STOP            (TIVA_MCS_STOP)
+#define TIVA_I2C_BURST_SEND_ERROR_STOP      (TIVA_MCS_STOP)
+
+#define TIVA_I2C_SINGLE_RECEIVE             (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_START        (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_CONTINUE     (TIVA_MCS_RUN | TIVA_MCS_ACK)
+#define TIVA_I2C_BURST_RECEIVE_FINISH       (TIVA_MCS_RUN | TIVA_MCS_STOP)
+#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP   (TIVA_MCS_STOP)
+
+#define TIVA_MDR_DATA       (255 << 0)
+
+#define TIVA_MTPR_TPR       (127 << 0)
+#define TIVA_MTPR_HS        (1 << 7)
+
+#define TIVA_MIMR_IM        (1 << 0)
+#define TIVA_MIMR_CLKIM     (1 << 1)
+
+#define TIVA_MRIS_RIS       (1 << 0)
+#define TIVA_MRIS_CLKRIS    (1 << 1)
+
+#define TIVA_MMIS_MIS       (1 << 0)
+#define TIVA_MMIS_CLKMIS    (1 << 1)
+
+#define TIVA_MICR_IC        (1 << 0)
+#define TIVA_MICR_CLKIC     (1 << 1)
+
+#define TIVA_MCR_LPBK       (1 << 0)
+#define TIVA_MCR_MFE        (1 << 4)
+#define TIVA_MCR_SFE        (1 << 5)
+#define TIVA_MCR_GFE        (1 << 6)
+
+#define TIVA_MCLKOCNT_CNTL  (255 << 0)
+
+#define TIVA_MBMON_SCL      (1 << 0)
+#define TIVA_MBMON_SDA      (1 << 1)
+
+#define TIVA_MCR2_GFPW      (7 << 4)
+
+// interrupt states
+#define STATE_IDLE          0
+#define STATE_WRITE_NEXT    1
+#define STATE_WRITE_FINAL   2
+#define STATE_WAIT_ACK      3
+#define STATE_SEND_ACK      4
+#define STATE_READ_ONE      5
+#define STATE_READ_FIRST    6
+#define STATE_READ_NEXT     7
+#define STATE_READ_FINAL    8
+#define STATE_READ_WAIT     9
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+/**
+ * @brief   I2C0 driver enable switch.
+ * @details If set to @p TRUE the support for I2C0 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C0) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C0           FALSE
+#endif
+
+/**
+ * @brief   I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C1           FALSE
+#endif
+
+/**
+ * @brief   I2C2 driver enable switch.
+ * @details If set to @p TRUE the support for I2C2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C2) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C2           FALSE
+#endif
+
+/**
+ * @brief   I2C3 driver enable switch.
+ * @details If set to @p TRUE the support for I2C3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C3) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C3           FALSE
+#endif
+
+/**
+ * @brief   I2C4 driver enable switch.
+ * @details If set to @p TRUE the support for I2C4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C4) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C4           FALSE
+#endif
+
+/**
+ * @brief   I2C5 driver enable switch.
+ * @details If set to @p TRUE the support for I2C5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C5) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C5           FALSE
+#endif
+
+/**
+ * @brief   I2C6 driver enable switch.
+ * @details If set to @p TRUE the support for I2C6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C6) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C6           FALSE
+#endif
+
+/**
+ * @brief   I2C7 driver enable switch.
+ * @details If set to @p TRUE the support for I2C7 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C7) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C7           FALSE
+#endif
+
+/**
+ * @brief   I2C8 driver enable switch.
+ * @details If set to @p TRUE the support for I2C8 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C8) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C8           FALSE
+#endif
+
+/**
+ * @brief   I2C9 driver enable switch.
+ * @details If set to @p TRUE the support for I2C9 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_I2C_USE_I2C9) || defined(__DOXYGEN__)
+#define TIVA_I2C_USE_I2C9           FALSE
+#endif
+
+/**
+ * @brief   I2C timeout on busy condition in milliseconds.
+ */
+#if !defined(TIVA_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
+#define TIVA_I2C_BUSY_TIMEOUT       50
+#endif
+
+/**
+ * @brief   I2C0 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C0_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C1 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C1_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C2 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C2_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C3 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C3_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C4 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C4_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C5 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C5_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C6 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C6_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C7 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C7_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C8 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C8_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C8_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @brief   I2C9 interrupt priority level setting.
+ */
+#if !defined(TIVA_I2C_I2C9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_I2C_I2C9_IRQ_PRIORITY  4
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/**
+ * @brief  error checks
+ */
+#if !TIVA_I2C_USE_I2C0 && !TIVA_I2C_USE_I2C1 && !TIVA_I2C_USE_I2C2 && \
+    !TIVA_I2C_USE_I2C3 && !TIVA_I2C_USE_I2C4 && !TIVA_I2C_USE_I2C5 && \
+    !TIVA_I2C_USE_I2C6 && !TIVA_I2C_USE_I2C7 && !TIVA_I2C_USE_I2C8 && \
+    !TIVA_I2C_USE_I2C9
+#error "I2C driver activated but no I2C peripheral assigned"
+#endif
+
+#if TIVA_I2C_USE_I2C0 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C0"
+#endif
+
+#if TIVA_I2C_USE_I2C1 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C1"
+#endif
+
+#if TIVA_I2C_USE_I2C2 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C2"
+#endif
+
+#if TIVA_I2C_USE_I2C3 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C3"
+#endif
+
+#if TIVA_I2C_USE_I2C4 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C4"
+#endif
+
+#if TIVA_I2C_USE_I2C5 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C5"
+#endif
+
+#if TIVA_I2C_USE_I2C6 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C6"
+#endif
+
+#if TIVA_I2C_USE_I2C7 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C7"
+#endif
+
+#if TIVA_I2C_USE_I2C8 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C8"
+#endif
+
+#if TIVA_I2C_USE_I2C9 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to I2C9"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type representing I2C address.
+ */
+typedef uint16_t i2caddr_t;
+
+/**
+ * @brief   I2C Driver condition flags type.
+ */
+typedef uint32_t i2cflags_t;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct
+{
+  /**
+   * @brief Specifies the clock frequency.
+   * @note  Must be set to a value lower than 3.33Mbps.
+   * TODO: high-speed mode: 3333 kHz. setup is 100-400-1000 kHz then switched to 3333 kHz
+   */
+  uint32_t        clock_speed;
+} I2CConfig;
+
+/**
+ * @brief   Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+  /**
+   * @brief   Driver state.
+   */
+  i2cstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const I2CConfig           *config;
+  /**
+   * @brief   Error flags.
+   */
+  i2cflags_t                errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the bus.
+   */
+  mutex_t                   mutex;
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+  I2C_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief     Thread waiting for I/O completion.
+   */
+  thread_reference_t        thread;
+  /**
+   * @brief     Current slave address without R/W bit.
+   */
+  i2caddr_t                 addr;
+  /**
+   * @brief     Pointer to the buffer with data to send.
+   */
+  const uint8_t             *txbuf;
+  /**
+   * @brief     Number of bytes of data to send.
+   */
+  size_t                    txbytes;
+  /**
+   * @brief     Pointer to the buffer to put received data.
+   */
+  uint8_t                   *rxbuf;
+    /**
+   * @brief     Number of bytes of data to receive.
+   */
+  size_t                    rxbytes;
+  /**
+   * @brief     State of the interrupt state machine.
+   *
+   * TODO is it possible to remove the interrupt state?
+   */
+  uint8_t                   intstate;
+  /**
+   * @brief     Pointer to the I2Cx registers block.
+   */
+  I2C_TypeDef               *i2c;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Get errors from I2C driver.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+#if TIVA_I2C_USE_I2C0
+extern I2CDriver I2CD1;
+#endif
+
+#if TIVA_I2C_USE_I2C1
+extern I2CDriver I2CD2;
+#endif
+
+#if TIVA_I2C_USE_I2C2
+extern I2CDriver I2CD3;
+#endif
+
+#if TIVA_I2C_USE_I2C3
+extern I2CDriver I2CD4;
+#endif
+
+#if TIVA_I2C_USE_I2C4
+extern I2CDriver I2CD5;
+#endif
+
+#if TIVA_I2C_USE_I2C5
+extern I2CDriver I2CD6;
+#endif
+
+#if TIVA_I2C_USE_I2C6
+extern I2CDriver I2CD7;
+#endif
+
+#if TIVA_I2C_USE_I2C7
+extern I2CDriver I2CD8;
+#endif
+
+#if TIVA_I2C_USE_I2C8
+extern I2CDriver I2CD9;
+#endif
+
+#if TIVA_I2C_USE_I2C9
+extern I2CDriver I2CD10;
+#endif
+
+#endif /* !defined(__DOXYGEN__) */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void i2c_lld_init(void);
+  void i2c_lld_start(I2CDriver *i2cp);
+  void i2c_lld_stop(I2CDriver *i2cp);
+  msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                        const uint8_t *txbuf, size_t txbytes,
+                                        uint8_t *rxbuf, size_t rxbytes,
+                                        systime_t timeout);
+  msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+                                       uint8_t *rxbuf, size_t rxbytes,
+                                       systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C  */
+
+#endif /* _I2C_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/pal_lld.c b/os/hal/ports/TIVA/LLD/pal_lld.c
new file mode 100644
index 0000000..657f982
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/pal_lld.c
@@ -0,0 +1,313 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/pal_lld.c
+ * @brief   TM4C123x/TM4C129x PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define RCGCGPIOA       (1 << 0)
+#define RCGCGPIOB       (1 << 1)
+#define RCGCGPIOC       (1 << 2)
+#define RCGCGPIOD       (1 << 3)
+#define RCGCGPIOE       (1 << 4)
+#define RCGCGPIOF       (1 << 5)
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+#define RCGCGPIOG       (1 << 6)
+#else
+#define RCGCGPIOG       0
+#endif
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+#define RCGCGPIOH       (1 << 7)
+#else
+#define RCGCGPIOH       0
+#endif
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+#define RCGCGPIOJ       (1 << 8)
+#else
+#define RCGCGPIOJ       0
+#endif
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+#define RCGCGPIOK       (1 << 9)
+#else
+#define RCGCGPIOK       0
+#endif
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+#define RCGCGPIOL       (1 << 10)
+#else
+#define RCGCGPIOL       0
+#endif
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+#define RCGCGPIOM       (1 << 11)
+#else
+#define RCGCGPIOM       0
+#endif
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+#define RCGCGPION       (1 << 12)
+#else
+#define RCGCGPION       0
+#endif
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+#define RCGCGPIOP       (1 << 13)
+#else
+#define RCGCGPIOP       0
+#endif
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+#define RCGCGPIOQ       (1 << 14)
+#else
+#define RCGCGPIOQ       0
+#endif
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+#define RCGCGPIOR       (1 << 15)
+#else
+#define RCGCGPIOR       0
+#endif
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+#define RCGCGPIOS       (1 << 16)
+#else
+#define RCGCGPIOS       0
+#endif
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+#define RCGCGPIOT       (1 << 17)
+#else
+#define RCGCGPIOT       0
+#endif
+
+#define RCGCGPIO_VALUE  (RCGCGPIOA | RCGCGPIOB | RCGCGPIOC | RCGCGPIOD |      \
+                         RCGCGPIOE | RCGCGPIOF | RCGCGPIOG | RCGCGPIOH |      \
+                         RCGCGPIOJ | RCGCGPIOK | RCGCGPIOL | RCGCGPIOM |      \
+                         RCGCGPION | RCGCGPIOP | RCGCGPIOQ | RCGCGPIOR |      \
+                         RCGCGPIOS | RCGCGPIOT)
+
+/* GPIO lock password.*/
+#define TIVA_GPIO_LOCK_PWD                  0x4C4F434B
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+void gpio_init (GPIO_TypeDef *gpiop, const tiva_gpio_setup_t *config)
+{
+  gpiop->DATA   = config->data;
+  gpiop->DIR    = config->dir;
+  gpiop->AFSEL  = config->afsel;
+  gpiop->DR2R   = config->dr2r;
+  gpiop->DR4R   = config->dr4r;
+  gpiop->DR8R   = config->dr8r;
+  gpiop->ODR    = config->odr;
+  gpiop->PUR    = config->pur;
+  gpiop->PDR    = config->pdr;
+  gpiop->SLR    = config->slr;
+  gpiop->DEN    = config->den;
+  gpiop->AMSEL  = config->amsel;
+  gpiop->PCTL   = config->pctl;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   TIVA I/O ports configuration.
+ * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled.
+ *
+ * @param[in] config    the TIVA ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config)
+{
+  SYSCTL->RCGCGPIO = RCGCGPIO_VALUE;
+
+  __NOP();
+  __NOP();
+  __NOP();
+  
+  gpio_init(GPIOA, &config->PAData);
+
+  gpio_init(GPIOB, &config->PBData);
+
+  GPIOC->LOCK = TIVA_GPIO_LOCK_PWD;
+  GPIOC->CR = 0x01;
+  gpio_init(GPIOC, &config->PCData);
+  GPIOC->LOCK = 0;
+
+  gpio_init(GPIOD, &config->PDData);
+
+  gpio_init(GPIOE, &config->PEData);
+
+  GPIOF->LOCK = TIVA_GPIO_LOCK_PWD;
+  GPIOF->CR = 0x01;
+  gpio_init(GPIOF, &config->PFData);
+  GPIOF->LOCK = 0;
+  
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_init(GPIOG, &config->PGData);
+#endif /* TIVA_HAS_GPIOG.*/
+  
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_init(GPIOH, &config->PHData);
+#endif /* TIVA_HAS_GPIOH.*/
+  
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_init(GPIOJ, &config->PJData);
+#endif /* TIVA_HAS_GPIOJ.*/
+  
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_init(GPIOK, &config->PKData);
+#endif /* TIVA_HAS_GPIOK.*/
+  
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+  gpio_init(GPIOL, &config->PLData);
+#endif /* TIVA_HAS_GPIOL.*/
+  
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+  gpio_init(GPIOM, &config->PMData);
+#endif /* TIVA_HAS_GPIOM.*/
+  
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+  gpio_init(GPION, &config->PNData);
+#endif /* TIVA_HAS_GPION.*/
+  
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+  gpio_init(GPIOP, &config->PPData);
+#endif /* TIVA_HAS_GPIOP.*/
+  
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+  gpio_init(GPIOQ, &config->PQData);
+#endif /* TIVA_HAS_GPIOQ.*/
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+  gpio_init(GPIOR, &config->PRData);
+#endif /* TIVA_HAS_GPIOR.*/
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+  gpio_init(GPIOS, &config->PSData);
+#endif /* TIVA_HAS_GPIOS.*/
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+  gpio_init(GPIOT, &config->PTData);
+#endif /* TIVA_HAS_GPIOT.*/
+}
+
+/**
+ * @brief   Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ *
+ * @param[in] port      the port identifier
+ * @param[in] mask      the group mask
+ * @param[in] mode      the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+                           ioportmask_t mask,
+                           iomode_t mode)
+{
+  /* TODO: What does this function exactly do? The pins are already configured
+   * in board.h and initialized by the pal driver. */
+
+  (void) port;
+  (void) mask;
+  (void) mode;
+
+  /*
+  switch (mode) {
+  case PAL_MODE_UNCONNECTED:
+  case PAL_MODE_INPUT_PULLUP:
+    port->PUR |= mask;
+  case PAL_MODE_INPUT:
+    port->AFSEL &= ~mask;
+    port->DIR &= ~mask;
+    port->ODR &= ~mask;
+    port->DEN |= mask;
+    break;
+
+  case PAL_MODE_INPUT_PULLDOWN:
+    port->AFSEL &= ~mask;
+    port->DIR &= ~mask;
+    port->ODR &= ~mask;
+    port->DEN |= mask;
+    port->PDR |= mask;
+    break;
+
+  case PAL_MODE_RESET:
+  case PAL_MODE_INPUT_ANALOG:
+    port->AFSEL &= ~mask;
+    port->DIR &= ~mask;
+    port->ODR &= ~mask;
+    port->DEN &= ~mask;
+    port->PUR &= ~mask;
+    port->PDR &= ~mask;
+    break;
+
+  case PAL_MODE_OUTPUT_PUSHPULL:
+    port->AFSEL &= ~mask;
+    port->DIR |= mask;
+    port->ODR &= ~mask;
+    port->DEN |= mask;
+    break;
+
+  case PAL_MODE_OUTPUT_OPENDRAIN:
+    port->AFSEL &= ~mask;
+    port->DIR |= mask;
+    port->ODR |= mask;
+    port->DEN |= mask;
+    break;
+  }*/
+}
+
+#endif /* HAL_USE_PAL */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/pal_lld.h b/os/hal/ports/TIVA/LLD/pal_lld.h
new file mode 100644
index 0000000..a87e5fd
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/pal_lld.h
@@ -0,0 +1,466 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/pal_lld.h
+ * @brief   TM4C123x/TM4C129x PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes                                      */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* I/O Ports Types and constants.                                            */
+/*===========================================================================*/
+
+/**	
+ * @brief   GPIO port setup info.
+ */
+typedef struct 
+{
+  /** @brief Initial value for DATA register.*/
+  uint32_t data;
+  /** @brief Initial value for DIR register.*/
+  uint32_t dir;
+  /** @brief Initial value for AFSEL register.*/
+  uint32_t afsel;
+  /** @brief Initial value for DR2R register.*/
+  uint32_t dr2r;
+  /** @brief Initial value for DR4R register.*/
+  uint32_t dr4r;
+  /** @brief Initial value for DR8R register.*/
+  uint32_t dr8r;
+  /** @brief Initial value for ODR register.*/
+  uint32_t odr;
+  /** @brief Initial value for PUR register.*/
+  uint32_t pur;
+  /** @brief Initial value for PDR register.*/
+  uint32_t pdr;
+  /** @brief Initial value for SLR register.*/
+  uint32_t slr;
+  /** @brief Initial value for DEN register.*/
+  uint32_t den;
+  /** @brief Initial value for AMSEL register.*/
+  uint32_t amsel;
+  /** @brief Initial value for PCTL register.*/
+  uint32_t pctl;
+} tiva_gpio_setup_t;
+
+/**
+ * @brief   Tiva GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ *          system startup time in order to initialized the digital I/O
+ *          subsystem. This represents only the initial setup, specific pads
+ *          or whole ports can be reprogrammed at later time.
+ */
+typedef struct
+{
+  /** @brief Port A setup data.*/
+  tiva_gpio_setup_t     PAData;
+  /** @brief Port B setup data.*/
+  tiva_gpio_setup_t     PBData;
+  /** @brief Port C setup data.*/
+  tiva_gpio_setup_t     PCData;
+  /** @brief Port D setup data.*/
+  tiva_gpio_setup_t     PDData;
+  /** @brief Port E setup data.*/
+  tiva_gpio_setup_t     PEData;
+  /** @brief Port F setup data.*/
+  tiva_gpio_setup_t     PFData;
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+  /** @brief Port G setup data.*/
+  tiva_gpio_setup_t     PGData;
+#endif /* TIVA_HAS_GPIOG.*/
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+  /** @brief Port H setup data.*/
+  tiva_gpio_setup_t     PHData;
+#endif /* TIVA_HAS_GPIOH.*/
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+  /** @brief Port J setup data.*/
+  tiva_gpio_setup_t     PJData;
+#endif /* TIVA_HAS_GPIOJ.*/
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+  /** @brief Port K setup data.*/
+  tiva_gpio_setup_t     PKData;
+#endif /* TIVA_HAS_GPIOK.*/
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+  /** @brief Port L setup data.*/
+  tiva_gpio_setup_t     PLData;
+#endif /* TIVA_HAS_GPIOL.*/
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+  /** @brief Port M setup data.*/
+  tiva_gpio_setup_t     PMData;
+#endif /* TIVA_HAS_GPIOM.*/
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+  /** @brief Port N setup data.*/
+  tiva_gpio_setup_t     PNData;
+#endif /* TIVA_HAS_GPION.*/
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+  /** @brief Port P setup data.*/
+  tiva_gpio_setup_t     PPData;
+#endif /* TIVA_HAS_GPIOP.*/
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+  /** @brief Port Q setup data.*/
+  tiva_gpio_setup_t     PQData;
+#endif /* TIVA_HAS_GPIOQ.*/
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+  /** @brief Port R setup data.*/
+  tiva_gpio_setup_t     PRData;
+#endif /* TIVA_HAS_GPIOR.*/
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+  /** @brief Port S setup data.*/
+  tiva_gpio_setup_t     PSData;
+#endif /* TIVA_HAS_GPIOS.*/
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+  /** @brief Port T setup data.*/
+  tiva_gpio_setup_t     PTData;
+#endif /* TIVA_HAS_GPIOT.*/
+} PALConfig;
+
+/**
+ * @brief   Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 8
+
+/**
+ * @brief   Whole port mask.
+ * @brief   This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
+
+/**
+ * @brief   Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief   Digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief   Port Identifier.
+ */
+typedef GPIO_TypeDef *ioportid_t;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers.                                                    */
+/*===========================================================================*/
+
+/** @brief   GPIOA port identifier.*/
+#define IOPORT1         GPIOA
+
+/** @brief   GPIOB port identifier.*/
+#define IOPORT2         GPIOB
+
+/** @brief   GPIOC port identifier.*/
+#define IOPORT3         GPIOC
+
+/** @brief   GPIOD port identifier.*/
+#define IOPORT4         GPIOD
+
+/** @brief   GPIOE port identifier.*/
+#define IOPORT5         GPIOE
+
+/** @brief   GPIOF port identifier.*/
+#define IOPORT6         GPIOF
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+/** @brief Port G setup data.*/
+#define IOPORT7         GPIOG
+#endif /* TIVA_HAS_GPIOG.*/
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+/** @brief Port H setup data.*/
+#define IOPORT8         GPIOH
+#endif /* TIVA_HAS_GPIOH.*/
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+/** @brief Port J setup data.*/
+#define IOPORT9         GPIOJ
+#endif /* TIVA_HAS_GPIOJ.*/
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+/** @brief Port K setup data.*/
+#define IOPORT10        GPIOK
+#endif /* TIVA_HAS_GPIOK.*/
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+/** @brief Port L setup data.*/
+#define IOPORT11        GPIOL
+#endif /* TIVA_HAS_GPIOL.*/
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+/** @brief Port M setup data.*/
+#define IOPORT12        GPIOM
+#endif /* TIVA_HAS_GPIOM.*/
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+/** @brief Port N setup data.*/
+#define IOPORT13        GPION
+#endif /* TIVA_HAS_GPION.*/
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+/** @brief Port P setup data.*/
+#define IOPORT14        GPIOP
+#endif /* TIVA_HAS_GPIOP.*/
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+/** @brief Port Q setup data.*/
+#define IOPORT15        GPIOQ
+#endif /* TIVA_HAS_GPIOQ.*/
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+/** @brief Port R setup data.*/
+#define IOPORT16        GPIOR
+#endif /* TIVA_HAS_GPIOR.*/
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+/** @brief Port S setup data.*/
+#define IOPORT17        GPIOS
+#endif /* TIVA_HAS_GPIOS.*/
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+/** @brief Port T setup data.*/
+#define IOPORT18        GPIOT
+#endif /* TIVA_HAS_GPIOT.*/
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as      */
+/* functions, if so please put them in pal_lld.c.                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level PAL subsystem initialization.
+ *
+ * @param[in] config    architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief   Reads the physical I/O port states.
+ *
+ * @param[in] port      port identifier
+ * @return              The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port)  ((port)->DATA)
+
+/**
+ * @brief   Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ *          value.
+ *
+ * @param[in] port      port identifier
+ * @return              The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) ((port)->DATA)
+
+/**
+ * @brief   Writes a bits mask on a I/O port.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits)   ((port)->DATA = (bits))
+
+/**
+ * @brief   Sets a bits mask on a I/O port.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF)
+
+/**
+ * @brief   Clears a bits mask on a I/O port.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] bits      bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits)   ((port)->MASKED_ACCESS[bits] = 0)
+
+/**
+ * @brief   Reads a group of bits.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @return              The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset)   \
+  ((port)->MASKED_ACCESS[(mask) << (offset)])
+
+/**
+ * @brief   Writes a group of bits.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] bits      bits to be written. Values exceeding the group width
+ *                      are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits)    \
+  ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
+
+/**
+ * @brief   Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ *          with the specified mode.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] mask      group mask
+ * @param[in] offset    group bit offset within the port
+ * @param[in] mode      group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode)                      \
+  _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief   Reads a logical state from an I/O pad.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @return              The logical state.
+ * @retval PAL_LOW      low logical state.
+ * @retval PAL_HIGH     high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)])
+
+/**
+ * @brief   Writes a logical state on an output pad.
+ * @note    This function is not meant to be invoked directly by the
+ *          application  code.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] bit       logical value, the value must be @p PAL_LOW or
+ *                      @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit)    \
+  ((port)->MASKED_ACCESS[1 << (pad)] = (bit))
+
+/**
+ * @brief   Sets a pad logical state to @p PAL_HIGH.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad)   \
+  ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
+
+/**
+ * @brief   Clears a pad logical state to @p PAL_LOW.
+ * @note    The @ref PAL provides a default software implementation of this
+ *          functionality, implement this function if can optimize it by using
+ *          special hardware functionalities or special coding.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) \
+  ((port)->MASKED_ACCESS[1 << (pad)] = 0)
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void _pal_lld_init(const PALConfig *config);
+  void _pal_lld_setgroupmode(ioportid_t port,
+                             ioportmask_t mask,
+                             iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* _PAL_LLD_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/pwm_lld.c b/os/hal/ports/TIVA/LLD/pwm_lld.c
new file mode 100644
index 0000000..c0ee9d7
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/pwm_lld.c
@@ -0,0 +1,577 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/pwm_lld.c
+ * @brief   TM4C123x/TM4C129x PWM subsystem low level driver.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define PWM_INT_CMPBD       (1 << 5)
+#define PWM_INT_CMPBU       (1 << 4)
+#define PWM_INT_CMPAD       (1 << 3)
+#define PWM_INT_CMPAU       (1 << 2)
+#define PWM_INT_CNTLOAD     (1 << 1)
+#define PWM_INT_CNTZERO     (1 << 0)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   PWMD1 driver identifier.
+ */
+#if TIVA_PWM_USE_PWM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief   PWMD2 driver identifier.
+ */
+#if TIVA_PWM_USE_PWM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Common PWM Generator IRQ handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] i         pwm generator number
+ */
+static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i)
+{
+  uint32_t isc;
+
+  isc = pwmp->pwm->PWM[i].ISC;
+  pwmp->pwm->PWM[i].ISC = isc;
+
+  if (((isc & PWM_INT_CMPAD) != 0) &&
+      (pwmp->config->channels[i * 2 + 0].callback != NULL)) {
+    pwmp->config->channels[i * 2 + 0].callback(pwmp);
+  }
+
+  if (((isc & PWM_INT_CMPAU) != 0) &&
+      (pwmp->config->channels[i * 2 + 0].callback != NULL)) {
+    pwmp->config->channels[i * 2 + 0].callback(pwmp);
+  }
+
+  if (((isc & PWM_INT_CMPBD) != 0) &&
+      (pwmp->config->channels[i * 2 + 1].callback != NULL)) {
+    pwmp->config->channels[i * 2 + 1].callback(pwmp);
+  }
+
+  if (((isc & PWM_INT_CMPBU) != 0) &&
+      (pwmp->config->channels[i * 2 + 1].callback != NULL)) {
+    pwmp->config->channels[i * 2 + 1].callback(pwmp);
+  }
+
+  if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) {
+    pwmp->config->callback(pwmp);
+  }
+
+  if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) {
+    pwmp->config->callback(pwmp);
+  }
+}
+
+/**
+ * @brief   Common PWM fault IRQ handler.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ */
+static void pwm_lld_serve_fault_interrupt (PWMDriver *pwmp)
+{
+  (void) pwmp;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_PWM_USE_PWM0
+#if !defined(TIVA_PWM0FAULT_HANDLER)
+#error "TIVA_PWM0FAULT_HANDLER not defined"
+#endif
+/*
+ * @brief PWM0 Fault handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM0FAULT_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_fault_interrupt(&PWMD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM0GEN0_HANDLER)
+#error "TIVA_PWM0GEN0_HANDLER not defined"
+#endif
+/*
+ * @brief PWM0 Generator 0 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM0GEN0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM0GEN1_HANDLER)
+#error "TIVA_PWM0GEN1_HANDLER not defined"
+#endif
+/*
+ * @brief PWM0 Generator 1 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM0GEN1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM0GEN2_HANDLER)
+#error "TIVA_PWM0GEN2_HANDLER not defined"
+#endif
+/*
+ * @brief PWM0 Generator 2 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM0GEN2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM0GEN3_HANDLER)
+#error "TIVA_PWM0GEN3_HANDLER not defined"
+#endif
+/*
+ * @brief PWM0 Generator 3 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM0GEN3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_PWM_USE_PWM1
+#if !defined(TIVA_PWM1FAULT_HANDLER)
+#error "TIVA_PWM1FAULT_HANDLER not defined"
+#endif
+/*
+ * @brief PWM1 Fault handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM1FAULT_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_fault_interrupt(&PWMD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM1GEN0_HANDLER)
+#error "TIVA_PWM1GEN0_HANDLER not defined"
+#endif
+/*
+ * @brief PWM1 Generator 0 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM1GEN0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD2, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM1GEN1_HANDLER)
+#error "TIVA_PWM1GEN1_HANDLER not defined"
+#endif
+/*
+ * @brief PWM1 Generator 1 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM1GEN1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD2, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM1GEN2_HANDLER)
+#error "TIVA_PWM1GEN2_HANDLER not defined"
+#endif
+/*
+ * @brief PWM1 Generator 2 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM1GEN2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD2, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(TIVA_PWM1GEN3_HANDLER)
+#error "TIVA_PWM1GEN3_HANDLER not defined"
+#endif
+/*
+ * @brief PWM1 Generator 3 handler
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_PWM1GEN3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  pwm_lld_serve_generator_interrupt(&PWMD2, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void)
+{
+  /* Driver initialization.*/
+#if TIVA_PWM_USE_PWM0
+  pwmObjectInit(&PWMD1);
+  PWMD1.channels = PWM_CHANNELS;
+  PWMD1.pwm = PWM0;
+#endif
+
+#if TIVA_PWM_USE_PWM1
+  pwmObjectInit(&PWMD2);
+  PWMD2.channels = PWM_CHANNELS;
+  PWMD2.pwm = PWM1;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the PWM peripheral.
+ * @note    Starting a driver that is already in the @p PWM_READY state
+ *          disables all the active channels.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp)
+{
+  uint8_t i;
+  uint32_t invert = 0;
+  uint32_t enable = 0;
+
+  if (pwmp->state == PWM_STOP) {
+    /* Clock activation.*/
+#if TIVA_PWM_USE_PWM0
+    if (&PWMD1 == pwmp) {
+      SYSCTL->RCGCPWM = (1 << 0);
+      nvicEnableVector(TIVA_PWM0FAULT_NUMBER,
+                       TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM0GEN1_NUMBER, TIVA_PWM_PWM0_1_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM0GEN2_NUMBER, TIVA_PWM_PWM0_2_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM0GEN3_NUMBER, TIVA_PWM_PWM0_3_IRQ_PRIORITY);
+    }
+#endif
+
+#if TIVA_PWM_USE_PWM1
+    if (&PWMD2 == pwmp) {
+      SYSCTL->RCGCPWM = (1 << 1);
+      nvicEnableVector(TIVA_PWM1FAULT_NUMBER,
+                       TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM1GEN1_NUMBER, TIVA_PWM_PWM1_1_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM1GEN2_NUMBER, TIVA_PWM_PWM1_2_IRQ_PRIORITY);
+      nvicEnableVector(TIVA_PWM1GEN3_NUMBER, TIVA_PWM_PWM1_3_IRQ_PRIORITY);
+    }
+#endif
+  }
+  else {
+    /* Driver re-configuration scenario, it must be stopped first.*/
+    pwmp->pwm->PWM[0].CTL = 0;
+    pwmp->pwm->PWM[1].CTL = 0;
+    pwmp->pwm->PWM[2].CTL = 0;
+    pwmp->pwm->PWM[3].CTL = 0;
+  }
+
+  /* Timer configuration.*/
+  for (i = 0; i  < (PWM_CHANNELS >> 1); i++) {
+    pwmp->pwm->PWM[i].CTL = 0;
+    pwmp->pwm->PWM[i].GEN[0] = 0x08C;
+    pwmp->pwm->PWM[i].GEN[1] = 0x80C;
+    pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1);
+    pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1);
+    pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1);
+  }
+
+  /* Output enables and polarities setup.*/
+  for (i = 0; i < PWM_CHANNELS; i++) {
+    switch (pwmp->config->channels[i].mode & PWM_OUTPUT_MASK) {
+    case PWM_OUTPUT_DISABLED:
+      enable &= ~(1 << i);
+      break;
+    case PWM_OUTPUT_ACTIVE_LOW:
+      invert |= (1 << i);
+      enable |= (1 << i);
+      break;
+    case PWM_OUTPUT_ACTIVE_HIGH:
+      invert &= ~(1 << i);
+      enable |= (1 << i);
+      break;
+    default:
+      ;
+    }
+  }
+
+  pwmp->pwm->INVERT = invert;
+  pwmp->pwm->ENABLE = enable;
+  pwmp->pwm->ISC = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp)
+{
+  /* If in ready state then disables the PWM clock.*/
+  if (pwmp->state == PWM_READY) {
+    pwmp->pwm->PWM[0].CTL = 0;
+    pwmp->pwm->PWM[1].CTL = 0;
+    pwmp->pwm->PWM[2].CTL = 0;
+    pwmp->pwm->PWM[3].CTL = 0;
+
+#if TIVA_PWM_USE_PWM0
+    if (&PWMD1 == pwmp) {
+      nvicDisableVector(TIVA_PWM0FAULT_NUMBER);
+      nvicDisableVector(TIVA_PWM0GEN0_NUMBER);
+      nvicDisableVector(TIVA_PWM0GEN1_NUMBER);
+      nvicDisableVector(TIVA_PWM0GEN2_NUMBER);
+      nvicDisableVector(TIVA_PWM0GEN3_NUMBER);
+      SYSCTL->RCGCPWM &= ~(1 << 0);
+    }
+#endif
+
+#if TIVA_PWM_USE_PWM1
+    if (&PWMD2 == pwmp) {
+      nvicDisableVector(TIVA_PWM1FAULT_NUMBER);
+      nvicDisableVector(TIVA_PWM1GEN0_NUMBER);
+      nvicDisableVector(TIVA_PWM1GEN1_NUMBER);
+      nvicDisableVector(TIVA_PWM1GEN2_NUMBER);
+      nvicDisableVector(TIVA_PWM1GEN3_NUMBER);
+      SYSCTL->RCGCPWM &= ~(1 << 1);
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Enables a PWM channel.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The channel is active using the specified configuration.
+ * @note    The function has effect at the next cycle start.
+ * @note    Channel notification is not enabled.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ * @param[in] width     PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+                            pwmchannel_t channel,
+                            pwmcnt_t width)
+{
+  /* Changing channel duty cycle on the fly.*/
+  pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width;
+  pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0);
+}
+
+/**
+ * @brief   Disables a PWM channel and its notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The channel is disabled and its output line returned to the
+ *          idle state.
+ * @note    The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel)
+{
+  pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0;
+  pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0);
+}
+
+/**
+ * @brief   Enables the periodic activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @note    If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp)
+{
+  uint32_t inten;
+  uint8_t i;
+
+  /* If the IRQ is not already enabled care must be taken to clear it,
+     it is probably already pending because the timer is running.*/
+  for(i = 0; i < (PWM_CHANNELS >> 1); i++) {
+    inten = pwmp->pwm->PWM[i].INTEN;
+    if ((inten & 0x03) == 0) {
+      pwmp->pwm->PWM[i].INTEN |= 0x03;
+      pwmp->pwm->PWM[i].ISC = 0x03;
+    }
+  }
+
+  pwmp->pwm->INTEN = 0x3f;
+}
+
+/**
+ * @brief   Disables the periodic activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @note    If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp)
+{
+  pwmp->pwm->PWM[0].INTEN &= ~(0x03);
+  pwmp->pwm->PWM[1].INTEN &= ~(0x03);
+  pwmp->pwm->PWM[2].INTEN &= ~(0x03);
+  pwmp->pwm->PWM[3].INTEN &= ~(0x03);
+  pwmp->pwm->INTEN &= ~(0x3F);
+}
+
+/**
+ * @brief   Enables a channel de-activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @pre     The channel must have been activated using @p pwmEnableChannel().
+ * @note    If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+                                         pwmchannel_t channel)
+{
+  uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN;
+
+  /* If the IRQ is not already enabled care must be taken to clear it,
+     it is probably already pending because the timer is running.*/
+  if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) {
+    pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2));
+    pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2));
+  }
+}
+
+/**
+ * @brief   Disables a channel de-activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @pre     The channel must have been activated using @p pwmEnableChannel().
+ * @note    If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+                                          pwmchannel_t channel)
+{
+  pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2));
+}
+
+#endif /* HAL_USE_PWM */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/pwm_lld.h b/os/hal/ports/TIVA/LLD/pwm_lld.h
new file mode 100644
index 0000000..70ba97b
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/pwm_lld.h
@@ -0,0 +1,372 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/pwm_lld.c
+ * @brief   TM4C123x/TM4C129x PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _PWM_LLD_H_
+#define _PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS                            8
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+/**
+ * @brief   PWMD1 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_PWM_USE_PWM0) || defined(__DOXYGEN__)
+#define TIVA_PWM_USE_PWM0                       FALSE
+#endif
+
+/**
+ * @brief   PWMD2 driver enable switch.
+ * @details If set to @p TRUE the support for PWMD2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_PWM_USE_PWM1) || defined(__DOXYGEN__)
+#define TIVA_PWM_USE_PWM1                       FALSE
+#endif
+
+/**
+ * @brief   PWMD1 fault interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__)
+#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief   PWMD1 channel 0 & 1 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM0_0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM0_0_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD1 channel 2 & 3 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM0_1_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD1 channel 4 & 5 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM0_2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM0_2_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD1 channel 6 & 7 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM0_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM0_3_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD2 fault interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__)
+#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY
+#endif
+
+/**
+ * @brief   PWMD2 channel 0 & 1 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM1_0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM1_0_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD2 channel 2 & 3 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM1_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM1_1_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD2 channel 4 & 5 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM1_2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM1_2_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @brief   PWMD2 channel 6 & 7 interrupt priority level setting.
+ */
+#if !defined(TIVA_PWM_PWM1_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PWM_PWM1_3_IRQ_PRIORITY            4
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Configuration checks.                                                     */
+/*===========================================================================*/
+
+#if TIVA_PWM_USE_PWM0 && !TIVA_HAS_PWM0
+#error "PWM0 not present in the selected device"
+#endif
+
+#if TIVA_PWM_USE_PWM1 && !TIVA_HAS_PWM1
+#error "PWM1 not present in the selected device"
+#endif
+
+#if !TIVA_PWM_USE_PWM0 && !TIVA_PWM_USE_PWM1
+#error "PWM driver activated but no PWM peripheral assigned"
+#endif
+
+#if TIVA_PWM_USE_PWM0 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM0 FAULT"
+#endif
+
+#if TIVA_PWM_USE_PWM0 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM0 GEN0"
+#endif
+
+#if TIVA_PWM_USE_PWM0 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM0 GEN1"
+#endif
+
+#if TIVA_PWM_USE_PWM0 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM0 GEN2"
+#endif
+
+#if TIVA_PWM_USE_PWM0 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM0 GEN3"
+#endif
+
+#if TIVA_PWM_USE_PWM1 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM1 FAULT"
+#endif
+
+#if TIVA_PWM_USE_PWM1 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM1 GEN0"
+#endif
+
+#if TIVA_PWM_USE_PWM1 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM1 GEN1"
+#endif
+
+#if TIVA_PWM_USE_PWM1 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM1 GEN2"
+#endif
+
+#if TIVA_PWM_USE_PWM1 &&                                                    \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PWM1 GEN3"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief   Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief   Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief   Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief   Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Channel active logic level.
+   */
+  pwmmode_t                 mode;
+  /**
+   * @brief Channel callback pointer.
+   * @note  This callback is invoked on the channel compare event. If set to
+   *        @p NULL then the callback is disabled.
+   */
+  pwmcallback_t             callback;
+  /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief   Type of a PWM driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   Timer clock in Hz.
+   * @note    The low level can use assertions in order to catch invalid
+   *          frequency specifications.
+   */
+  uint32_t                  frequency;
+  /**
+   * @brief   PWM period in ticks.
+   * @note    The low level can use assertions in order to catch invalid
+   *          period specifications.
+   */
+  pwmcnt_t                  period;
+  /**
+   * @brief Periodic callback pointer.
+   * @note  This callback is invoked on PWM counter reset. If set to
+   *        @p NULL then the callback is disabled.
+   */
+  pwmcallback_t             callback;
+  /**
+   * @brief Channels configurations.
+   */
+  PWMChannelConfig          channels[PWM_CHANNELS];
+  /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief   Structure representing a PWM driver.
+ */
+struct PWMDriver {
+  /**
+   * @brief Driver state.
+   */
+  pwmstate_t                state;
+  /**
+   * @brief Current driver configuration data.
+   */
+  const PWMConfig           *config;
+  /**
+   * @brief   Current PWM period in ticks.
+   */
+  pwmcnt_t                  period;
+  /**
+   * @brief   Mask of the enabled channels.
+   */
+  pwmchnmsk_t               enabled;
+  /**
+   * @brief   Number of channels in this instance.
+   */
+  pwmchannel_t              channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+  PWM_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the PWMx registers block.
+   */
+  PWM_TypeDef               *pwm;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ *          been activated using @p pwmStart().
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The PWM unit period is changed to the new value.
+ * @note    The function has effect at the next cycle start.
+ * @note    If a period is specified that is shorter than the pulse width
+ *          programmed in one of the channels then the behavior is not
+ *          guaranteed.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] period    new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period)                                  \
+  ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1));                     \
+  ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1));                     \
+  ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1));                     \
+  ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1))
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_PWM_USE_PWM0 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+
+#if TIVA_PWM_USE_PWM1 && !defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void pwm_lld_init(void);
+  void pwm_lld_start(PWMDriver *pwmp);
+  void pwm_lld_stop(PWMDriver *pwmp);
+  void pwm_lld_enable_channel(PWMDriver *pwmp,
+                              pwmchannel_t channel,
+                              pwmcnt_t width);
+  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+  void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+  void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+  void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+                                           pwmchannel_t channel);
+  void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+                                            pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* _PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/serial_lld.c b/os/hal/ports/TIVA/LLD/serial_lld.c
new file mode 100644
index 0000000..6874e5e
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/serial_lld.c
@@ -0,0 +1,632 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/serial_lld.c
+ * @brief   Tiva low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief UART0 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/**
+ * @brief UART1 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/**
+ * @brief UART2 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/**
+ * @brief UART3 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+/**
+ * @brief UART4 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+/**
+ * @brief UART5 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
+/**
+ * @brief UART6 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
+SerialDriver SD7;
+#endif
+
+/**
+ * @brief UART7 serial driver identifier.
+ */
+#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+SerialDriver SD8;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig sd_default_config =
+{
+  SERIAL_DEFAULT_BITRATE,
+  TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8,
+  TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   UART initialization.
+ *
+ * @param[in] sdp       communication channel associated to the UART
+ * @param[in] config    the architecture-dependent serial driver configuration
+ */
+static void uart_init(SerialDriver *sdp, const SerialConfig *config)
+{
+  UART_TypeDef *u = sdp->uart;
+  uint32_t div;  /* baud rate divisor */
+
+  /* disable the UART before any of the control registers are reprogrammed */
+  u->CTL &= ~TIVA_CTL_UARTEN;
+  div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2;
+  u->IBRD = div / 64;   /* integer portion of the baud rate divisor */
+  u->FBRD = div % 64;   /* fractional portion of the baud rate divisor */
+  u->LCRH = config->sc_lcrh;   /* set data format */
+  u->IFLS = config->sc_ifls;
+  u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN;
+  u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM;   /* interrupts enable */
+}
+
+/**
+ * @brief   UART de-initialization.
+ *
+ * @param[in] u         pointer to an UART I/O block
+ */
+static void uart_deinit(UART_TypeDef *u)
+{
+  u->CTL &= ~TIVA_CTL_UARTEN;
+}
+
+/**
+ * @brief   Error handling routine.
+ *
+ * @param[in] sdp       communication channel associated to the UART
+ * @param[in] err       UART LSR register value
+ */
+static void set_error(SerialDriver *sdp, uint16_t err)
+{
+  eventflags_t sts = 0;
+  
+  if (err & TIVA_MIS_FEMIS)
+    sts |= SD_FRAMING_ERROR;
+  if (err & TIVA_MIS_PEMIS)
+    sts |= SD_PARITY_ERROR;
+  if (err & TIVA_MIS_BEMIS)
+    sts |= SD_BREAK_DETECTED;
+  if (err & TIVA_MIS_OEMIS)
+    sts |= SD_OVERRUN_ERROR;
+  osalSysLockFromISR();
+  chnAddFlagsI(sdp, sts);
+  osalSysUnlockFromISR();
+}
+
+/**
+ * @brief   Common IRQ handler.
+ * @note    Tries hard to clear all the pending interrupt sources, we don't
+ *          want to go through the whole ISR and have another interrupt soon
+ *          after.
+ *
+ * @param[in] u         pointer to an UART I/O block
+ * @param[in] sdp       communication channel associated to the UART
+ */
+static void serial_serve_interrupt(SerialDriver *sdp) 
+{
+  UART_TypeDef *u = sdp->uart;
+  uint16_t mis = u->MIS;
+  
+  u->ICR = mis;		/* clear interrupts */
+
+  if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) {
+    set_error(sdp, mis);
+  }
+
+  if ((mis & TIVA_MIS_RXMIS) || (mis &  TIVA_MIS_RTMIS)) {
+    osalSysLockFromISR();
+    if (iqIsEmptyI(&sdp->iqueue)) {
+      chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+    }
+    osalSysUnlockFromISR();
+    while ((u->FR & TIVA_FR_RXFE) == 0) {
+      osalSysLockFromISR();
+      if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) {
+        chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+      }
+      osalSysUnlockFromISR();
+    }
+  }
+
+  if (mis & TIVA_MIS_TXMIS) {
+    while ((u->FR & TIVA_FR_TXFF) == 0) {
+      msg_t b;
+      osalSysLockFromISR();
+      b = oqGetI(&sdp->oqueue);
+      osalSysUnlockFromISR();
+      if (b < Q_OK) {
+        u->IM &= ~TIVA_IM_TXIM;
+        osalSysLockFromISR();
+        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+        osalSysUnlockFromISR();
+        break;
+      }
+      u->DR = b;
+    }
+  }
+}
+
+/**
+ * @brief
+ */
+static void fifo_load(SerialDriver *sdp)
+{
+  UART_TypeDef *u = sdp->uart;
+
+  while ((u->FR & TIVA_FR_TXFF) == 0) {
+    msg_t b = oqGetI(&sdp->oqueue);
+    if (b < Q_OK) {
+      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+      return;
+    }
+    u->DR = b;
+  }
+  u->IM |= TIVA_IM_TXIM;   /* transmit interrupt enable */
+}
+
+/**
+ * @brief   Driver SD1 output notification.
+ */
+#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD1);
+}
+#endif
+
+/**
+ * @brief   Driver SD2 output notification.
+ */
+#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD2);
+}
+#endif
+
+/**
+ * @brief   Driver SD3 output notification.
+ */
+#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD3);
+}
+#endif
+
+/**
+ * @brief   Driver SD4 output notification.
+ */
+#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+static void notify4(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD4);
+}
+#endif
+
+/**
+ * @brief   Driver SD5 output notification.
+ */
+#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+static void notify5(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD5);
+}
+#endif
+
+/**
+ * @brief   Driver SD6 output notification.
+ */
+#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+static void notify6(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD6);
+}
+#endif
+
+/**
+ * @brief   Driver SD7 output notification.
+ */
+#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
+static void notify7(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD7);
+}
+#endif
+
+/**
+ * @brief   Driver SD8 output notification.
+ */
+#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+static void notify8(io_queue_t *qp)
+{
+  (void)qp;
+  fifo_load(&SD8);
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   UART0 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART0_HANDLER)
+#error "TIVA_UART0_HANDLER not defined"
+#endif
+CH_IRQ_HANDLER(TIVA_UART0_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD1);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART1 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART1_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD2);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART2 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART2_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD3);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART3 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART3_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD4);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART4 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART4_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD5);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART5 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART5_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD6);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART6 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART6_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD7);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief   UART7 IRQ handler.
+ */
+#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(TIVA_UART7_HANDLER)
+{
+  CH_IRQ_PROLOGUE();
+
+  serial_serve_interrupt(&SD8);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level serial driver initialization.
+ */
+void sd_lld_init(void)
+{
+#if TIVA_SERIAL_USE_UART0
+  sdObjectInit(&SD1, NULL, notify1);
+  SD1.uart = UART0;
+#endif
+
+#if TIVA_SERIAL_USE_UART1
+  sdObjectInit(&SD2, NULL, notify2);
+  SD2.uart = UART1;
+#endif
+
+#if TIVA_SERIAL_USE_UART2
+  sdObjectInit(&SD3, NULL, notify3);
+  SD3.uart = UART2;
+#endif
+
+#if TIVA_SERIAL_USE_UART3
+  sdObjectInit(&SD4, NULL, notify4);
+  SD4.uart = UART3;
+#endif
+
+#if TIVA_SERIAL_USE_UART4
+  sdObjectInit(&SD5, NULL, notify5);
+  SD5.uart = UART4;
+#endif
+
+#if TIVA_SERIAL_USE_UART5
+  sdObjectInit(&SD6, NULL, notify6);
+  SD6.uart = UART5;
+#endif
+
+#if TIVA_SERIAL_USE_UART6
+  sdObjectInit(&SD7, NULL, notify7);
+  SD7.uart = UART6;
+#endif
+
+#if TIVA_SERIAL_USE_UART7
+  sdObjectInit(&SD8, NULL, notify8);
+  SD8.uart = UART7;
+#endif
+}
+
+/**
+ * @brief   Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration.
+ *                      If this parameter is set to @p NULL then a default
+ *                      configuration is used.
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config)
+{
+  if (config == NULL)
+    config = &sd_default_config;
+
+  if (sdp->state == SD_STOP) {
+#if TIVA_SERIAL_USE_UART0
+    if (&SD1 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 0);
+      nvicEnableVector(UART0_IRQn, TIVA_SERIAL_UART0_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART1
+    if (&SD2 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 1);
+      nvicEnableVector(UART1_IRQn, TIVA_SERIAL_UART1_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART2
+    if (&SD3 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 2);  /* enable UART2 module */
+      nvicEnableVector(UART2_IRQn, TIVA_SERIAL_UART2_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART3
+    if (&SD4 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 3);  /* enable UART3 module */
+      nvicEnableVector(UART3_IRQn, TIVA_SERIAL_UART3_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART4
+    if (&SD5 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 4);  /* enable UART4 module */
+      nvicEnableVector(UART4_IRQn, TIVA_SERIAL_UART4_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART5
+    if (&SD6 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 5);  /* enable UART5 module */
+      nvicEnableVector(UART5_IRQn, TIVA_SERIAL_UART5_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART6
+    if (&SD7 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 6);  /* enable UART6 module */
+      nvicEnableVector(UART6_IRQn, TIVA_SERIAL_UART6_PRIORITY);
+    }
+#endif
+#if TIVA_SERIAL_USE_UART7
+    if (&SD8 == sdp) {
+      SYSCTL->RCGCUART |= (1 << 7);  /* enable UART7 module */
+      nvicEnableVector(UART7_IRQn, TIVA_SERIAL_UART7_PRIORITY);
+    }
+#endif
+  }
+  uart_init(sdp, config);
+}
+
+/**
+ * @brief   Low level serial driver stop.
+ * @details De-initializes the UART, stops the associated clock, resets the
+ *          interrupt vector.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ */
+void sd_lld_stop(SerialDriver *sdp)
+{
+  if (sdp->state == SD_READY) {
+    uart_deinit(sdp->uart);
+#if TIVA_SERIAL_USE_UART0
+    if (&SD1 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 0);  /* disable UART0 module */
+      nvicDisableVector(UART0_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART1
+    if (&SD2 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 1);  /* disable UART1 module */
+      nvicDisableVector(UART1_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART2
+    if (&SD3 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 2);  /* disable UART2 module */
+      nvicDisableVector(UART2_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART3
+    if (&SD4 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 3);  /* disable UART3 module */
+      nvicDisableVector(UART3_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART4
+    if (&SD5 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 4);  /* disable UART4 module */
+      nvicDisableVector(UART4_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART5
+    if (&SD6 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 5);  /* disable UART5 module */
+      nvicDisableVector(UART5_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART6
+    if (&SD7 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 6);  /* disable UART6 module */
+      nvicDisableVector(UART6_IRQn);
+      return;
+    }
+#endif
+#if TIVA_SERIAL_USE_UART7
+    if (&SD8 == sdp) {
+      SYSCTL->RCGCUART &= ~(1 << 7);  /* disable UART7 module */
+      nvicDisableVector(UART7_IRQn);
+      return;
+    }
+#endif
+  }
+}
+
+#endif /* CH_HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/serial_lld.h b/os/hal/ports/TIVA/LLD/serial_lld.h
new file mode 100644
index 0000000..5ba4645
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/serial_lld.h
@@ -0,0 +1,482 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/LLD/serial_lld.h
+ * @brief   Tiva low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    FR register bits definitions
+ * @{
+ */
+
+#define TIVA_FR_CTS         (1 << 0)
+
+#define TIVA_FR_BUSY        (1 << 3)
+
+#define TIVA_FR_RXFE        (1 << 4)
+
+#define TIVA_FR_TXFF        (1 << 5)
+
+#define TIVA_FR_RXFF        (1 << 6)
+
+#define TIVA_FR_TXFE        (1 << 7)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    LCRH register bits definitions
+ * @{
+ */
+
+#define TIVA_LCRH_BRK       (1 << 0)
+
+#define TIVA_LCRH_PEN       (1 << 1)
+
+#define TIVA_LCRH_EPS       (1 << 2)
+
+#define TIVA_LCRH_STP2      (1 << 3)
+
+#define TIVA_LCRH_FEN       (1 << 4)
+
+#define TIVA_LCRH_WLEN_MASK (3 << 5)
+#define TIVA_LCRH_WLEN_5    (0 << 5)
+#define TIVA_LCRH_WLEN_6    (1 << 5)
+#define TIVA_LCRH_WLEN_7    (2 << 5)
+#define TIVA_LCRH_WLEN_8    (3 << 5)
+
+#define TIVA_LCRH_SPS       (1 << 7)
+
+/**
+ * @}
+ */
+ 
+/**
+ * @name    CTL register bits definitions
+ * @{
+ */
+
+#define TIVA_CTL_UARTEN     (1 << 0)
+
+#define TIVA_CTL_SIREN      (1 << 1)
+
+#define TIVA_CTL_SIRLP      (1 << 2)
+
+#define TIVA_CTL_SMART      (1 << 3)
+
+#define TIVA_CTL_EOT        (1 << 4)
+
+#define TIVA_CTL_HSE        (1 << 5)
+
+#define TIVA_CTL_LBE        (1 << 7)
+
+#define TIVA_CTL_TXE        (1 << 8)
+
+#define TIVA_CTL_RXE        (1 << 9)
+
+#define TIVA_CTL_RTS        (1 << 11)
+
+#define TIVA_CTL_RTSEN      (1 << 14)
+
+#define TIVA_CTL_CTSEN      (1 << 15)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    IFLS register bits definitions
+ * @{
+ */
+
+#define TIVA_IFLS_TXIFLSEL_MASK     (7 << 0)
+#define TIVA_IFLS_TXIFLSEL_1_8_F    (0 << 0)
+#define TIVA_IFLS_TXIFLSEL_1_4_F    (1 << 0)
+#define TIVA_IFLS_TXIFLSEL_1_2_F    (2 << 0)
+#define TIVA_IFLS_TXIFLSEL_3_4_F    (3 << 0)
+#define TIVA_IFLS_TXIFLSEL_7_8_F    (4 << 0)
+
+#define TIVA_IFLS_RXIFLSEL_MASK     (7 << 3)
+#define TIVA_IFLS_RXIFLSEL_7_8_E    (0 << 3)
+#define TIVA_IFLS_RXIFLSEL_3_4_E    (1 << 3)
+#define TIVA_IFLS_RXIFLSEL_1_2_E    (2 << 3)
+#define TIVA_IFLS_RXIFLSEL_1_4_E    (3 << 3)
+#define TIVA_IFLS_RXIFLSEL_1_8_E    (4 << 3)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    MIS register bits definitions
+ * @{
+ */
+
+#define TIVA_MIS_CTSMIS             (1 << 1)
+
+#define TIVA_MIS_RXMIS              (1 << 4)
+
+#define TIVA_MIS_TXMIS              (1 << 5)
+
+#define TIVA_MIS_RTMIS              (1 << 6)
+
+#define TIVA_MIS_FEMIS              (1 << 7)
+
+#define TIVA_MIS_PEMIS              (1 << 8)
+
+#define TIVA_MIS_BEMIS              (1 << 9)
+
+#define TIVA_MIS_OEMIS              (1 << 10)
+
+#define TIVA_MIS_9BITMIS            (1 << 12)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    IM register bits definitions
+ * @{
+ */
+
+#define TIVA_IM_CTSIM               (1 << 1)
+
+#define TIVA_IM_RXIM                (1 << 4)
+
+#define TIVA_IM_TXIM                (1 << 5)
+
+#define TIVA_IM_RTIM                (1 << 6)
+
+#define TIVA_IM_FEIM                (1 << 7)
+
+#define TIVA_IM_PEIM                (1 << 8)
+
+#define TIVA_IM_BEIM                (1 << 9)
+
+#define TIVA_IM_OEIM                (1 << 10)
+
+#define TIVA_IM_9BITIM              (1 << 12)
+
+/**
+ * @}
+ */
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+/**
+ * @brief   UART0 driver enable switch.
+ * @details If set to @p TRUE the support for UART0 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(TIVA_SERIAL_USE_UART0) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART0           FALSE
+#endif
+
+/**
+ * @brief   UART1 driver enable switch.
+ * @details If set to @p TRUE the support for UART1 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART1) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART1           FALSE
+#endif
+
+/**
+ * @brief   UART2 driver enable switch.
+ * @details If set to @p TRUE the support for UART2 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART2) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART2           FALSE
+#endif
+
+/**
+ * @brief   UART3 driver enable switch.
+ * @details If set to @p TRUE the support for UART3 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART3           FALSE
+#endif
+
+/**
+ * @brief   UART4 driver enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART4           FALSE
+#endif
+
+/**
+ * @brief   UART5 driver enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART5           FALSE
+#endif
+
+/**
+ * @brief   UART6 driver enable switch.
+ * @details If set to @p TRUE the support for UART6 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART6) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART6           FALSE
+#endif
+
+/**
+ * @brief   UART7 driver enable switch.
+ * @details If set to @p TRUE the support for UART7 is included.
+ * @note    The default is @p FALSE .
+ */
+#if !defined(TIVA_SERIAL_USE_UART7) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_USE_UART7           FALSE
+#endif
+
+/**
+ * @brief   UART0 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART0_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART1 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART1_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART2 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART2_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART3_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART4_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART5_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART6 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART6_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART6_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART7 interrupt priority level setting.
+ */
+#if !defined(TIVA_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_SERIAL_UART7_PRIORITY      5
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !TIVA_SERIAL_USE_UART0 && !TIVA_SERIAL_USE_UART1 && \
+    !TIVA_SERIAL_USE_UART2 && !TIVA_SERIAL_USE_UART3 && \
+	!TIVA_SERIAL_USE_UART4 && !TIVA_SERIAL_USE_UART5 && \
+    !TIVA_SERIAL_USE_UART6 && !TIVA_SERIAL_USE_UART7
+#error "SERIAL driver activated but no UART peripheral assigned"
+#endif
+
+#if TIVA_SERIAL_USE_UART0 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART0_PRIORITY)
+#error "Invalid IRQ priority assigned to UART0"
+#endif
+
+#if TIVA_SERIAL_USE_UART1 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART1_PRIORITY)
+#error "Invalid IRQ priority assigned to UART1"
+#endif
+
+#if TIVA_SERIAL_USE_UART2 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART2_PRIORITY)
+#error "Invalid IRQ priority assigned to UART2"
+#endif
+
+#if TIVA_SERIAL_USE_UART3 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART3_PRIORITY)
+#error "Invalid IRQ priority assigned to UART3"
+#endif
+
+#if TIVA_SERIAL_USE_UART4 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART4_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if TIVA_SERIAL_USE_UART5 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART5_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if TIVA_SERIAL_USE_UART6 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART6_PRIORITY)
+#error "Invalid IRQ priority assigned to UART6"
+#endif
+
+#if TIVA_SERIAL_USE_UART7 && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_SERIAL_UART7_PRIORITY)
+#error "Invalid IRQ priority assigned to UART7"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Tiva Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ *          in order to configure and start a serial driver operations.
+ */
+typedef struct {
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  sc_speed;
+  /* End of the mandatory fields. */
+  /**
+   * @brief Initialization value for the LCRH (Line Control) register.
+   */
+  uint32_t                  sc_lcrh;
+  /**
+   * @brief Initialization value for the IFLS (Interrupt FIFO Level Select)
+   * register.
+   */
+  uint32_t                  sc_ifls;
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data                                                 \
+  _base_asynchronous_channel_data                                           \
+  /* Driver state.*/                                                        \
+  sdstate_t                 state;                                          \
+  /* Input queue.*/                                                         \
+  input_queue_t             iqueue;                                         \
+  /* Output queue.*/                                                        \
+  output_queue_t            oqueue;                                         \
+  /* Input circular buffer.*/                                               \
+  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
+  /* Output circular buffer.*/                                              \
+  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
+  /* End of the mandatory fields.*/                                         \
+  /* Pointer to the USART registers block.*/                                \
+  UART_TypeDef              *uart;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#if TIVA_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#if TIVA_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+
+#if TIVA_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+
+#if TIVA_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+
+#if TIVA_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
+#if TIVA_SERIAL_USE_UART6 && !defined(__DOXYGEN__)
+extern SerialDriver SD7;
+#endif
+
+#if TIVA_SERIAL_USE_UART7 && !defined(__DOXYGEN__)
+extern SerialDriver SD8;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sd_lld_init(void);
+  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+  void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/st_lld.c b/os/hal/ports/TIVA/LLD/st_lld.c
new file mode 100644
index 0000000..6e83c10
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/st_lld.c
@@ -0,0 +1,284 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    Tiva/LLD/st_lld.c
+ * @brief   ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+
+#if (TIVA_ST_USE_WIDE_TIMER == TRUE)
+
+#if TIVA_ST_TIMER_NUMBER == 0
+#warning "WGPT0"
+#define ST_HANDLER                          TIVA_WGPT0A_HANDLER
+#define ST_NUMBER                           TIVA_WGPT0A_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 0))
+
+#elif TIVA_ST_TIMER_NUMBER == 1
+#warning "WGPT1"
+#define ST_HANDLER                          TIVA_WGPT1A_HANDLER
+#define ST_NUMBER                           TIVA_WGPT1A_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 1))
+
+#elif TIVA_ST_TIMER_NUMBER == 2
+#warning "WGPT2"
+#define ST_HANDLER                          TIVA_WGPT2A_HANDLER
+#define ST_NUMBER                           TIVA_WGPT2A_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 2))
+
+#elif TIVA_ST_TIMER_NUMBER == 3
+#warning "WGPT3"
+#define ST_HANDLER                          TIVA_WGPT3A_HANDLER
+#define ST_NUMBER                           TIVA_WGPT3A_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 3))
+
+#elif TIVA_ST_TIMER_NUMBER == 4
+#warning "WGPT4"
+#define ST_HANDLER                          TIVA_WGPT4A_HANDLER
+#define ST_NUMBER                           TIVA_WGPT4A_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 4))
+
+#elif TIVA_ST_TIMER_NUMBER == 5
+#warning "WGPT5"
+#define ST_HANDLER                          TIVA_WGPT5A_HANDLER
+#define ST_NUMBER                           TIVA_WGPT5A_NUMBER
+//#define ST_CLOCK_SRC                        (80000000)
+#define ST_CLOCK_SRC                        (16000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 5))
+
+#else
+#error "TIVA_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
+#error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
+#endif
+
+#elif (TIVA_ST_USE_WIDE_TIMER == FALSE)
+
+#if TIVA_ST_TIMER_NUMBER == 0
+#warning "GPT0"
+#define ST_HANDLER                          TIVA_GPT0_HANDLER
+#define ST_NUMBER                           TIVA_GPT0_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 0))
+
+#elif TIVA_ST_TIMER_NUMBER == 1
+#warning "GPT1"
+#define ST_HANDLER                          TIVA_GPT1_HANDLER
+#define ST_NUMBER                           TIVA_GPT1_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 1))
+
+#elif TIVA_ST_TIMER_NUMBER == 2
+#warning "GPT2"
+#define ST_HANDLER                          TIVA_GPT2_HANDLER
+#define ST_NUMBER                           TIVA_GPT2_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 2))
+
+#elif TIVA_ST_TIMER_NUMBER == 3
+#warning "GPT3"
+#define ST_HANDLER                          TIVA_GPT3_HANDLER
+#define ST_NUMBER                           TIVA_GPT3_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 3))
+
+#elif TIVA_ST_TIMER_NUMBER == 4
+#warning "GPT4"
+#define ST_HANDLER                          TIVA_GPT4_HANDLER
+#define ST_NUMBER                           TIVA_GPT4_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 4))
+
+#elif TIVA_ST_TIMER_NUMBER == 5
+#warning "GPT5"
+#define ST_HANDLER                          TIVA_GPT5_HANDLER
+#define ST_NUMBER                           TIVA_GPT5_NUMBER
+#define ST_CLOCK_SRC                        (80000000)
+#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 5))
+
+#else
+#error "TIVA_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFF
+#error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
+#endif
+
+#endif
+
+#if ST_CLOCK_SRC % OSAL_ST_FREQUENCY != 0
+#error "the selected ST frequency is not obtainable because integer rounding"
+#endif
+
+#endif
+
+//#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
+//#error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
+//#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types.                                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief   System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  osalSysLockFromISR();
+  osalOsTimerHandlerI();
+  osalSysUnlockFromISR();
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)
+/**
+ * @brief   TIM2 interrupt handler.
+ * @details This interrupt is used for system tick in free running mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(ST_HANDLER)
+{
+  uint32_t mis;
+  uint32_t temp;
+
+  OSAL_IRQ_PROLOGUE();
+
+  mis = TIVA_ST_TIM->MIS;
+  TIVA_ST_TIM->ICR = 0xffffffff;
+
+  if (mis & GPTM_IMR_TATOIM) {
+    temp = 3;
+  }
+
+  if (mis & GPTM_IMR_CAMIM) {
+    temp = 1;
+  }
+
+  if (mis & GPTM_IMR_CAEIM) {
+    temp = 2;
+  }
+
+  if (mis & GPTM_IMR_TAMIM) {
+    osalSysLockFromISR();
+    osalOsTimerHandlerI();
+    osalSysUnlockFromISR();
+  }
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  /* Free running counter mode.*/
+
+  /* Enabling timer clock.*/
+  ST_ENABLE_CLOCK();
+
+  /* Initializing the counter in free running mode.*/
+  TIVA_ST_TIM->CTL  = 0;
+  TIVA_ST_TIM->CFG  = GPTM_CFG_CFG_SPLIT;           /* Timer split mode */
+  TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |    /* Periodic mode */
+                        GPTM_TAMR_TACDIR |          /* Count up */
+                        GPTM_TAMR_TAMIE |           /* Match interrupt enable */
+                        GPTM_TAMR_TASNAPS);         /* Snapshot mode */
+  //TIVA_ST_TIM->TAPR = (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1;
+  /* in up mode (used by tickless mode) the prescaler register extends the TAV
+   * and TAR registers. How to solve this? In down mode it is working better
+   * because the prescaler really works as prescaler. */
+  //TIVA_ST_TIM->CTL  = (GPTM_CTL_TAEN | GPTM_CTL_TASTALL);
+  TIVA_ST_TIM->CTL  = (GPTM_CTL_TAEN |              /* Timer A enable */
+                        GPTM_CTL_TASTALL);          /* Timer A stall when paused */
+
+  /* IRQ enabled.*/
+  nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+  /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+     in this mode.*/
+  SysTick->LOAD = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1;
+  SysTick->VAL = 0;
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+                  SysTick_CTRL_ENABLE_Msk |
+                  SysTick_CTRL_TICKINT_Msk;
+
+  /* IRQ enabled.*/
+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, TIVA_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/st_lld.h b/os/hal/ports/TIVA/LLD/st_lld.h
new file mode 100644
index 0000000..49bd91d
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/st_lld.h
@@ -0,0 +1,323 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    Tiva/LLD/st_lld.h
+ * @brief   ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ *          include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef _ST_LLD_H_
+#define _ST_LLD_H_
+
+#include "mcuconf.h"
+#include "tiva_registry.h"
+#include "tiva_gpt.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define TIVA_ST_TIM_PRESCALER       ((80000000 / 10000) - 1)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+/**
+ * @brief   SysTick timer IRQ priority.
+ */
+#if !defined(TIVA_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_ST_IRQ_PRIORITY                2
+#endif
+
+/**
+ * @brief   GPTx unit (by number) to be used for free running operations.
+ * @note    You must select a 32 bits timer if a 32 bits @p systick_t type
+ *          is required.
+ */
+#if !defined(TIVA_ST_TIMER_NUMBER) || defined(__DOXYGEN__)
+#define TIVA_ST_TIMER_NUMBER                0
+#endif
+
+/* TODO: Add description */
+#if !defined(TIVA_ST_USE_WIDE_TIMER) || defined(__DOXYGEN__)
+#define TIVA_ST_USE_WIDE_TIMER              TRUE
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+
+#error "Tickless system tick mode is not working yet! Please use the periodic system tick mode."
+
+#if (TIVA_ST_USE_WIDE_TIMER == TRUE)
+
+#if TIVA_ST_TIMER_NUMBER == 0
+#if !TIVA_HAS_WGPT0
+#error "WGPT0 not present"
+#endif
+#define TIVA_ST_TIM                         WGPT0
+
+#elif TIVA_ST_TIMER_NUMBER == 1
+#if !TIVA_HAS_WGPT1
+#error "WGPT1 not present"
+#endif
+#define TIVA_ST_TIM                         WGPT1
+
+#elif TIVA_ST_TIMER_NUMBER == 2
+#if !TIVA_HAS_WGPT2
+#error "WGPT2 not present"
+#endif
+#define TIVA_ST_TIM                         WGPT2
+
+#elif TIVA_ST_TIMER_NUMBER == 3
+#if !TIVA_HAS_WGPT3
+#error "WGPT3 not present"
+#endif
+#define TIVA_ST_TIM                         WGPT3
+
+#elif TIVA_ST_TIMER_NUMBER == 4
+#if !TIVA_HAS_WGPT4
+#error "WGPT4 not present"
+#endif
+#define TIVA_ST_TIM                         WGPT4
+
+#elif TIVA_ST_TIMER_NUMBER == 5
+#if !TIVA_HAS_WGPT5
+#error "WGPT5 not present"
+#endif
+#define TIVA_ST_TIM                         WGPT5
+
+#else
+#error "TIVA_ST_USE_TIMER specifies an unsupported timer"
+#endif
+
+#elif (TIVA_ST_USE_WIDE_TIMER == FALSE)
+
+#if TIVA_ST_TIMER_NUMBER == 0
+#if !TIVA_HAS_GPT0
+#error "GPT0 not present"
+#endif
+#define TIVA_ST_TIM                         GPT0
+
+#elif TIVA_ST_TIMER_NUMBER == 1
+#if !TIVA_HAS_GPT1
+#error "GPT1 not present"
+#endif
+#define TIVA_ST_TIM                         GPT1
+
+#elif TIVA_ST_TIMER_NUMBER == 2
+#if !TIVA_HAS_GPT2
+#error "GPT2 not present"
+#endif
+#define TIVA_ST_TIM                         GPT2
+
+#elif TIVA_ST_TIMER_NUMBER == 3
+#if !TIVA_HAS_GPT3
+#error "GPT3 not present"
+#endif
+#define TIVA_ST_TIM                         GPT3
+
+#elif TIVA_ST_TIMER_NUMBER == 4
+#if !TIVA_HAS_GPT4
+#error "GPT4 not present"
+#endif
+#define TIVA_ST_TIM                         GPT4
+
+#elif TIVA_ST_TIMER_NUMBER == 5
+#if !TIVA_HAS_GPT5
+#error "GPT5 not present"
+#endif
+#define TIVA_ST_TIM                         GPT5
+
+#else
+#error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer"
+#endif
+
+#else
+#error "wrong value defined for TIVA_ST_USE_WIDE_TIMER"
+#endif
+
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions.                                                  */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the time counter value.
+ *
+ * @return              The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  return (systime_t) TIVA_ST_TIM->TAV;
+#else
+  return (systime_t) 0;
+#endif
+}
+
+/**
+ * @brief   Starts the alarm.
+ * @note    Makes sure that no spurious alarms are triggered after
+ *          this call.
+ *
+ * @param[in] time      the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  uint64_t temp;
+
+  temp = (uint64_t) time * TIVA_ST_TIM_PRESCALER;
+
+  TIVA_ST_TIM->TAMATCHR = (uint32_t) temp;
+
+  temp = temp >> 32;
+
+  TIVA_ST_TIM->TAPMR = (uint16_t) temp;
+
+  TIVA_ST_TIM->ICR = 0xffffffff;
+  TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM;
+#else
+  (void)time;
+#endif
+}
+
+/**
+ * @brief   Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  TIVA_ST_TIM->IMR = 0;
+#endif
+}
+
+/**
+ * @brief   Sets the alarm time.
+ *
+ * @param[in] time      the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  uint64_t temp;
+
+  temp = (uint64_t) time * TIVA_ST_TIM_PRESCALER;
+
+  TIVA_ST_TIM->TAMATCHR = (uint32_t) temp;
+
+  temp = temp >> 32;
+
+  TIVA_ST_TIM->TAPMR = (uint16_t) temp;
+#else
+  (void)time;
+#endif
+}
+
+/**
+ * @brief   Returns the current alarm time.
+ *
+ * @return              The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  uint64_t temp;
+
+  temp = TIVA_ST_TIM->TAPR;
+  temp = temp << 32;
+  temp = TIVA_ST_TIM->TAR;
+
+  temp = temp / TIVA_ST_TIM_PRESCALER;
+
+  return (systime_t) temp;
+#else
+  return (systime_t) 0;
+#endif
+}
+
+/**
+ * @brief   Determines if the alarm is active.
+ *
+ * @return              The alarm status.
+ * @retval false        if the alarm is not active.
+ * @retval true         is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void)
+{
+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING
+  return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0);
+#else
+  return (bool) false;
+#endif
+}
+
+#endif /* _ST_LLD_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h
new file mode 100644
index 0000000..0644724
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/tiva_gpt.h
@@ -0,0 +1,135 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    tiva_gpt.h
+ * @brief   TIVA GPT registers layout header.
+ *
+ * @addtogroup TIVA_GPT
+ * @{
+ */
+
+#ifndef TIVA_GPT_H_
+#define TIVA_GPT_H_
+
+// cfg
+#define GPTM_CFG_CFG_MASK       (7 << 0)
+#define GPTM_CFG_CFG_WHOLE      (0 << 0)
+#define GPTM_CFG_CFG_RTC        (1 << 0)
+#define GPTM_CFG_CFG_SPLIT      (4 << 0)
+
+// tamr
+#define GPTM_TAMR_TAMR_MASK     (3 << 0)
+#define GPTM_TAMR_TAMR_ONESHOT  (1 << 0)
+#define GPTM_TAMR_TAMR_PERIODIC (2 << 0)
+#define GPTM_TAMR_TAMR_CAPTURE  (3 << 0)
+
+#define GPTM_TAMR_TACMR         (1 << 2)
+
+#define GPTM_TAMR_TAAMS         (1 << 3)
+
+#define GPTM_TAMR_TACDIR        (1 << 4)
+
+#define GPTM_TAMR_TAMIE         (1 << 5)
+
+#define GPTM_TAMR_TAWOT         (1 << 6)
+
+#define GPTM_TAMR_TASNAPS       (1 << 7)
+
+#define GPTM_TAMR_TAILD         (1 << 8)
+
+#define GPTM_TAMR_TAPWMIE       (1 << 9)
+
+#define GPTM_TAMR_TAMRSU        (1 << 10)
+
+#define GPTM_TAMR_TAPLO         (1 << 11)
+
+// ctl
+#define GPTM_CTL_TAEN           (1 << 0)
+
+#define GPTM_CTL_TASTALL        (1 << 1)
+
+#define GPTM_CTL_TAEVENT_MASK   (3 << 2)
+#define GPTM_CTL_TAEVENT_POS    (0 << 2)
+#define GPTM_CTL_TAEVENT_NEG    (1 << 2)
+#define GPTM_CTL_TAEVENT_BOTH   (3 << 2)
+
+#define GPTM_CTL_RTCEN          (1 << 4)
+
+#define GPTM_CTL_TAOTE          (1 << 5)
+
+#define GPTM_CTL_TAPWML         (1 << 6)
+
+#define GPTM_CTL_TBEN           (1 << 8)
+
+#define GPTM_CTL_TBSTALL        (1 << 9)
+
+#define GPTM_CTL_TBEVENT_MASK   (3 << 10)
+#define GPTM_CTL_TBEVENT_POS    (0 << 10)
+#define GPTM_CTL_TBEVENT_NEG    (1 << 10)
+#define GPTM_CTL_TBEVENT_BOTH   (3 << 10)
+
+#define GPTM_CTL_TBOTE          (1 << 13)
+
+#define GPTM_CTL_TBPWML         (1 << 14)
+
+// imr
+#define GPTM_IMR_TATOIM         (1 << 0)
+
+#define GPTM_IMR_CAMIM          (1 << 1)
+
+#define GPTM_IMR_CAEIM          (1 << 2)
+
+#define GPTM_IMR_RTCIM          (1 << 3)
+
+#define GPTM_IMR_TAMIM          (1 << 4)
+
+#define GPTM_IMR_TBTOIM         (1 << 8)
+
+#define GPTM_IMR_CBMIM          (1 << 9)
+
+#define GPTM_IMR_CBEIM          (1 << 10)
+
+#define GPTM_IMR_TBMIM          (1 << 11)
+
+#define GPTM_IMR_WUEIM          (1 << 16)
+
+// icr
+#define GPTM_ICR_TATOCINT         (1 << 0)
+
+#define GPTM_ICR_CAMCINT          (1 << 1)
+
+#define GPTM_ICR_CAECINT          (1 << 2)
+
+#define GPTM_ICR_RTCCINT          (1 << 3)
+
+#define GPTM_ICR_TAMCINT          (1 << 4)
+
+#define GPTM_ICR_TBTOCINT         (1 << 8)
+
+#define GPTM_ICR_CBMCINT          (1 << 9)
+
+#define GPTM_ICR_CBECINT          (1 << 10)
+
+#define GPTM_ICR_TBMCINT          (1 << 11)
+
+#define GPTM_ICR_WUECINT          (1 << 16)
+
+#endif /* TIVA_GPT_H_ */
+
+/*
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c
new file mode 100644
index 0000000..7a6046d
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c
@@ -0,0 +1,138 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/TM4C123x/hal_lld.c
+ * @brief   TM4C123x HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void)
+{
+}
+
+/**
+ * @brief   TM4C123x clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h and 
+ *          @p mcuconf.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void tiva_clock_init(void)
+{
+  uint32_t rcc, rcc2, i;
+
+  /* 1. Bypass the PLL and system clock divider by setting the BYPASS bit and
+   * clearing the USESYSDIV bit in the RCC register, thereby configuring the
+   * microcontroller to run off a "raw" clock source and allowing for the new
+   * PLL configuration to be validated before switching the system clock to the
+   * PLL. */
+  /* read */
+
+  rcc = SYSCTL->RCC;
+  rcc2 = SYSCTL->RCC2;
+  
+  /* modify */
+  rcc |= TIVA_RCC_BYPASS;
+  rcc &= ~TIVA_RCC_USESYSDIV;
+  rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2;
+  
+  /* write */
+  SYSCTL->RCC = rcc;
+  SYSCTL->RCC2 = rcc2;
+
+  /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and
+   * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically
+   * pulls valid PLL configuration data for the appropriate crystal, and
+   * clearing the PWRDN bit powers and enables the PLL and its output. */
+  /* modify */
+  rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS);
+  rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS));
+  rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2);
+  rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400));
+  
+  /* write */
+  SYSCTL->RCC = rcc;
+  SYSCTL->RCC2 = rcc2;
+  for(i = 100000; i; i--);
+
+  /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the
+   * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for
+   * the microcontroller. */
+  /* modify */
+  rcc &= ~TIVA_RCC_SYSDIV_MASK;
+  rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV;
+  rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB);
+  rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB));
+  
+  /* write */
+  SYSCTL->RCC = rcc;
+  SYSCTL->RCC2 = rcc2;
+
+  /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw
+   * Interrupt Status (RIS) register. */
+  while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0);
+
+  /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */
+  rcc &= ~TIVA_RCC_BYPASS;
+  rcc2 &= ~TIVA_RCC2_BYPASS2;
+  rcc |= (TIVA_BYPASS_VALUE << 11);
+  rcc2 |= (TIVA_BYPASS_VALUE << 11);
+  SYSCTL->RCC = rcc;
+  SYSCTL->RCC2 = rcc2;
+
+#if HAL_USE_PWM
+  SYSCTL->RCC |= TIVA_PWM_FIELDS;
+#endif
+}
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
new file mode 100644
index 0000000..d8b856f
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
@@ -0,0 +1,366 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    Tiva/TM4C123x/hal_lld.h
+ * @brief   TM4C123x HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - TODO: add required macros
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "tiva_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+ 
+#define PLATFORM_NAME           "Tiva C Series TM4C123x"
+
+/**
+ * @}
+ */
+
+/**
+ * @name    RCC register bits definitions
+ * @{
+ */
+
+#define TIVA_RCC_MOSCDIS            (0x01 << 0)
+
+#define TIVA_RCC_OSCSRC_MASK        (0x03 << 4)
+#define TIVA_RCC_OSCSRC_MOSC        (0x00 << 4)
+#define TIVA_RCC_OSCSRC_PIOSC       (0x01 << 4)
+#define TIVA_RCC_OSCSRC_PIOSC_4     (0x02 << 4)
+#define TIVA_RCC_OSCSRC_LFIOSC      (0x03 << 4)
+
+#define TIVA_RCC_XTAL_MASK          (0x1f << 6)
+#define TIVA_RCC_XTAL_4000000       (0x06 << 6)
+#define TIVA_RCC_XTAL_4096000       (0x07 << 6)
+#define TIVA_RCC_XTAL_4915200       (0x08 << 6)
+#define TIVA_RCC_XTAL_5000000       (0x09 << 6)
+#define TIVA_RCC_XTAL_5120000       (0x0a << 6)
+#define TIVA_RCC_XTAL_6000000       (0x0b << 6)
+#define TIVA_RCC_XTAL_6144000       (0x0c << 6)
+#define TIVA_RCC_XTAL_7372800       (0x0d << 6)
+#define TIVA_RCC_XTAL_8000000       (0x0e << 6)
+#define TIVA_RCC_XTAL_8192000       (0x0f << 6)
+#define TIVA_RCC_XTAL_10000000      (0x10 << 6)
+#define TIVA_RCC_XTAL_12000000      (0x11 << 6)
+#define TIVA_RCC_XTAL_12288000      (0x12 << 6)
+#define TIVA_RCC_XTAL_13560000      (0x13 << 6)
+#define TIVA_RCC_XTAL_14318180      (0x14 << 6)
+#define TIVA_RCC_XTAL_16000000      (0x15 << 6)
+#define TIVA_RCC_XTAL_16384000      (0x16 << 6)
+#define TIVA_RCC_XTAL_18000000      (0x17 << 6)
+#define TIVA_RCC_XTAL_20000000      (0x18 << 6)
+#define TIVA_RCC_XTAL_24000000      (0x19 << 6)
+#define TIVA_RCC_XTAL_25000000      (0x1a << 6)
+
+#define TIVA_RCC_BYPASS             (1 << 11)
+
+#define TIVA_RCC_PWRDN              (1 << 13)
+
+#define TIVA_RCC_PWMDIV_MASK        (0x07 << 17)
+#define TIVA_RCC_PWMDIV_2           (0x00 << 17)
+#define TIVA_RCC_PWMDIV_4           (0x01 << 17)
+#define TIVA_RCC_PWMDIV_8           (0x02 << 17)
+#define TIVA_RCC_PWMDIV_16          (0x03 << 17)
+#define TIVA_RCC_PWMDIV_32          (0x04 << 17)
+#define TIVA_RCC_PWMDIV_64          (0x07 << 17)
+
+#define TIVA_RCC_USEPWMDIV          (1 << 20)
+
+#define TIVA_RCC_USESYSDIV	        (1 << 22)
+
+#define TIVA_RCC_SYSDIV_MASK	    (0x0f << 23)
+#define TIVA_RCC_SYSDIV_1           (0x00 << 23)
+#define TIVA_RCC_SYSDIV_2           (0x01 << 23)
+#define TIVA_RCC_SYSDIV_3           (0x02 << 23)
+#define TIVA_RCC_SYSDIV_4           (0x03 << 23)
+#define TIVA_RCC_SYSDIV_5           (0x04 << 23)
+#define TIVA_RCC_SYSDIV_6           (0x05 << 23)
+#define TIVA_RCC_SYSDIV_7           (0x06 << 23)
+#define TIVA_RCC_SYSDIV_8           (0x07 << 23)
+#define TIVA_RCC_SYSDIV_9           (0x08 << 23)
+#define TIVA_RCC_SYSDIV_10          (0x09 << 23)
+#define TIVA_RCC_SYSDIV_11          (0x0a << 23)
+#define TIVA_RCC_SYSDIV_12          (0x0b << 23)
+#define TIVA_RCC_SYSDIV_13          (0x0c << 23)
+#define TIVA_RCC_SYSDIV_14          (0x0d << 23)
+#define TIVA_RCC_SYSDIV_15          (0x0e << 23)
+#define TIVA_RCC_SYSDIV_16          (0x0f << 23)
+
+#define TIVA_RCC_ACG		        (1 << 27)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    RCC2 register bits definitions
+ * @{
+ */
+
+#define TIVA_RCC2_OSCSRC2_MASK      (0x07 << 4)
+#define TIVA_RCC2_OSCSRC2_MOSC      (0x00 << 4)
+#define TIVA_RCC2_OSCSRC2_PIOSC     (0x01 << 4)
+#define TIVA_RCC2_OSCSRC2_PIOSC_4   (0x02 << 4)
+#define TIVA_RCC2_OSCSRC2_LFIOSC    (0x03 << 4)
+#define TIVA_RCC2_OSCSRC2_32768     (0x07 << 4)
+
+#define TIVA_RCC2_BYPASS2           (1 << 11)
+
+#define TIVA_RCC2_PWRDN2            (1 << 13)
+
+#define TIVA_RCC2_USBPWRDN          (1 << 14)
+
+#define TIVA_RCC2_SYSDIV2LSB        (1 << 22)
+
+#define TIVA_RCC2_SYSDIV2_MASK      (0x3f << 23)
+
+#define TIVA_RCC2_DIV400            (1 << 30)
+
+#define TIVA_RCC2_USERCC2           (1 << 31)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    RIS register bits definitions
+ * @{
+ */
+
+#define SYSCTL_RIS_PLLLRIS	            (1 << 6)
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+
+#if !defined(TIVA_OSCSRC)
+#define TIVA_OSCSRC                     TIVA_RCC2_OSCSRC2_MOSC
+#endif
+
+#if !defined(TIVA_MOSC_ENABLE)
+#define TIVA_MOSC_ENABLE                TRUE
+#endif
+
+#if !defined(TIVA_DIV400_VALUE)
+#define TIVA_DIV400_VALUE               1
+#endif
+
+#if !defined(TIVA_SYSDIV_VALUE)
+#define TIVA_SYSDIV_VALUE               2
+#endif
+
+#if !defined(TIVA_USESYSDIV_ENABLE)
+#define TIVA_USESYSDIV_ENABLE           FALSE
+#endif
+
+#if !defined(TIVA_SYSDIV2LSB_ENABLE)
+#define TIVA_SYSDIV2LSB_ENABLE          FALSE
+#endif
+
+#if !defined(TIVA_BYPASS_VALUE)
+#define TIVA_BYPASS_VALUE               0
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(TM4C123x_MCUCONF)
+#error "Using a wrong mcuconf.h file, TM4C123x_MCUCONF not defined"
+#endif
+
+/*
+ * Oscillator-related checks.
+ */
+#if !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_MOSC) &&                                 \
+    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC) &&                                \
+    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC_4) &&                              \
+    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_LFIOSC) &&                               \
+    !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_32768)
+#error "Invalid value for TIVA_OSCSRC defined"
+#endif
+
+#if TIVA_XTAL_VALUE == 4000000
+#define TIVA_XTAL_              (0x06 << 6)
+#elif TIVA_XTAL_VALUE == 4096000
+#define TIVA_XTAL_              (0x07 << 6)
+#elif TIVA_XTAL_VALUE == 4915200
+#define TIVA_XTAL_              (0x08 << 6)
+#elif TIVA_XTAL_VALUE == 5000000
+#define TIVA_XTAL_              (0x09 << 6)
+#elif TIVA_XTAL_VALUE == 5120000
+#define TIVA_XTAL_              (0x0a << 6)
+#elif TIVA_XTAL_VALUE == 6000000
+#define TIVA_XTAL_              (0x0b << 6)
+#elif TIVA_XTAL_VALUE == 6144000
+#define TIVA_XTAL_              (0x0c << 6)
+#elif TIVA_XTAL_VALUE == 7372800
+#define TIVA_XTAL_              (0x0d << 6)
+#elif TIVA_XTAL_VALUE == 8000000
+#define TIVA_XTAL_              (0x0e << 6)
+#elif TIVA_XTAL_VALUE == 8192000
+#define TIVA_XTAL_              (0x0f << 6)
+#elif TIVA_XTAL_VALUE == 10000000
+#define TIVA_XTAL_              (0x10 << 6)
+#elif TIVA_XTAL_VALUE == 12000000
+#define TIVA_XTAL_              (0x11 << 6)
+#elif TIVA_XTAL_VALUE == 12288000
+#define TIVA_XTAL_              (0x12 << 6)
+#elif TIVA_XTAL_VALUE == 13560000
+#define TIVA_XTAL_              (0x13 << 6)
+#elif TIVA_XTAL_VALUE == 14318180
+#define TIVA_XTAL_              (0x14 << 6)
+#elif TIVA_XTAL_VALUE == 16000000
+#define TIVA_XTAL_              (0x15 << 6)
+#elif TIVA_XTAL_VALUE == 16384000
+#define TIVA_XTAL_              (0x16 << 6)
+#elif TIVA_XTAL_VALUE == 18000000
+#define TIVA_XTAL_              (0x17 << 6)
+#elif TIVA_XTAL_VALUE == 20000000
+#define TIVA_XTAL_              (0x18 << 6)
+#elif TIVA_XTAL_VALUE == 24000000
+#define TIVA_XTAL_              (0x19 << 6)
+#elif TIVA_XTAL_VALUE == 25000000
+#define TIVA_XTAL_              (0x1a << 6)
+#else
+#error "Invalid value for TIVA_XTAL_VALUE defined"
+#endif
+
+#if TIVA_MOSC_ENABLE == TRUE
+#define TIVA_MOSCDIS            (0 << 0)
+#define TIVA_XTAL               TIVA_XTAL_
+#elif TIVA_MOSC_ENABLE == FALSE
+#define TIVA_MOSCDIS            (1 << 0)
+#define TIVA_XTAL               0
+#else
+#error "Invalid value for TIVA_MOSC_ENABLE defined"
+#endif
+
+#if TIVA_DIV400_VALUE == 1
+#define TIVA_DIV400             (1 << 30)
+#elif TIVA_DIV400_VALUE == 0
+#define TIVA_DIV400             (0 << 30)
+#else
+#error "Invalid value for TIVA_DIV400_VALUE defined"
+#endif
+
+#if (TIVA_SYSDIV_VALUE >= 0x02) && (TIVA_SYSDIV_VALUE <= 0x3f)
+#define TIVA_SYSDIV             (TIVA_SYSDIV_VALUE << 23)
+#define TIVA_SYSDIV2            (TIVA_SYSDIV_VALUE << 23)
+#else
+#error "Invalid value for TIVA_SYSDIV_VALUE defined"
+#endif
+
+#if TIVA_USESYSDIV_ENABLE == TRUE
+#define TIVA_USESYSDIV          (1 << 22)
+#elif TIVA_USESYSDIV_ENABLE == FALSE
+#define TIVA_USESYSDIV          (0 << 22)
+#else
+#error "Invalid value for TIVA_USESYSDIV_ENABLE defined"
+#endif
+
+#if TIVA_SYSDIV2LSB_ENABLE == TRUE
+#define TIVA_SYSDIV2LSB         (1 << 22)
+#elif TIVA_SYSDIV2LSB_ENABLE == FALSE
+#define TIVA_SYSDIV2LSB         (0 << 22)
+#else
+#error "Invalid value for TIVA_SYSDIV2LSB_ENABLE defined"
+#endif
+
+#if TIVA_BYPASS_VALUE == 1
+#define TIVA_SRC                16000000
+#elif TIVA_BYPASS_VALUE == 0
+#define TIVA_SRC                (200000000 + (TIVA_DIV400_VALUE * 200000000))
+#else
+#error "Invalid value for TIVA_BYPASS_VALUE defined"
+#endif
+
+#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE)
+#error "Main Oscillator selected but not enabled"
+#endif
+
+/*
+ * System Clock calculation 
+ */
+#define TIVA_SYSCLK             (TIVA_SRC / (((TIVA_SYSDIV_VALUE << TIVA_DIV400_VALUE /*& TIVA_BYPASS_VALUE*/) | (TIVA_SYSDIV2LSB >> 22)) + 1))
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SysTick"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "tiva_isr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void tiva_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk
new file mode 100644
index 0000000..3051cd3
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C123x/platform.mk
@@ -0,0 +1,14 @@
+# List of all the TM4C123x platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C123x/hal_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/i2c_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/gpt_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pwm_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C123x \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD
diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
new file mode 100644
index 0000000..a7bd264
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h
@@ -0,0 +1,643 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TM4C123x/tiva_isr.h
+ * @brief   TM4C123x ISR remapper driver header.
+ *
+ * @addtogroup TM4C123x_ISR
+ * @{
+ */
+
+#ifndef _TIVA_ISR_H_
+#define _TIVA_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    ISR names and numbers remapping
+ * @{
+ */
+
+/* GPIO units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM)  \
+  || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM)  \
+  || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM)  \
+  || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+#define TIVA_GPIOG_HANDLER                  VectorBC
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#define TIVA_GPIOG_NUMBER                   31
+#endif
+#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
+  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
+  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
+  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#endif
+#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ)   \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ)  \
+  || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ)  \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ)  \
+  || defined(TM4C123GH6PZ)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+#define TIVA_GPIOG_HANDLER                  VectorBC
+#define TIVA_GPIOH_HANDLER                  VectorC0
+#define TIVA_GPIOJ_HANDLER                  Vector118
+#define TIVA_GPIOK_HANDLER                  Vector11C
+#define TIVA_GPIOL_HANDLER                  Vector120
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#define TIVA_GPIOG_NUMBER                   31
+#define TIVA_GPIOH_NUMBER                   32
+#define TIVA_GPIOJ_NUMBER                   54
+#define TIVA_GPIOK_NUMBER                   55
+#define TIVA_GPIOL_NUMBER                   56
+#endif
+#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\
+  || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+#define TIVA_GPIOG_HANDLER                  VectorBC
+#define TIVA_GPIOH_HANDLER                  VectorC0
+#define TIVA_GPIOJ_HANDLER                  Vector118
+#define TIVA_GPIOK_HANDLER                  Vector11C
+#define TIVA_GPIOL_HANDLER                  Vector120
+#define TIVA_GPIOM_HANDLER                  Vector1FC
+#define TIVA_GPION_HANDLER                  Vector200
+#define TIVA_GPIOP0_HANDLER                 Vector210
+#define TIVA_GPIOP1_HANDLER                 Vector214
+#define TIVA_GPIOP2_HANDLER                 Vector218
+#define TIVA_GPIOP3_HANDLER                 Vector21C
+#define TIVA_GPIOP4_HANDLER                 Vector220
+#define TIVA_GPIOP5_HANDLER                 Vector224
+#define TIVA_GPIOP6_HANDLER                 Vector228
+#define TIVA_GPIOP7_HANDLER                 Vector22C
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#define TIVA_GPIOG_NUMBER                   31
+#define TIVA_GPIOH_NUMBER                   32
+#define TIVA_GPIOJ_NUMBER                   54
+#define TIVA_GPIOK_NUMBER                   55
+#define TIVA_GPIOL_NUMBER                   56
+#define TIVA_GPIOM_NUMBER                   111
+#define TIVA_GPION_NUMBER                   112
+#define TIVA_GPIOP0_NUMBER                  116
+#define TIVA_GPIOP1_NUMBER                  117
+#define TIVA_GPIOP2_NUMBER                  118
+#define TIVA_GPIOP3_NUMBER                  119
+#define TIVA_GPIOP4_NUMBER                  120
+#define TIVA_GPIOP5_NUMBER                  121
+#define TIVA_GPIOP6_NUMBER                  122
+#define TIVA_GPIOP7_NUMBER                  123
+#endif
+#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+#define TIVA_GPIOG_HANDLER                  VectorBC
+#define TIVA_GPIOH_HANDLER                  VectorC0
+#define TIVA_GPIOJ_HANDLER                  Vector118
+#define TIVA_GPIOK_HANDLER                  Vector11C
+#define TIVA_GPIOL_HANDLER                  Vector120
+#define TIVA_GPIOM_HANDLER                  Vector1FC
+#define TIVA_GPION_HANDLER                  Vector200
+#define TIVA_GPIOP0_HANDLER                 Vector210
+#define TIVA_GPIOP1_HANDLER                 Vector214
+#define TIVA_GPIOP2_HANDLER                 Vector218
+#define TIVA_GPIOP3_HANDLER                 Vector21C
+#define TIVA_GPIOP4_HANDLER                 Vector220
+#define TIVA_GPIOP5_HANDLER                 Vector224
+#define TIVA_GPIOP6_HANDLER                 Vector228
+#define TIVA_GPIOP7_HANDLER                 Vector22C
+#define TIVA_GPIOQ0_HANDLER                 Vector230
+#define TIVA_GPIOQ1_HANDLER                 Vector234
+#define TIVA_GPIOQ2_HANDLER                 Vector238
+#define TIVA_GPIOQ3_HANDLER                 Vector23C
+#define TIVA_GPIOQ4_HANDLER                 Vector240
+#define TIVA_GPIOQ5_HANDLER                 Vector244
+#define TIVA_GPIOQ6_HANDLER                 Vector248
+#define TIVA_GPIOQ7_HANDLER                 Vector24C
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#define TIVA_GPIOG_NUMBER                   31
+#define TIVA_GPIOH_NUMBER                   32
+#define TIVA_GPIOJ_NUMBER                   54
+#define TIVA_GPIOK_NUMBER                   55
+#define TIVA_GPIOL_NUMBER                   56
+#define TIVA_GPIOM_NUMBER                   111
+#define TIVA_GPION_NUMBER                   112
+#define TIVA_GPIOP0_NUMBER                  116
+#define TIVA_GPIOP1_NUMBER                  117
+#define TIVA_GPIOP2_NUMBER                  118
+#define TIVA_GPIOP3_NUMBER                  119
+#define TIVA_GPIOP4_NUMBER                  120
+#define TIVA_GPIOP5_NUMBER                  121
+#define TIVA_GPIOP6_NUMBER                  122
+#define TIVA_GPIOP7_NUMBER                  123
+#define TIVA_GPIOQ0_NUMBER                  124
+#define TIVA_GPIOQ1_NUMBER                  125
+#define TIVA_GPIOQ2_NUMBER                  126
+#define TIVA_GPIOQ3_NUMBER                  127
+#define TIVA_GPIOQ4_NUMBER                  128
+#define TIVA_GPIOQ5_NUMBER                  129
+#define TIVA_GPIOQ6_NUMBER                  130
+#define TIVA_GPIOQ7_NUMBER                  131
+#endif
+
+/* GPTM units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_GPT0A_HANDLER                   Vector8C
+#define TIVA_GPT0B_HANDLER                   Vector90
+#define TIVA_GPT1A_HANDLER                   Vector94
+#define TIVA_GPT1B_HANDLER                   Vector98
+#define TIVA_GPT2A_HANDLER                   Vector9C
+#define TIVA_GPT2B_HANDLER                   VectorA0
+#define TIVA_GPT3A_HANDLER                   VectorCC
+#define TIVA_GPT3B_HANDLER                   VectorD0
+#define TIVA_GPT4A_HANDLER                   Vector158
+#define TIVA_GPT4B_HANDLER                   Vector15C
+#define TIVA_GPT5A_HANDLER                   Vector1B0
+#define TIVA_GPT5B_HANDLER                   Vector1B4
+
+#define TIVA_GPT0A_NUMBER                    19
+#define TIVA_GPT0B_NUMBER                    20
+#define TIVA_GPT1A_NUMBER                    21
+#define TIVA_GPT1B_NUMBER                    22
+#define TIVA_GPT2A_NUMBER                    23
+#define TIVA_GPT2B_NUMBER                    24
+#define TIVA_GPT3A_NUMBER                    35
+#define TIVA_GPT3B_NUMBER                    36
+#define TIVA_GPT4A_NUMBER                    70
+#define TIVA_GPT4B_NUMBER                    71
+#define TIVA_GPT5A_NUMBER                    92
+#define TIVA_GPT5B_NUMBER                    93
+
+#define TIVA_WGPT0A_HANDLER                  Vector1B8
+#define TIVA_WGPT0B_HANDLER                  Vector1BC
+#define TIVA_WGPT1A_HANDLER                  Vector1C0
+#define TIVA_WGPT1B_HANDLER                  Vector1C4
+#define TIVA_WGPT2A_HANDLER                  Vector1C8
+#define TIVA_WGPT2B_HANDLER                  Vector1CC
+#define TIVA_WGPT3A_HANDLER                  Vector1D0
+#define TIVA_WGPT3B_HANDLER                  Vector1D4
+#define TIVA_WGPT4A_HANDLER                  Vector1D8
+#define TIVA_WGPT4B_HANDLER                  Vector1DC
+#define TIVA_WGPT5A_HANDLER                  Vector1E0
+#define TIVA_WGPT5B_HANDLER                  Vector1E4
+
+#define TIVA_WGPT0A_NUMBER                   94
+#define TIVA_WGPT0B_NUMBER                   95
+#define TIVA_WGPT1A_NUMBER                   96
+#define TIVA_WGPT1B_NUMBER                   97
+#define TIVA_WGPT2A_NUMBER                   98
+#define TIVA_WGPT2B_NUMBER                   99
+#define TIVA_WGPT3A_NUMBER                   100
+#define TIVA_WGPT3B_NUMBER                   101
+#define TIVA_WGPT4A_NUMBER                   102
+#define TIVA_WGPT4B_NUMBER                   103
+#define TIVA_WGPT5A_NUMBER                   104
+#define TIVA_WGPT5B_NUMBER                   105
+#endif
+
+/* WDT units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_WDT_HANDLER                    Vector88
+
+#define TIVA_WDT_NUMBER                     18
+#endif
+
+/* ADC units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_ADC0_SEQ0_HANDLER              Vector78
+#define TIVA_ADC0_SEQ1_HANDLER              Vector7C
+#define TIVA_ADC0_SEQ2_HANDLER              Vector80
+#define TIVA_ADC0_SEQ3_HANDLER              Vector84
+#define TIVA_ADC1_SEQ0_HANDLER              Vector100
+#define TIVA_ADC1_SEQ1_HANDLER              Vector104
+#define TIVA_ADC1_SEQ2_HANDLER              Vector108
+#define TIVA_ADC1_SEQ3_HANDLER              Vector10C
+
+#define TIVA_ADC0_SEQ0_NUMBER               14
+#define TIVA_ADC0_SEQ1_NUMBER               15
+#define TIVA_ADC0_SEQ2_NUMBER               16
+#define TIVA_ADC0_SEQ3_NUMBER               17
+#define TIVA_ADC1_SEQ0_NUMBER               48
+#define TIVA_ADC1_SEQ1_NUMBER               49
+#define TIVA_ADC1_SEQ2_NUMBER               50
+#define TIVA_ADC1_SEQ3_NUMBER               51
+#endif
+
+/* UART units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_UART0_HANDLER                  Vector54
+#define TIVA_UART1_HANDLER                  Vector58
+#define TIVA_UART2_HANDLER                  VectorC4
+#define TIVA_UART3_HANDLER                  Vector12C
+#define TIVA_UART4_HANDLER                  Vector130
+#define TIVA_UART5_HANDLER                  Vector134
+#define TIVA_UART6_HANDLER                  Vector138
+#define TIVA_UART7_HANDLER                  Vector13C
+
+#define TIVA_UART0_NUMBER                   5
+#define TIVA_UART1_NUMBER                   6
+#define TIVA_UART2_NUMBER                   33
+#define TIVA_UART3_NUMBER                   59
+#define TIVA_UART4_NUMBER                   60
+#define TIVA_UART5_NUMBER                   61
+#define TIVA_UART6_NUMBER                   62
+#define TIVA_UART7_NUMBER                   63
+#endif
+
+/* SPI units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_SSI0_HANDLER                   Vector5C
+#define TIVA_SSI1_HANDLER                   VectorC8
+#define TIVA_SSI2_HANDLER                   Vector124
+#define TIVA_SSI3_HANDLER                   Vector128
+
+#define TIVA_SSI0_NUMBER                    7
+#define TIVA_SSI1_NUMBER                    34
+#define TIVA_SSI2_NUMBER                    57
+#define TIVA_SSI3_NUMBER                    58
+#endif
+
+/* I2C units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \
+  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \
+  || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
+  || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ)  \
+  || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \
+  || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_I2C0_HANDLER                   Vector60
+#define TIVA_I2C1_HANDLER                   VectorD4
+#define TIVA_I2C2_HANDLER                   Vector150
+#define TIVA_I2C3_HANDLER                   Vector154
+#define TIVA_I2C4_HANDLER                   Vector1F4
+#define TIVA_I2C5_HANDLER                   Vector1F8
+
+#define TIVA_I2C0_NUMBER                    8
+#define TIVA_I2C1_NUMBER                    37
+#define TIVA_I2C2_NUMBER                    68
+#define TIVA_I2C3_NUMBER                    69
+#define TIVA_I2C4_NUMBER                    109
+#define TIVA_I2C5_NUMBER                    110
+#endif
+#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
+  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
+  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
+  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#define TIVA_I2C0_HANDLER                   Vector60
+#define TIVA_I2C1_HANDLER                   VectorD4
+#define TIVA_I2C2_HANDLER                   Vector150
+#define TIVA_I2C3_HANDLER                   Vector154
+
+#define TIVA_I2C0_NUMBER                    8
+#define TIVA_I2C1_NUMBER                    37
+#define TIVA_I2C2_NUMBER                    68
+#define TIVA_I2C3_NUMBER                    69
+#endif
+
+/* CAN units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ)
+#define TIVA_CAN0_HANDLER                   VectorDC
+
+#define TIVA_CAN0_NUMBER                    39
+#endif
+#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
+  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
+  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_CAN0_HANDLER                   VectorDC
+#define TIVA_CAN1_HANDLER                   VectorE0
+
+#define TIVA_CAN0_NUMBER                    39
+#define TIVA_CAN1_NUMBER                    40
+#endif
+
+/* USB units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)  \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB)
+/* No interrupt handler and number.*/
+#endif
+#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)   \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)  \
+  || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
+  || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \
+  || defined(TM4C123GH5ZXR)
+#define TIVA_USB0_HANDLER                   VectorF0
+
+#define TIVA_USB0_NUMBER                    44
+#endif
+
+/* AC units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM)  \
+  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
+  || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM)  \
+  || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
+  || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM)  \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#define TIVA_AC0_HANDLER                    VectorA4
+#define TIVA_AC1_HANDLER                    VectorA8
+
+#define TIVA_AC0_NUMBER                     25
+#define TIVA_AC1_NUMBER                     26
+#endif
+#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE)  \
+  || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \
+  || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_AC0_HANDLER                    VectorA4
+#define TIVA_AC1_HANDLER                    VectorA8
+#define TIVA_AC2_HANDLER                    VectorAC
+
+#define TIVA_AC0_NUMBER                     25
+#define TIVA_AC1_NUMBER                     26
+#define TIVA_AC2_NUMBER                     27
+#endif
+
+/* PWM units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ)
+/* No interrupt handler and number.*/
+#endif
+#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
+  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
+  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_PWM0FAULT_HANDLER              Vector64
+#define TIVA_PWM0GEN0_HANDLER               Vector68
+#define TIVA_PWM0GEN1_HANDLER               Vector6C
+#define TIVA_PWM0GEN2_HANDLER               Vector70
+#define TIVA_PWM0GEN3_HANDLER               VectorF4
+#define TIVA_PWM1FAULT_HANDLER              Vector268
+#define TIVA_PWM1GEN0_HANDLER               Vector258
+#define TIVA_PWM1GEN1_HANDLER               Vector25C
+#define TIVA_PWM1GEN2_HANDLER               Vector260
+#define TIVA_PWM1GEN3_HANDLER               Vector264
+
+#define TIVA_PWM0FAULT_NUMBER               9
+#define TIVA_PWM0GEN0_NUMBER                10
+#define TIVA_PWM0GEN1_NUMBER                11
+#define TIVA_PWM0GEN2_NUMBER                12
+#define TIVA_PWM0GEN3_NUMBER                45
+#define TIVA_PWM1FAULT_NUMBER               138
+#define TIVA_PWM1GEN0_NUMBER                134
+#define TIVA_PWM1GEN1_NUMBER                135
+#define TIVA_PWM1GEN2_NUMBER                136
+#define TIVA_PWM1GEN3_NUMBER                137
+#endif
+
+/* QEI units.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)
+/* No interrupt handler and number.*/
+#endif
+#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE)  \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_QEI0_HANLDER                   Vector74
+#define TIVA_QEI1_HANLDER                   VectorD8
+
+#define TIVA_QEI0_NUMBER                    13
+#define TIVA_QEI1_NUMBER                    38
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#endif /* _TIVA_ISR_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
new file mode 100644
index 0000000..c626428
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h
@@ -0,0 +1,492 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TM4C123x/tiva_registry.h
+ * @brief   TM4C123x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _TIVA_REGISTRY_H_
+#define _TIVA_REGISTRY_H_
+
+/*===========================================================================*/
+/* Defined device check.                                                     */
+/*===========================================================================*/
+
+#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) &&                       \
+  !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) &&                         \
+  !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) &&                         \
+  !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) &&                         \
+  !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) &&                        \
+  !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) &&                         \
+  !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) &&                         \
+  !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) &&                         \
+  !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) &&                         \
+  !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) &&                         \
+  !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) &&                        \
+  !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) &&                         \
+  !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) &&                         \
+  !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) &&                         \
+  !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) &&                         \
+  !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) &&                        \
+  !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) &&                         \
+  !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) &&                         \
+  !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) &&                         \
+  !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) &&                        \
+  !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) &&                        \
+  !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) &&                         \
+  !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) &&                         \
+  !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) &&                        \
+  !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) &&                        \
+  !defined(TM4C123GH5ZXR)
+#error "No valid device defined."
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    TM4C123x capabilities
+ * @{
+ */
+
+/* GPIO attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM)  \
+  || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM)  \
+  || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM)  \
+  || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      TRUE
+#define TIVA_HAS_GPIOH                      FALSE
+#define TIVA_HAS_GPIOJ                      FALSE
+#define TIVA_HAS_GPIOK                      FALSE
+#define TIVA_HAS_GPIOL                      FALSE
+#define TIVA_HAS_GPIOM                      FALSE
+#define TIVA_HAS_GPION                      FALSE
+#define TIVA_HAS_GPIOP                      FALSE
+#define TIVA_HAS_GPIOQ                      FALSE
+#define TIVA_HAS_GPIOR                      FALSE
+#define TIVA_HAS_GPIOS                      FALSE
+#define TIVA_HAS_GPIOT                      FALSE
+#endif
+#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
+  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
+  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
+  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      FALSE
+#define TIVA_HAS_GPIOH                      FALSE
+#define TIVA_HAS_GPIOJ                      FALSE
+#define TIVA_HAS_GPIOK                      FALSE
+#define TIVA_HAS_GPIOL                      FALSE
+#define TIVA_HAS_GPIOM                      FALSE
+#define TIVA_HAS_GPION                      FALSE
+#define TIVA_HAS_GPIOP                      FALSE
+#define TIVA_HAS_GPIOQ                      FALSE
+#define TIVA_HAS_GPIOR                      FALSE
+#define TIVA_HAS_GPIOS                      FALSE
+#define TIVA_HAS_GPIOT                      FALSE
+#endif
+#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ)   \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ)  \
+  || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ)  \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ)  \
+  || defined(TM4C123GH6PZ)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      TRUE
+#define TIVA_HAS_GPIOH                      TRUE
+#define TIVA_HAS_GPIOJ                      TRUE
+#define TIVA_HAS_GPIOK                      TRUE
+#define TIVA_HAS_GPIOL                      TRUE
+#define TIVA_HAS_GPIOM                      FALSE
+#define TIVA_HAS_GPION                      FALSE
+#define TIVA_HAS_GPIOP                      FALSE
+#define TIVA_HAS_GPIOQ                      FALSE
+#define TIVA_HAS_GPIOR                      FALSE
+#define TIVA_HAS_GPIOS                      FALSE
+#define TIVA_HAS_GPIOT                      FALSE
+#endif
+#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\
+  || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      TRUE
+#define TIVA_HAS_GPIOH                      TRUE
+#define TIVA_HAS_GPIOJ                      TRUE
+#define TIVA_HAS_GPIOK                      TRUE
+#define TIVA_HAS_GPIOL                      TRUE
+#define TIVA_HAS_GPIOM                      TRUE
+#define TIVA_HAS_GPION                      TRUE
+#define TIVA_HAS_GPIOP                      TRUE
+#define TIVA_HAS_GPIOQ                      FALSE
+#define TIVA_HAS_GPIOR                      FALSE
+#define TIVA_HAS_GPIOS                      FALSE
+#define TIVA_HAS_GPIOT                      FALSE
+#endif
+#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      TRUE
+#define TIVA_HAS_GPIOH                      TRUE
+#define TIVA_HAS_GPIOJ                      TRUE
+#define TIVA_HAS_GPIOK                      TRUE
+#define TIVA_HAS_GPIOL                      TRUE
+#define TIVA_HAS_GPIOM                      TRUE
+#define TIVA_HAS_GPION                      TRUE
+#define TIVA_HAS_GPIOP                      TRUE
+#define TIVA_HAS_GPIOQ                      TRUE
+#define TIVA_HAS_GPIOR                      FALSE
+#define TIVA_HAS_GPIOS                      FALSE
+#define TIVA_HAS_GPIOT                      FALSE
+#endif
+
+/* GPTM attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_GPT0                       TRUE
+#define TIVA_HAS_GPT1                       TRUE
+#define TIVA_HAS_GPT2                       TRUE
+#define TIVA_HAS_GPT3                       TRUE
+#define TIVA_HAS_GPT4                       TRUE
+#define TIVA_HAS_GPT5                       TRUE
+#define TIVA_HAS_GPT6                       FALSE
+#define TIVA_HAS_GPT7                       FALSE
+#define TIVA_HAS_WGPT0                      TRUE
+#define TIVA_HAS_WGPT1                      TRUE
+#define TIVA_HAS_WGPT2                      TRUE
+#define TIVA_HAS_WGPT3                      TRUE
+#define TIVA_HAS_WGPT4                      TRUE
+#define TIVA_HAS_WGPT5                      TRUE
+#endif
+
+/* WDT attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_WDT0                       TRUE
+#define TIVA_HAS_WDT1                       TRUE
+#endif
+
+/* ADC attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_ADC0                       TRUE
+#define TIVA_HAS_ADC1                       TRUE
+#endif
+
+/* UART attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_UART0                      TRUE
+#define TIVA_HAS_UART1                      TRUE
+#define TIVA_HAS_UART2                      TRUE
+#define TIVA_HAS_UART3                      TRUE
+#define TIVA_HAS_UART4                      TRUE
+#define TIVA_HAS_UART5                      TRUE
+#define TIVA_HAS_UART6                      TRUE
+#define TIVA_HAS_UART7                      TRUE
+#endif
+
+/* SPI attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_SSI0                       TRUE
+#define TIVA_HAS_SSI1                       TRUE
+#define TIVA_HAS_SSI2                       TRUE
+#define TIVA_HAS_SSI3                       TRUE
+#endif
+
+/* I2C attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \
+  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \
+  || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
+  || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ)  \
+  || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \
+  || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_I2C0                       TRUE
+#define TIVA_HAS_I2C1                       TRUE
+#define TIVA_HAS_I2C2                       TRUE
+#define TIVA_HAS_I2C3                       TRUE
+#define TIVA_HAS_I2C4                       TRUE
+#define TIVA_HAS_I2C5                       TRUE
+#define TIVA_HAS_I2C6                       FALSE
+#define TIVA_HAS_I2C7                       FALSE
+#define TIVA_HAS_I2C8                       FALSE
+#define TIVA_HAS_I2C9                       FALSE
+#endif
+#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM)   \
+  || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM)  \
+  || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM)  \
+  || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#define TIVA_HAS_I2C0                       TRUE
+#define TIVA_HAS_I2C1                       TRUE
+#define TIVA_HAS_I2C2                       TRUE
+#define TIVA_HAS_I2C3                       TRUE
+#define TIVA_HAS_I2C4                       FALSE
+#define TIVA_HAS_I2C5                       FALSE
+#define TIVA_HAS_I2C6                       FALSE
+#define TIVA_HAS_I2C7                       FALSE
+#define TIVA_HAS_I2C8                       FALSE
+#define TIVA_HAS_I2C9                       FALSE
+#endif
+
+/* CAN attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ)
+#define TIVA_HAS_CAN0                       TRUE
+#define TIVA_HAS_CAN1                       FALSE
+#endif
+#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
+  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
+  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_CAN0                       TRUE
+#define TIVA_HAS_CAN1                       TRUE
+#endif
+
+/* USB attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)  \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB)
+#define TIVA_HAS_USB0                       FALSE
+#endif
+#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)   \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM)  \
+  || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \
+  || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \
+  || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_USB0                       TRUE
+#endif
+
+/* AC attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM)  \
+  || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM)  \
+  || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM)  \
+  || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM)  \
+  || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)  \
+  || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM)  \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM)
+#define TIVA_HAS_AC0                        TRUE
+#define TIVA_HAS_AC1                        TRUE
+#define TIVA_HAS_AC2                        FALSE
+#endif
+#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE)  \
+  || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \
+  || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_AC0                        TRUE
+#define TIVA_HAS_AC1                        TRUE
+#define TIVA_HAS_AC2                        TRUE
+#endif
+
+/* PWM attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ)
+#define TIVA_HAS_PWM0                       FALSE
+#define TIVA_HAS_PWM1                       FALSE
+#endif
+#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM)   \
+  || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \
+  || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \
+  || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ)  \
+  || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \
+  || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_PWM0                       TRUE
+#define TIVA_HAS_PWM1                       TRUE
+#endif
+
+/* QEI attributes.*/
+#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM)   \
+  || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM)  \
+  || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ)  \
+  || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \
+  || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM)  \
+  || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM)  \
+  || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ)  \
+  || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \
+  || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM)  \
+  || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM)  \
+  || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \
+  || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM)
+#define TIVA_HAS_QEI0                       FALSE
+#define TIVA_HAS_QEI1                       FALSE
+#endif
+#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE)  \
+  || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \
+  || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM)  \
+  || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \
+  || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR)
+#define TIVA_HAS_QEI0                       TRUE
+#define TIVA_HAS_QEI1                       TRUE
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _TIVA_REGISTRY_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
new file mode 100644
index 0000000..f7bb8f5
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h
@@ -0,0 +1,962 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @addtogroup CMSIS
+ * @{
+ */
+
+/**
+ * @addtogroup TM4C123x
+ * @{
+ */
+
+#ifndef __TM4C123x_H
+#define __TM4C123x_H
+
+/** 
+ * @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __CM4_REV               0x0001  /**< Cortex-M4 Core Revision         */
+#define __MPU_PRESENT           1       /**< MPU present                     */
+#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
+#define __Vendor_SysTickConfig  0       /**< Use different SysTick Config    */
+#define __FPU_PRESENT           1       /**< FPU present                     */
+
+/**
+ * @brief   TM4C123x Interrupt Number Definitions
+ */
+typedef enum IRQn
+{
+  /***** Cortex-M4 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14,  /**< Cortex-M4 Non-Maskable Interrupt        */
+  HardFault_IRQn        = -13,  /**< Cortex-M4 Hard Fault Interrupt          */
+  MemoryManagement_IRQn = -12,  /**< Cortex-M4 Memory Management Interrupt   */
+  BusFault_IRQn         = -11,  /**< Cortex-M4 Bus Fault Interrupt           */
+  UsageFault_IRQn       = -10,  /**< Cortex-M4 Usage Fault Interrupt         */
+  SVCall_IRQn           = -5,   /**< Cortex-M4 SV Call Interrupt             */
+  DebugMonitor_IRQn     = -4,   /**< Cortex-M4 Debug Monitor Interrupt       */
+  PendSV_IRQn           = -3,   /**< Cortex-M4 Pend SV Interrupt             */
+  SysTick_IRQn          = -1,   /**< Cortex-M4 System Tick Interrupt         */
+  /***** TM4C123x Specific Interrupt Numbers *********************************/
+  GPIOA_IRQn            = 0,    /**< GPIO Port A                             */
+  GPIOB_IRQn            = 1,    /**< GPIO Port B                             */
+  GPIOC_IRQn            = 2,    /**< GPIO Port C                             */
+  GPIOD_IRQn            = 3,    /**< GPIO Port D                             */
+  GPIOE_IRQn            = 4,    /**< GPIO Port E                             */
+  UART0_IRQn            = 5,    /**< UART0                                   */
+  UART1_IRQn            = 6,    /**< UART1                                   */
+  SSI0_IRQn             = 7,    /**< SSI0                                    */
+  I2C0_IRQn             = 8,    /**< I2C0                                    */
+  PWM0FAULT_IRQn        = 9,    /**< PWM0 Fault                              */
+  PWM0GEN0_IRQn         = 10,   /**< PWM0 Generator 0                        */
+  PWM0GEN1_IRQn         = 11,   /**< PWM0 Generator 1                        */
+  PWM0GEN2_IRQn         = 12,   /**< PWM0 Generator 2                        */
+  QEI0_IRQn             = 13,   /**< QEI0                                    */
+  ADC0SEQ0_IRQn         = 14,   /**< ADC0 Sequence 0                         */
+  ADC0SEQ1_IRQn         = 15,   /**< ADC0 Sequence 1                         */
+  ADC0SEQ2_IRQn         = 16,   /**< ADC0 Sequence 2                         */
+  ADC0SEQ3_IRQn         = 17,   /**< ADC0 Sequence 3                         */
+  WATCHDOG_IRQn         = 18,   /**< Watchdog Timers 0 and 1                 */
+  TIMER0A_IRQn          = 19,   /**< 16/32-Bit Timer 0A                      */
+  TIMER0B_IRQn          = 20,   /**< 16/32-Bit Timer 0B                      */
+  TIMER1A_IRQn          = 21,   /**< 16/32-Bit Timer 1A                      */
+  TIMER1B_IRQn          = 22,   /**< 16/32-Bit Timer 1B                      */
+  TIMER2A_IRQn          = 23,   /**< 16/32-Bit Timer 2A                      */
+  TIMER2B_IRQn          = 24,   /**< 16/32-Bit Timer 2B                      */
+  ACOMP0_IRQn           = 25,   /**< Analog Comparator 0                     */
+  ACOMP1_IRQn           = 26,   /**< Analog Comparator 1                     */
+  SYSCON_IRQn           = 28,   /**< System Control                          */
+  FMCEECON_IRQn         = 29,   /**< Flash Memory Control and EEPROM Control */
+  GPIOF_IRQn            = 30,   /**< GPIO Port F                             */
+  UART2_IRQn            = 33,   /**< UART2                                   */
+  SSI1_IRQn             = 34,   /**< SSI1                                    */
+  TIMER3A_IRQn          = 35,   /**< 16/32-Bit Timer 3A                      */
+  TIMER3B_IRQn          = 36,   /**< 16/32-Bit Timer 3B                      */
+  I2C1_IRQn             = 37,   /**< I2C1                                    */
+  QEI1_IRQn             = 38,   /**< QEI1                                    */
+  CAN0_IRQn             = 39,   /**< CAN0                                    */
+  CAN1_IRQn             = 40,   /**< CAN1                                    */
+  HIBMODULE_IRQn        = 43,   /**< Hibernation Module                      */
+  USB_IRQn              = 44,   /**< USB                                     */
+  PWM0GEN3_IRQn         = 45,   /**< PWM0 Generator 3                        */
+  UDMASFW_IRQn          = 46,   /**< UDMA Software                           */
+  UDMAERR_IRQn          = 47,   /**< UDMA Error                              */
+  ADC1SEQ0_IRQn         = 48,   /**< ADC1 Sequence 0                         */
+  ADC1SEQ1_IRQn         = 49,   /**< ADC1 Sequence 1                         */
+  ADC1SEQ2_IRQn         = 50,   /**< ADC1 Sequence 2                         */
+  ADC1SEQ3_IRQn         = 51,   /**< ADC1 Sequence 3                         */
+  SSI2_IRQn             = 57,   /**< SSI2                                    */
+  SSI3_IRQn             = 58,   /**< SSI3                                    */
+  UART3_IRQn            = 59,   /**< UART3                                   */
+  UART4_IRQn            = 60,   /**< UART4                                   */
+  UART5_IRQn            = 61,   /**< UART5                                   */
+  UART6_IRQn            = 62,   /**< UART6                                   */
+  UART7_IRQn            = 63,   /**< UART7                                   */
+  I2C2_IRQn             = 68,   /**< I2C2                                    */
+  I2C3_IRQn             = 69,   /**< I2C3                                    */
+  TIMER4A_IRQn          = 70,   /**< 16/32-Bit Timer 4A                      */
+  TIMER4B_IRQn          = 71,   /**< 16/32-Bit Timer 4B                      */
+  TIMER5A_IRQn          = 92,   /**< 16/32-Bit Timer 5A                      */
+  TIMER5B_IRQn          = 93,   /**< 16/32-Bit Timer 5B                      */
+  WTIMER0A_IRQn         = 94,   /**< 32/64-Bit Timer 0A                      */
+  WTIMER0B_IRQn         = 95,   /**< 32/64-Bit Timer 0B                      */
+  WTIMER1A_IRQn         = 96,   /**< 32/64-Bit Timer 1A                      */
+  WTIMER1B_IRQn         = 97,   /**< 32/64-Bit Timer 1B                      */
+  WTIMER2A_IRQn         = 98,   /**< 32/64-Bit Timer 2A                      */
+  WTIMER2B_IRQn         = 99,   /**< 32/64-Bit Timer 2B                      */
+  WTIMER3A_IRQn         = 100,  /**< 32/64-Bit Timer 3A                      */
+  WTIMER3B_IRQn         = 101,  /**< 32/64-Bit Timer 3B                      */
+  WTIMER4A_IRQn         = 102,  /**< 32/64-Bit Timer 4A                      */
+  WTIMER4B_IRQn         = 103,  /**< 32/64-Bit Timer 4B                      */
+  WTIMER5A_IRQn         = 104,  /**< 32/64-Bit Timer 5A                      */
+  WTIMER5B_IRQn         = 105,  /**< 32/64-Bit Timer 5B                      */
+  SYSEXCEPT_IRQn        = 106,  /**< System Exception (imprecise)            */
+  PWM1GEN0_IRQn         = 134,  /**< PWM1 Generator 0                        */
+  PWM1GEN1_IRQn         = 135,  /**< PWM1 Generator 1                        */
+  PWM1GEN2_IRQn         = 136,  /**< PWM1 Generator 2                        */
+  PWM1GEN3_IRQn         = 137,  /**< PWM1 Generator 3                        */
+  PWM1FAULT_IRQn        = 138   /**< PWM1 Fault                              */
+} IRQn_Type;
+ 
+/**
+ * @}
+ */
+
+#include "core_cm4.h"   /* Cortex-M4 processor and core peripherals.*/
+#include <stdint.h>
+
+/**
+ * @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog Comparator
+ */
+typedef struct
+{
+  __IO uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t REFCTL;         /**< Reference Voltage Control               */
+  __I  uint32_t RESERVED1[3];   /**< Reserved                                */
+  __I  uint32_t STAT0;          /**< Status 0                                */
+  __IO uint32_t CTL0;           /**< Control 0                               */
+  __I  uint32_t RESERVED2[6];   /**< Reserved                                */
+  __I  uint32_t STAT1;          /**< Status 1                                */
+  __IO uint32_t CTL1;           /**< Control 1                               */
+  __I  uint32_t RESERVED3[990]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+} AC_TypeDef;
+
+/**
+ * @brief Analog-to-Digital Converter
+ */
+typedef struct
+{
+  __IO uint32_t ACTSS;          /**< Active Sample Sequencer                 */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+  __IO uint32_t OSTAT;          /**< Overflow Status                         */
+  __IO uint32_t EMUX;           /**< Event Multiplexer Select                */
+  __IO uint32_t USTAT;          /**< Underflow Status                        */
+  __IO uint32_t TSSEL;          /**< Trigger Source Select                   */
+  __IO uint32_t SSPRI;          /**< Sample Sequencer Priority               */
+  __IO uint32_t SPC;            /**< Sample Phase Control                    */
+  __IO uint32_t PSSI;           /**< Processor Sample Sequence Initiate      */
+  __I  uint32_t RESERVED1[1];   /**< Reserved                                */
+  __IO uint32_t SAC;            /**< Sample Averaging Control                */
+  __IO uint32_t DCISC;          /**< Digital Comparator Interrupt Status and
+                                     Clear                                   */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __I  uint32_t RESERVED2[1];   /**< Reserved                                */
+  __IO uint32_t SSMUX0;         /**< Sample Sequence Input Multiplexer Select
+                                     0                                       */
+  __IO uint32_t SSCTL0;         /**< Sample Sequence Control 0               */
+  __I  uint32_t SSFIFO0;        /**< Sample Sequence Result FIFO 0           */
+  __I  uint32_t SSFSTAT0;       /**< Sample Sequence FIFO 0 Status           */
+  __IO uint32_t SSOP0;          /**< Sample Sequence 0 Operation             */
+  __IO uint32_t SSDC0;          /**< Sample Sequence 0 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED3[2];   /**< Reserved                                */
+  __IO uint32_t SSMUX1;         /**< Sample Sequence Input Multiplexer Select
+                                     1                                       */
+  __IO uint32_t SSCTL1;         /**< Sample Sequence Control 1               */
+  __I  uint32_t SSFIFO1;        /**< Sample Sequence Result FIFO 1           */
+  __I  uint32_t SSFSTAT1;       /**< Sample Sequence FIFO 1 Status           */
+  __IO uint32_t SSOP1;          /**< Sample Sequence 1 Operation             */
+  __IO uint32_t SSDC1;          /**< Sample Sequence 1 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED4[2];   /**< Reserved                                */
+  __IO uint32_t SSMUX2;         /**< Sample Sequence Input Multiplexer Select
+                                     2                                       */
+  __IO uint32_t SSCTL2;         /**< Sample Sequence Control 2               */
+  __I  uint32_t SSFIFO2;        /**< Sample Sequence Result FIFO 2           */
+  __I  uint32_t SSFSTAT2;       /**< Sample Sequence FIFO 2 Status           */
+  __IO uint32_t SSOP2;          /**< Sample Sequence 2 Operation             */
+  __IO uint32_t SSDC2;          /**< Sample Sequence 2 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED5[2];   /**< Reserved                                */
+  __IO uint32_t SSMUX3;         /**< Sample Sequence Input Multiplexer Select
+                                     3                                       */
+  __IO uint32_t SSCTL3;         /**< Sample Sequence Control 3               */
+  __I  uint32_t SSFIFO3;        /**< Sample Sequence Result FIFO 3           */
+  __I  uint32_t SSFSTAT3;       /**< Sample Sequence FIFO 3 Status           */
+  __IO uint32_t SSOP3;          /**< Sample Sequence 3 Operation             */
+  __IO uint32_t SSDC3;          /**< Sample Sequence 3 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED6[786]; /**< Reserved                                */
+  __O  uint32_t DCRIC;          /**< Digital Comparator Reset Initial
+                                     Conditions                              */
+  __I  uint32_t RESERVED7[63];  /**< Reserved                                */
+  __IO uint32_t DCCTL0;         /**< Digital Comparator Control 0            */
+  __IO uint32_t DCCTL1;         /**< Digital Comparator Control 1            */
+  __IO uint32_t DCCTL2;         /**< Digital Comparator Control 2            */
+  __IO uint32_t DCCTL3;         /**< Digital Comparator Control 3            */
+  __IO uint32_t DCCTL4;         /**< Digital Comparator Control 4            */
+  __IO uint32_t DCCTL5;         /**< Digital Comparator Control 5            */
+  __IO uint32_t DCCTL6;         /**< Digital Comparator Control 6            */
+  __IO uint32_t DCCTL7;         /**< Digital Comparator Control 7            */
+  __I  uint32_t RESERVED8[8];   /**< Reserved                                */
+  __IO uint32_t DCCMP0;         /**< Digital Comparator Range 0              */
+  __IO uint32_t DCCMP1;         /**< Digital Comparator Range 1              */
+  __IO uint32_t DCCMP2;         /**< Digital Comparator Range 2              */
+  __IO uint32_t DCCMP3;         /**< Digital Comparator Range 3              */
+  __IO uint32_t DCCMP4;         /**< Digital Comparator Range 4              */
+  __IO uint32_t DCCMP5;         /**< Digital Comparator Range 5              */
+  __IO uint32_t DCCMP6;         /**< Digital Comparator Range 6              */
+  __IO uint32_t DCCMP7;         /**< Digital Comparator Range 7              */
+  __I  uint32_t RESERVED9[88];  /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __IO uint32_t PC;             /**< Peripheral Configuration                */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} ADC_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t STS;            /**< Status                                  */
+  __I  uint32_t ERR;            /**< Error Counter                           */
+  __IO uint32_t BIT;            /**< Bit Timing                              */
+  __I  uint32_t INT;            /**< Interrupt                               */
+  __IO uint32_t TST;            /**< Test                                    */
+  __IO uint32_t BRPE;           /**< Baud Rate Prescaler Extension           */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t IF1CRQ;         /**< IF1 Command Request                     */
+  __IO uint32_t IF1CMSK;        /**< IF1 Command Mask                        */
+  __IO uint32_t IF1MSK1;        /**< IF1 Mask 1                              */
+  __IO uint32_t IF1MSK2;        /**< IF1 Mask 2                              */
+  __IO uint32_t IF1ARB1;        /**< IF1 Arbitration 1                       */
+  __IO uint32_t IF1ARB2;        /**< IF1 Arbitration 2                       */
+  __IO uint32_t IF1MCTL;        /**< IF1 Message Control                     */
+  __IO uint32_t IF1DA1;         /**< IF1 Data A1                             */
+  __IO uint32_t IF1DA2;         /**< IF1 Data A2                             */
+  __IO uint32_t IF1DB1;         /**< IF1 Data B1                             */
+  __IO uint32_t IF1DB2;         /**< IF1 Data B2                             */
+  __I  uint32_t RESERVED1[13];  /**< Reserved                                */
+  __IO uint32_t IF2CRQ;         /**< IF2 Command Request                     */
+  __IO uint32_t IF2CMSK;        /**< IF2 Command Mask                        */
+  __IO uint32_t IF2MSK1;        /**< IF2 Mask 1                              */
+  __IO uint32_t IF2MSK2;        /**< IF2 Mask 2                              */
+  __IO uint32_t IF2ARB1;        /**< IF2 Arbitration 1                       */
+  __IO uint32_t IF2ARB2;        /**< IF2 Arbitration 2                       */
+  __IO uint32_t IF2MCTL;        /**< IF2 Message Control                     */
+  __IO uint32_t IF2DA1;         /**< IF2 Data A1                             */
+  __IO uint32_t IF2DA2;         /**< IF2 Data A2                             */
+  __IO uint32_t IF2DB1;         /**< IF2 Data B1                             */
+  __IO uint32_t IF2DB2;         /**< IF2 Data B2                             */
+  __I  uint32_t RESERVED2[21];  /**< Reserved                                */
+  __I  uint32_t TXRQ1;          /**< Transmission Request 1                  */
+  __I  uint32_t TXRQ2;          /**< Transmission Request 2                  */
+  __I  uint32_t RESERVED3[6];   /**< Reserved                                */
+  __I  uint32_t NWDA1;          /**< New Data 1                              */
+  __I  uint32_t NWDA2;          /**< New Data 2                              */
+  __I  uint32_t RESERVED4[6];   /**< Reserved                                */
+  __I  uint32_t MSG1INT;        /**< Message 1 Interrupt Pending             */
+  __I  uint32_t MSG2INT;        /**< Message 2 Interrupt Pending             */
+  __I  uint32_t RESERVED5[6];   /**< Reserved                                */
+  __I  uint32_t MSG1VAL;        /**< Message 1 Valid                         */
+  __I  uint32_t MSG2VAL;        /**< Message 2 Valid                         */
+} CAN_TypeDef;
+
+/**
+ * @brief EEPROM Memory
+ */
+typedef struct
+{
+  __IO uint32_t EESIZE;         /**< Size Information                        */
+  __IO uint32_t EEBLOCK;        /**< Current Block                           */
+  __IO uint32_t EEOFFSET;       /**< Current Offset                          */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t EERDWR;         /**< Read-Write                              */
+  __IO uint32_t EERDWRINC;      /**< Read-Write with Increment               */
+  __IO uint32_t EEDONE;         /**< Done Status                             */
+  __IO uint32_t EESUPP;         /**< Support Control and Status              */
+  __IO uint32_t EEUNLOCK;       /**< Unlock                                  */
+  __I  uint32_t RESERVED1[3];   /**< Reserved                                */
+  __IO uint32_t EEPROT;         /**< Protection                              */
+  __IO uint32_t EEPASS0;        /**< Password                                */
+  __IO uint32_t EEPASS1;        /**< Password                                */
+  __IO uint32_t EEPASS2;        /**< Password                                */
+  __IO uint32_t EEINT;          /**< Interrupt                               */
+  __I  uint32_t RESERVED2[3];   /**< Reserved                                */
+  __IO uint32_t EEHIDE;         /**< Block Hide                              */
+  __I  uint32_t RESERVED3[11];  /**< Reserved                                */
+  __IO uint32_t EEDBGME;        /**< Debug Mass Erase                        */
+  __I  uint32_t RESERVED4[975]; /**< Reserved                                */
+  __IO uint32_t EEPROMPP;       /**< Peripheral Properties                   */
+} EEPROM_TypeDef;
+
+/**
+ * @brief Flash Memory
+ */
+typedef struct
+{
+  __IO uint32_t FMA;            /**< Flash Memory Address                    */
+  __IO uint32_t FMD;            /**< Flash Memory Data                       */
+  __IO uint32_t FMC;            /**< Flash Memory Control                    */
+  __I  uint32_t FCRIS;          /**< Flash Controller Raw Interrupt Status   */
+  __IO uint32_t FCIM;           /**< Flash Controller Interrupt Mask         */
+  __IO uint32_t FCMISC;         /**< Masked Interrupt Status and Clear       */
+  __I  uint32_t RESERVED0[2];   /**< Reserved                                */
+  __IO uint32_t FMC2;           /**< Flash Memory Control 2                  */
+  __I  uint32_t RESERVED1[3];   /**< Reserved                                */
+  __IO uint32_t FWBVAL;         /**< Flash Write Buffer Valid                */
+  __I  uint32_t RESERVED2[51];  /**< Reserved                                */
+  __IO uint32_t FWBN;           /**< Flash Write Buffer n                    */
+  __I  uint32_t RESERVED3[943]; /**< Reserved                                */
+  __I  uint32_t FSIZE;          /**< Flash Size                              */
+  __I  uint32_t SSIZE;          /**< SRAM Size                               */
+  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
+  __IO uint32_t ROMSWMAP;       /**< ROM Software Map                        */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose Input/Outputs
+ */
+typedef struct
+{
+  union {
+    __IO uint32_t MASKED_ACCESS[256];   /**< Masked access of Data Register  */
+    struct {
+      __I  uint32_t RESERVED0[255];     /**< Reserved                        */
+      __IO uint32_t DATA;       /**< Data                                    */
+    };
+  };
+  __IO uint32_t DIR;            /**< Direction                               */
+  __IO uint32_t IS;             /**< Interrupt Sense                         */
+  __IO uint32_t IBE;            /**< Interrupt Both Edges                    */
+  __IO uint32_t IEV;            /**< Interrupt Event                         */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __IO uint32_t AFSEL;          /**< Alternate Function Select               */
+  __I  uint32_t RESERVED1[55];  /**< Reserved                                */
+  __IO uint32_t DR2R;           /**< 2-mA Drive Select                       */
+  __IO uint32_t DR4R;           /**< 4-mA Drive Select                       */
+  __IO uint32_t DR8R;           /**< 8-mA Drive Select                       */
+  __IO uint32_t ODR;            /**< Open Drain Select                       */
+  __IO uint32_t PUR;            /**< Pull-Up Select                          */
+  __IO uint32_t PDR;            /**< Pull-Down Select                        */
+  __IO uint32_t SLR;            /**< Slew Rate Control Select                */
+  __IO uint32_t DEN;            /**< Digital Enable                          */
+  __IO uint32_t LOCK;           /**< Lock                                    */
+  __IO uint32_t CR;             /**< Commit                                  */
+  __IO uint32_t AMSEL;          /**< Analog Mode Select                      */
+  __IO uint32_t PCTL;           /**< Port Control                            */
+  __IO uint32_t ADCCTL;         /**< ADC Control                             */
+  __IO uint32_t DMACTL;         /**< DMA Control                             */
+} GPIO_TypeDef;
+
+/**
+ * @brief General Purpose Timer
+ */
+typedef struct
+{
+  __IO uint32_t CFG;            /**< Configuration                           */
+  __IO uint32_t TAMR;           /**< Timer A Mode                            */
+  __IO uint32_t TBMR;           /**< Timer B Mode                            */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t SYNC;           /**< Synchronize                             */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t IMR;            /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __IO uint32_t TAILR;          /**< Timer A Interval Load                   */
+  __IO uint32_t TBILR;          /**< Timer B Interval Load                   */
+  __IO uint32_t TAMATCHR;       /**< Timer A Match                           */
+  __IO uint32_t TBMATCHR;       /**< Timer B Match                           */
+  __IO uint32_t TAPR;           /**< Timer A Prescale                        */
+  __IO uint32_t TBPR;           /**< Timer B Prescale                        */
+  __IO uint32_t TAPMR;          /**< Timer A Prescale Match                  */
+  __IO uint32_t TBPMR;          /**< Timer B Prescale Match                  */
+  __I  uint32_t TAR;            /**< Timer A                                 */
+  __I  uint32_t TBR;            /**< Timer B                                 */
+  __IO uint32_t TAV;            /**< Timer A Value                           */
+  __IO uint32_t TBV;            /**< Timer B Value                           */
+  __I  uint32_t RTCPD;          /**< RTC Predivide                           */
+  __I  uint32_t TAPS;           /**< Timer A Prescale Snapshot               */
+  __I  uint32_t TBPS;           /**< Timer B Prescale Snapshot               */
+  __I  uint32_t TAPV;           /**< Timer A Prescale Value                  */
+  __I  uint32_t TBPV;           /**< Timer B Prescale Value                  */
+  __I  uint32_t RESERVED1[981]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+} GPT_TypeDef;
+
+/**
+ * @brief Hibernation Module
+ */
+typedef struct
+{
+  __I  uint32_t RTCC;           /**< RTC Counter                             */
+  __IO uint32_t RTCM0;          /**< RTC Match 0                             */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t RTCLD;          /**< RTC Load                                */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __IO uint32_t IC;             /**< Interrupt Clear                         */
+  __IO uint32_t RTCT;           /**< RTC Trim                                */
+  __IO uint32_t RTCSS;          /**< RTC Sub Seconds                         */
+  __I  uint32_t RESERVED1[1];   /**< Reserved                                */
+  __IO uint32_t DATA;           /**< Data                                    */
+} HIB_TypeDef;
+
+/**
+ * @brief Inter-Integrated Circuit
+ */
+typedef struct
+{
+  __IO uint32_t MSA;            /**< Master Slave Address                    */
+  __IO uint32_t MCS;            /**< Master Control/Status                   */
+  __IO uint32_t MDR;            /**< Master Data                             */
+  __IO uint32_t MTPR;           /**< Master Timer Period                     */
+  __IO uint32_t MIMR;           /**< Master Interrupt Mask                   */
+  __I  uint32_t MRIS;           /**< Master Raw Interrupt Status             */
+  __IO uint32_t MMIS;           /**< Master Masked Interrupt Status          */
+  __O  uint32_t MICR;           /**< Master Interrupt Clear                  */
+  __IO uint32_t MCR;            /**< Master Configuration                    */
+  __IO uint32_t MCLKOCNT;       /**< Master Clock Low Timeout Count          */
+  __I  uint32_t RESERVED0;      /**< Reserved                                */
+  __I  uint32_t MBMON;          /**< Master Bus Monitor                      */
+  __IO uint32_t MCR2;           /**< Master Configuration 2                  */
+  __I  uint32_t RESERVED1[497]; /**< Reserved                                */
+  __IO uint32_t SOAR;           /**< Slave Own Address                       */
+  __IO uint32_t SCSR;           /**< Slave Control/Status                    */
+  __IO uint32_t SDR;            /**< Slave Data                              */
+  __IO uint32_t SIMR;           /**< Slave Interrupt Mask                    */
+  __I  uint32_t SRIS;           /**< Slave Raw Interrupt Status              */
+  __I  uint32_t SMIS;           /**< Slave Masked Interrupt Status           */
+  __O  uint32_t SICR;           /**< Slave Interrupt Clear                   */
+  __IO uint32_t SOAR2;          /**< Slave Own Address 2                     */
+  __IO uint32_t SACKCTL;        /**< Slave ACK Control                       */
+  __I  uint32_t RESERVED2[487]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __I  uint32_t PC;             /**< Peripheral Configuration                */
+} I2C_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t INTEN;          /**< Interrupt and Trigger Enable            */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+  __IO uint32_t LOAD;           /**< Load                                    */
+  __I  uint32_t COUNT;          /**< Counter                                 */
+  __IO uint32_t CMP[2];         /**< Compare A, B                            */
+  __IO uint32_t GEN[2];         /**< Generator A, B Control                  */
+  __IO uint32_t DBCTL;          /**< Dead-Band Control                       */
+  __IO uint32_t DBRISE;         /**< Dead-Band Rising-Edge Delay             */
+  __IO uint32_t DBFALL;         /**< Dead-Band Falling-Edge Delay            */
+  __IO uint32_t FLTSRC[2];      /**< Fault Source 0, 1                       */
+  __IO uint32_t MINFLTPER;      /**< Minimum Fault Period                    */
+} PWM_GENERATOR_T;
+
+/*
+ * @brief Pulse Width Modulator
+ */
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Master Control                          */
+  __IO uint32_t SYNC;           /**< Time Base Sync                          */
+  __IO uint32_t ENABLE;         /**< Output Enable                           */
+  __IO uint32_t INVERT;         /**< Output Inversion                        */
+  __IO uint32_t FAULT;          /**< Output Fault                            */
+  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+  __I  uint32_t STATUS;         /**< Status                                  */
+  __IO uint32_t FAULTVAL;       /**< Fault Condition Value                   */
+  __IO uint32_t ENUPD;          /**< Enable Update                           */
+  __I  uint32_t RESERVED0[5];   /**< Reserved                                */
+  __IO PWM_GENERATOR_T PWM[4];  /**< PWM Generator 0, 1, 2 and 3             */
+  __I  uint32_t RESERVED1[432]; /**< Reserved                                */
+  __IO uint32_t _0FLTSEN;       /**< Fault Pin Logic Sense                   */
+  __IO uint32_t _0FLTSTAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED2[29];  /**< Reserved                                */
+  __IO uint32_t _1FLTSEN;       /**< Fault Pin Logic Sense                   */
+  __IO uint32_t _1FLSTSAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED3[30];  /**< Reserved                                */
+  __IO uint32_t _2FLTSTAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED4[30];  /**< Reserved                                */
+  __IO uint32_t _3FLTSTAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED5[397]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+} PWM_TypeDef;
+
+/**
+ * @brief Quadrature Encoder Interface
+ */
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Control                                 */
+  __I  uint32_t STAT;           /**< Status                                  */
+  __IO uint32_t POS;            /**< Position                                */
+  __IO uint32_t MAXPOS;         /**< Maximum Position                        */
+  __IO uint32_t LOAD;           /**< Timer Load                              */
+  __I  uint32_t TIME;           /**< Timer                                   */
+  __I  uint32_t COUNT;          /**< Velocity Counter                        */
+  __I  uint32_t SPEED;          /**< Velocity                                */
+  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+} QEI_TypeDef;
+
+/**
+ * @brief Synchronous Serial Interface
+ */
+typedef struct
+{
+  __IO uint32_t CR0;            /**< Control 0                               */
+  __IO uint32_t CR1;            /**< Control 1                               */
+  __IO uint32_t DR;             /**< Data                                    */
+  __I  uint32_t SR;             /**< Status                                  */
+  __IO uint32_t CPSR;           /**< Clock Prescale                          */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __IO uint32_t DMACTL;         /**< DMA Control                             */
+  __I  uint32_t RESERVED1[1000];/**< Reserved                                */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} SSI_TypeDef;
+
+/** 
+ * @brief System Control
+ */
+typedef struct
+{
+  __I  uint32_t DID0;           /**< Device Identification 0                 */
+  __I  uint32_t DID1;           /**< Device Identification 1                 */
+  __I  uint32_t RESERVED0[10];  /**< Reserved                                */
+  __IO uint32_t PBORCTL;        /**< Brown-Out Reset Control                 */
+  __I  uint32_t RESERVED1[7];   /**< Reserved                                */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
+  __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
+  __IO uint32_t RESC;           /**< Reset Cause                             */
+  __IO uint32_t RCC;            /**< Run-Mode Clock Configuration            */
+  __I  uint32_t RESERVED2[2];   /**< Reserved                                */
+  __IO uint32_t GPIOHBCTL;      /**< GPIO High-Performance Bus Control       */
+  __IO uint32_t RCC2;           /**< Run-Mode Clock Configuration 2          */
+  __I  uint32_t RESERVED3[2];   /**< Reserved                                */
+  __IO uint32_t MOSCCTL;        /**< Main Oscillator Control                 */
+  __I  uint32_t RESERVED4[49];  /**< Reserved                                */
+  __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
+  __I  uint32_t RESERVED5[1];   /**< Reserved                                */
+  __I  uint32_t SYSPROP;        /**< System Properties                       */
+  __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
+  __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
+  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
+  __I  uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
+  __I  uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
+  __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
+  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
+  __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
+  __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
+  __I  uint32_t RESERVED8[9];   /**< Reserved                                */
+  __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
+  __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
+  __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
+  __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
+  __I  uint32_t RESERVED9[2];   /**< Reserved                                */
+  __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
+  __I  uint32_t RESERVED10[76]; /**< Reserved                                */
+  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
+  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
+  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
+  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
+  __I  uint32_t RESERVED11[1];  /**< Reserved                                */
+  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
+  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
+  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
+  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
+  __I  uint32_t RESERVED12[1];  /**< Reserved                                */
+  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
+  __I  uint32_t RESERVED13[2];  /**< Reserved                                */
+  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
+  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
+  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
+  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
+  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
+  __I  uint32_t RESERVED14[4];  /**< Reserved                                */
+  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
+  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
+  __I  uint32_t RESERVED15[104];/**< Reserved                                */
+  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
+  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
+  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
+  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
+  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
+  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
+  __IO uint32_t SRUART;         /**< UART Software Reset                     */
+  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
+  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
+  __I  uint32_t RESERVED17[1];  /**< Reserved                                */
+  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
+  __I  uint32_t RESERVED18[2];  /**< Reserved                                */
+  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
+  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
+  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
+  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
+  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
+  __I  uint32_t RESERVED19[4];  /**< Reserved                                */
+  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
+  __IO uint32_t SRWTIMER;       /**< Wide GPT Software Reset                 */
+  __I  uint32_t RESERVED20[40]; /**< Reserved                                */
+  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
+  __I  uint32_t RESERVED21[1];  /**< Reserved                                */
+  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
+  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
+  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED23[2];  /**< Reserved                                */
+  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
+  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
+  __IO uint32_t RCGCWTIMER;     /**< Wide GPT Run Mode Clock Gating Control  */
+  __I  uint32_t RESERVED25[40]; /**< Reserved                                */
+  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
+  __I  uint32_t RESERVED26[1];  /**< Reserved                                */
+  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED27[1];  /**< Reserved                                */
+  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED28[2];  /**< Reserved                                */
+  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED29[4];  /**< Reserved                                */
+  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
+  __IO uint32_t SCGCWTIMER;     /**< Wide GPT Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED30[40]; /**< Reserved                                */
+  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __I  uint32_t RESERVED31[1];  /**< Reserved                                */
+  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED32[1];  /**< Reserved                                */
+  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED33[2];  /**< Reserved                                */
+  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED34[4];  /**< Reserved                                */
+  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCWTIMER;     /**< Wide GPT Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __I  uint32_t RESERVED35[104];/**< Reserved                                */
+  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
+  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
+  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
+  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
+  __I  uint32_t RESERVED36[1];  /**< Reserved                                */
+  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
+  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
+  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
+  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
+  __I  uint32_t RESERVED37[1];  /**< Reserved                                */
+  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
+  __I  uint32_t RESERVED38[2];  /**< Reserved                                */
+  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
+  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
+  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
+  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
+  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
+  __I  uint32_t RESERVED39[4];  /**< Reserved                                */
+  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
+  __IO uint32_t PRWTIMER;       /**< Wide GPT Peripheral Ready               */
+} SYSCTL_TypeDef;
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter
+ */
+typedef struct
+{
+  __IO uint32_t DR;             /**< Data                                    */
+  union  {
+    __I  uint32_t RSR;          /**< Receive Status                          */
+    __O  uint32_t ECR;          /**< Error Clear                             */
+  };
+  __I  uint32_t RESERVED0[4];   /**< Reserved                                */
+  __I  uint32_t FR;             /**< Flag                                    */
+  __I  uint32_t RESERVED1[1];   /**< Reserved                                */
+  __IO uint32_t ILPR;           /**< IrDA Low-Power Register                 */
+  __IO uint32_t IBRD;           /**< Integer Baud-Rate Divisor               */
+  __IO uint32_t FBRD;           /**< Fractional Baud-Rate Divisor            */
+  __IO uint32_t LCRH;           /**< Line Control                            */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t IFLS;           /**< Interrupt FIFO Level Select             */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O uint32_t ICR;             /**< Interrupt Clear                         */
+  __IO uint32_t DMACTL;         /**< DMA Control                             */
+  __I  uint32_t RESERVED2[22];  /**< Reserved                                */
+  __IO uint32_t BIT9ADDR;       /**< 9-Bit Self Address                      */
+  __IO uint32_t BIT9AMASK;      /**< 9-Bit Self Address Mask                 */
+  __I  uint32_t RESERVED3[965]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} UART_TypeDef;
+
+/**
+ * @brief Micro Direct Memory Access
+ */
+typedef struct
+{
+  __IO uint32_t STAT;           /**< Status                                  */
+  __O  uint32_t CFG;            /**< Configuration                           */
+  __IO uint32_t CTLBASE;        /**< Channel Control Base Pointer            */
+  __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
+  __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
+  __O  uint32_t SWREQ;          /**< Channel Software Request                */
+  __IO uint32_t USEBURSTSET;    /**< Channel Useburst Set                    */
+  __O  uint32_t USEBURSTCLR;    /**< Channel Useburst Clear                  */
+  __IO uint32_t REQMASKSET;     /**< Channel Request Mask Set                */
+  __O  uint32_t REQMASKCLR;     /**< Channel Request Mask Clear              */
+  __IO uint32_t ENASET;         /**< Channel Enable Set                      */
+  __O  uint32_t ENACLR;         /**< Channel Enable Clear                    */
+  __IO uint32_t ALTSET;         /**< Channel Primary Alternate Set           */
+  __O  uint32_t ALTCLR;         /**< Channel Primary Alternate Clear         */
+  __IO uint32_t PRIOSET;        /**< Channel Priority Set                    */
+  __O  uint32_t PRIOCLR;        /**< Channel Priority Clear                  */
+  __I  uint32_t RESERVED0[3];   /**< Reserved                                */
+  __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
+  __I  uint32_t RESERVED1[300]; /**< Reserved                                */
+  __IO uint32_t CHASGN;         /**< Channel Assignment                      */
+  __IO uint32_t CHIS;           /**< Channel Interrupt Status                */
+  __I  uint32_t RESERVED2[2];   /**< Reserved                                */
+  __IO uint32_t CHMAP0;         /**< Channel Map Select 0                    */
+  __IO uint32_t CHMAP1;         /**< Channel Map Select 1                    */
+  __IO uint32_t CHMAP2;         /**< Channel Map Select 2                    */
+  __IO uint32_t CHMAP3;         /**< Channel Map Select 3                    */
+} UDMA_TypeDef;
+
+// USB
+
+/**
+ * @brief Watchdog Timer
+ */
+typedef struct
+{
+  __IO uint32_t LOAD;           /**< Load                                    */
+  __I  uint32_t VALUE;          /**< Value                                   */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __I  uint32_t RESERVED0[256]; /**< Reserved                                */
+  __IO uint32_t TEST;           /**< Test                                    */
+  __I  uint32_t RESERVED1[505]; /**< Reserved                                */
+  __IO uint32_t LOCK;           /**< Lock                                    */
+} WATCHDOG_TypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup Peripheral_memorymap
+ * @{
+ */
+
+#define SYSCTL_BASE 0x400FE000
+#define HIB_BASE    0x400FC000
+#define FLASH_BASE  0x400FD000
+#define EEPROM_BASE 0x400AF000
+#define UDMA_BASE   0x400FF000
+#define GPIOA_BASE  0x40004000
+#define GPIOB_BASE  0x40005000
+#define GPIOC_BASE  0x40006000
+#define GPIOD_BASE  0x40007000
+#define GPIOE_BASE  0x40024000
+#define GPIOF_BASE  0x40025000
+#define GPT0_BASE   0x40030000
+#define GPT1_BASE   0x40031000
+#define GPT2_BASE   0x40032000
+#define GPT3_BASE   0x40033000
+#define GPT4_BASE   0x40034000
+#define GPT5_BASE   0x40035000
+#define WGPT0_BASE  0x40036000
+#define WGPT1_BASE  0x40037000
+#define WGPT2_BASE  0x4004C000
+#define WGPT3_BASE  0x4004D000
+#define WGPT4_BASE  0x4004E000
+#define WGPT5_BASE  0x4004F000
+#define WDT0_BASE   0x40000000
+#define WDT1_BASE   0x40001000
+#define ADC0_BASE   0x40038000
+#define ADC1_BASE   0x40039000
+#define UART0_BASE  0x4000C000
+#define UART1_BASE  0x4000D000
+#define UART2_BASE  0x4000E000
+#define UART3_BASE  0x4000F000
+#define UART4_BASE  0x40010000
+#define UART5_BASE  0x40011000
+#define UART6_BASE  0x40012000
+#define UART7_BASE  0x40013000
+#define SSI0_BASE   0x40008000
+#define SSI1_BASE   0x40009000
+#define SSI2_BASE   0x4000A000
+#define SSI3_BASE   0x4000B000
+#define I2C0_BASE   0x40020000
+#define I2C1_BASE   0x40021000
+#define I2C2_BASE   0x40022000
+#define I2C3_BASE   0x40023000
+#define CAN0_BASE   0x40040000
+#define CAN1_BASE   0x40041000
+// usb
+#define AC_BASE     0x4003C000
+#define PWM0_BASE   0x40028000
+#define PWM1_BASE   0x40029000
+#define QEI0_BASE   0x4002C000
+#define QEI1_BASE   0x4002D000
+
+/**
+ * @}
+ */
+
+/** 
+ * @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define SYSCTL  ((SYSCTL_TypeDef *) SYSCTL_BASE)
+#define HIB     ((HIB_TypeDef *)    HIB_BASE)
+#define FLASH   ((FLASH_TypeDef *)  FLASH_BASE)
+#define EEPROM  ((EEPROM_TypeDef *) EEPROM_BASE)
+#define UDMA    ((UDMA_TypeDef *)   UDMA_BASE)										
+#define GPIOA   ((GPIO_TypeDef *)   GPIOA_BASE)
+#define GPIOB   ((GPIO_TypeDef *)   GPIOB_BASE)
+#define GPIOC   ((GPIO_TypeDef *)   GPIOC_BASE)
+#define GPIOD   ((GPIO_TypeDef *)   GPIOD_BASE)
+#define GPIOE   ((GPIO_TypeDef *)   GPIOE_BASE)
+#define GPIOF   ((GPIO_TypeDef *)   GPIOF_BASE)
+#define GPT0    ((GPT_TypeDef *)    GPT0_BASE)
+#define GPT1    ((GPT_TypeDef *)    GPT1_BASE)
+#define GPT2    ((GPT_TypeDef *)    GPT2_BASE)
+#define GPT3    ((GPT_TypeDef *)    GPT3_BASE)
+#define GPT4    ((GPT_TypeDef *)    GPT4_BASE)
+#define GPT5    ((GPT_TypeDef *)    GPT5_BASE)
+#define WGPT0   ((GPT_TypeDef *)    WGPT0_BASE)
+#define WGPT1   ((GPT_TypeDef *)    WGPT1_BASE)
+#define WGPT2   ((GPT_TypeDef *)    WGPT2_BASE)
+#define WGPT3   ((GPT_TypeDef *)    WGPT3_BASE)
+#define WGPT4   ((GPT_TypeDef *)    WGPT4_BASE)
+#define WGPT5   ((GPT_TypeDef *)    WGPT5_BASE)
+#define ADC0    ((ADC_TypeDef*)     ADC0_BASE)
+#define ADC1    ((ADC_TypeDef*)     ADC1_BASE)
+#define UART0   ((UART_TypeDef *)   UART0_BASE)
+#define UART1   ((UART_TypeDef *)   UART1_BASE)
+#define UART2   ((UART_TypeDef *)   UART2_BASE)
+#define UART3   ((UART_TypeDef *)   UART3_BASE)
+#define UART4   ((UART_TypeDef *)   UART4_BASE)
+#define UART5   ((UART_TypeDef *)   UART5_BASE)
+#define UART6   ((UART_TypeDef *)   UART6_BASE)
+#define UART7   ((UART_TypeDef *)   UART7_BASE)
+#define SSI0    ((SSI_TypeDef *)    SSI0_BASE)
+#define SSI1    ((SSI_TypeDef *)    SSI1_BASE)
+#define SSI2    ((SSI_TypeDef *)    SSI2_BASE)
+#define SSI3    ((SSI_TypeDef *)    SSI3_BASE)
+#define I2C0    ((I2C_TypeDef *)    I2C0_BASE)
+#define I2C1    ((I2C_TypeDef *)    I2C1_BASE)
+#define I2C2    ((I2C_TypeDef *)    I2C2_BASE)
+#define I2C3    ((I2C_TypeDef *)    I2C3_BASE)
+#define CAN0    ((CAN_TypeDef *)    CAN0_BASE)
+#define CAN1    ((CAN_TypeDef *)    CAN1_BASE)
+// usb
+#define AC      ((AC_TypeDef *)     AC_BASE)
+#define PWM0    ((PWM_TypeDef *)    PWM0_BASE)
+#define PWM1    ((PWM_TypeDef *)    PWM1_BASE)
+#define QEI0    ((QEI_TypeDef *)    QEI0_BASE)
+#define QEI1    ((QEI_TypeDef *)    QEI1_BASE)
+
+/**
+ * @}
+ */
+
+#endif /* __TM4C123x_H */
+
+/**
+ * @}
+ */
+ 
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
new file mode 100644
index 0000000..4f2a968
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c
@@ -0,0 +1,152 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/TM4C129x/hal_lld.c
+ * @brief   TM4C129x HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void)
+{
+}
+
+/**
+ * @brief   TM4C129x clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h and 
+ *          @p mcuconf.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void tiva_clock_init(void)
+{
+  uint32_t moscctl, rsclkcfg;
+
+  /*
+   * 1. Once POR has completed, the PIOSC is acting as the system clock.
+   */
+
+  /*
+   * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register.
+   */
+  moscctl = SYSCTL->MOSCCTL;
+  moscctl &= ~MOSCCTL_NOXTAL;
+
+  /*
+   * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required,
+   * clear the PWRDN bit and wait for the MOSCPUPRIS bit to be set in the Raw Interrupt Status
+   * (RIS), indicating MOSC crystal mode is ready.
+   */
+#if TIVA_MOSC_SINGLE_ENDED
+  SYSCTL->MOSCCTL = moscctl;
+#else
+  moscctl &= ~MOSCCTL_PWRDN;
+  SYSCTL->MOSCCTL = moscctl;
+
+  while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS));
+#endif
+
+  /*
+   * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0.
+   */
+  rsclkcfg = SYSCTL->RSCLKCFG;
+
+  rsclkcfg |= TIVA_RSCLKCFG_OSCSRC;
+
+  /*
+   * 5. If the application also requires the MOSC to be the deep-sleep clock source, then program the
+   * DSOSCSRC field in the DSCLKCFG register to 0x3.
+   */
+
+  /*
+   * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to
+   * the configure the desired VCO frequency setting.
+   */
+  SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1
+  SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR;
+
+  /*
+   * 7. Write the MEMTIM0 register to correspond to the new system clock setting.
+   */
+  SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1);
+
+  /*
+   * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point
+   * (or that a timeout period has passed and lock has failed, in which case an error condition exists
+   * and this sequence is abandoned and error processing is initiated).
+   */
+  while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK);
+
+  /*
+   * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU
+   * bit.
+   */
+
+  rsclkcfg = SYSCTL->RSCLKCFG;
+
+  rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24));
+
+  //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20));
+
+  rsclkcfg |= RSCLKCFG_MEMTIMU;
+
+  // set new configuration
+  SYSCTL->RSCLKCFG = rsclkcfg;
+
+#if HAL_USE_PWM
+#if TIVA_PWM_USE_PWM0
+  PWM0->CC = TIVA_PWM_FIELDS;
+#endif
+#endif
+}
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h
new file mode 100644
index 0000000..a0e769b
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h
@@ -0,0 +1,381 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TIVA/TM4C129x/hal_lld.h
+ * @brief   TM4C129x HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - TODO: add required macros
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "tiva_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+ 
+#define PLATFORM_NAME           "Tiva C Series TM4C129x"
+
+/**
+ * @}
+ */
+
+/**
+ * @name    RIS register bits definitions
+ * @{
+ */
+
+#define SYSCTL_RIS_PLLLRIS	            (1 << 6)
+#define SYSCTL_RIS_MOSCPUPRIS           (1 << 8)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    MOSCCTL register bits definitions
+ * @{
+ */
+
+#define MOSCCTL_CVAL                (1 << 0)
+#define MOSCCTL_MOSCIM              (1 << 1)
+#define MOSCCTL_NOXTAL              (1 << 2)
+#define MOSCCTL_PWRDN               (1 << 3)
+#define MOSCCTL_OSCRNG              (1 << 4)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    RSCLKCFG register bits definitions
+ * @{
+ */
+
+#define RSCLKCFG_PSYSDIV_bm         (0xfffff << 0)
+#define RSCLKCFG_OSYSDIV_bm         (0xfffff << 10
+
+#define RSCLKCFG_OSCSRC_bm          (0xff << 20)
+#define RSCLKCFG_OSCSRC_PIOSC       (0 << 20)
+#define RSCLKCFG_OSCSRC_LFIOSC      (0x02 << 20)
+#define RSCLKCFG_OSCSRC_MOSC        (0x03 << 20)
+#define RSCLKCFG_OSCSRC_RTCOSC      (0x04 << 20)
+
+#define RSCLKCFG_PLLSRC_bm          (0xff << 24)
+#define RSCLKCFG_PLLSRC_PIOSC       (0 << 24)
+#define RSCLKCFG_PLLSRC_MOSC        (0x03 << 24)
+
+#define RSCLKCFG_USEPLL             (1 << 28)
+
+#define RSCLKCFG_ACG                (1 << 29)
+
+#define RSCLKCFG_NEWFREQ            (1 << 30)
+
+#define RSCLKCFG_MEMTIMU            (1 << 31)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    PLLFREQ0 register bits definitions
+ * The PLL frequency can be calculated using the following equation:
+ * fVCO = (fIN * MDIV)
+ * where
+ * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1)
+ * MDIV = MINT + (MFRAC / 1024)
+ * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC
+ * should be programmed to 0x0.
+ * @{
+ */
+
+#define PLLFREQ0_MINT_bm            (0xfffff << 0)
+#define PLLFREQ0_MFRAC_bm           (0xfffff << 10)
+#define PLLFREQ0_PLLPWR             (1 << 23)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    PLLFREQ1 register bits definitions
+ * @{
+ */
+
+#define PLLFREQ1_N_bm               (0x7ff << 0)
+#define PLLFREQ1_Q_bm               (0x7ff << 8)
+
+/**
+ * @}
+ */
+
+/**
+ * @name    MEMTIM0 register bits definitions
+ * @{
+ */
+
+#define MEMTIM0_FWS_bm              (0xff << 0)
+#define MEMTIM0_FWS_0               (0x00 << 0)
+#define MEMTIM0_FWS_1               (0x01 << 0)
+#define MEMTIM0_FWS_2               (0x02 << 0)
+#define MEMTIM0_FWS_3               (0x03 << 0)
+#define MEMTIM0_FWS_4               (0x04 << 0)
+#define MEMTIM0_FWS_5               (0x05 << 0)
+#define MEMTIM0_FWS_6               (0x06 << 0)
+#define MEMTIM0_FWS_7               (0x07 << 0)
+
+#define MEMTIM0_FBCE                (1 << 5)
+
+#define MEMTIM0_FBCHT_bm            (0xff << 6)
+#define MEMTIM0_FBCHT_0_5           (0x00 << 6)
+#define MEMTIM0_FBCHT_1             (0x01 << 6)
+#define MEMTIM0_FBCHT_1_5           (0x02 << 6)
+#define MEMTIM0_FBCHT_2             (0x03 << 6)
+#define MEMTIM0_FBCHT_2_5           (0x04 << 6)
+#define MEMTIM0_FBCHT_3             (0x05 << 6)
+#define MEMTIM0_FBCHT_3_5           (0x06 << 6)
+#define MEMTIM0_FBCHT_4             (0x07 << 6)
+#define MEMTIM0_FBCHT_4_5           (0x08 << 6)
+
+#define MEMTIM0_EWS_bm              (0xff << 16)
+#define MEMTIM0_EWS_0               (0x00 << 16)
+#define MEMTIM0_EWS_1               (0x01 << 16)
+#define MEMTIM0_EWS_2               (0x02 << 16)
+#define MEMTIM0_EWS_3               (0x03 << 16)
+#define MEMTIM0_EWS_4               (0x04 << 16)
+#define MEMTIM0_EWS_5               (0x05 << 16)
+#define MEMTIM0_EWS_6               (0x06 << 16)
+#define MEMTIM0_EWS_7               (0x07 << 16)
+
+#define MEMTIM0_EBCE                (1 << 21)
+
+#define MEMTIM0_EBCHT_bm            (0xff << 22)
+#define MEMTIM0_EBCHT_0_5           (0x00 << 22)
+#define MEMTIM0_EBCHT_1             (0x01 << 22)
+#define MEMTIM0_EBCHT_1_5           (0x02 << 22)
+#define MEMTIM0_EBCHT_2             (0x03 << 22)
+#define MEMTIM0_EBCHT_2_5           (0x04 << 22)
+#define MEMTIM0_EBCHT_3             (0x05 << 22)
+#define MEMTIM0_EBCHT_3_5           (0x06 << 22)
+#define MEMTIM0_EBCHT_4             (0x07 << 22)
+#define MEMTIM0_EBCHT_4_5           (0x08 << 22)
+
+// XXX: what is this?
+#define MEMTIM0_MB1          0x00100010  // MB1 = Must be one
+
+/**
+ * @}
+ */
+
+/**
+ * @name    PLLSTAT register bits definitions
+ * @{
+ */
+
+#define PLLSTAT_LOCK                (1 << 0)
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+#if !defined(TIVA_MOSC_SINGLE_ENDED)
+#define TIVA_MOSC_SINGLE_ENDED          FALSE
+#endif
+
+#if !defined(TIVA_RSCLKCFG_OSCSRC)
+#define TIVA_RSCLKCFG_OSCSRC            RSCLKCFG_OSCSRC_MOSC
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(TM4C129x_MCUCONF)
+#error "Using a wrong mcuconf.h file, TM4C129x_MCUCONF not defined"
+#endif
+
+/*
+ * Oscillator-related checks.
+ */
+#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) &&                       \
+    !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) &&                      \
+    !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) &&                        \
+    !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC)
+#error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined"
+#endif
+
+#if TIVA_XTAL_VALUE == 4000000
+#define TIVA_XTAL_              (0x06 << 6)
+#elif TIVA_XTAL_VALUE == 4096000
+#define TIVA_XTAL_              (0x07 << 6)
+#elif TIVA_XTAL_VALUE == 4915200
+#define TIVA_XTAL_              (0x08 << 6)
+#elif TIVA_XTAL_VALUE == 5000000
+#define TIVA_XTAL_              (0x09 << 6)
+#elif TIVA_XTAL_VALUE == 5120000
+#define TIVA_XTAL_              (0x0a << 6)
+#elif TIVA_XTAL_VALUE == 6000000
+#define TIVA_XTAL_              (0x0b << 6)
+#elif TIVA_XTAL_VALUE == 6144000
+#define TIVA_XTAL_              (0x0c << 6)
+#elif TIVA_XTAL_VALUE == 7372800
+#define TIVA_XTAL_              (0x0d << 6)
+#elif TIVA_XTAL_VALUE == 8000000
+#define TIVA_XTAL_              (0x0e << 6)
+#elif TIVA_XTAL_VALUE == 8192000
+#define TIVA_XTAL_              (0x0f << 6)
+#elif TIVA_XTAL_VALUE == 10000000
+#define TIVA_XTAL_              (0x10 << 6)
+#elif TIVA_XTAL_VALUE == 12000000
+#define TIVA_XTAL_              (0x11 << 6)
+#elif TIVA_XTAL_VALUE == 12288000
+#define TIVA_XTAL_              (0x12 << 6)
+#elif TIVA_XTAL_VALUE == 13560000
+#define TIVA_XTAL_              (0x13 << 6)
+#elif TIVA_XTAL_VALUE == 14318180
+#define TIVA_XTAL_              (0x14 << 6)
+#elif TIVA_XTAL_VALUE == 16000000
+#define TIVA_XTAL_              (0x15 << 6)
+#elif TIVA_XTAL_VALUE == 16384000
+#define TIVA_XTAL_              (0x16 << 6)
+#elif TIVA_XTAL_VALUE == 18000000
+#define TIVA_XTAL_              (0x17 << 6)
+#elif TIVA_XTAL_VALUE == 20000000
+#define TIVA_XTAL_              (0x18 << 6)
+#elif TIVA_XTAL_VALUE == 24000000
+#define TIVA_XTAL_              (0x19 << 6)
+#elif TIVA_XTAL_VALUE == 25000000
+#define TIVA_XTAL_              (0x1a << 6)
+#else
+#error "Invalid value for TIVA_XTAL_VALUE defined"
+#endif
+
+/*
+#if TIVA_MOSC_ENABLE == TRUE
+#define TIVA_MOSCDIS            (0 << 0)
+#define TIVA_XTAL               TIVA_XTAL_
+#elif TIVA_MOSC_ENABLE == FALSE
+#define TIVA_MOSCDIS            (1 << 0)
+#define TIVA_XTAL               0
+#else
+#error "Invalid value for TIVA_MOSC_ENABLE defined"
+#endif
+
+#if TIVA_DIV400_ENABLE == TRUE
+#define TIVA_DIV400             (1 << 30)
+#elif TIVA_DIV400_ENABLE == FALSE
+#define TIVA_DIV400             (0 << 30)
+#else
+#error "Invalid value for TIVA_DIV400_ENABLE defined"
+#endif
+
+#if (TIVA_SYSDIV_VALUE >= 0x02) && (TIVA_SYSDIV_VALUE <= 0x3f)
+#define TIVA_SYSDIV             (TIVA_SYSDIV_VALUE << 23)
+#define TIVA_SYSDIV2            (TIVA_SYSDIV_VALUE << 23)
+#else
+#error "Invalid value for TIVA_SYSDIV_VALUE defined"
+#endif
+
+#if TIVA_USESYSDIV_ENABLE == TRUE
+#define TIVA_USESYSDIV          (1 << 22)
+#elif TIVA_USESYSDIV_ENABLE == FALSE
+#define TIVA_USESYSDIV          (0 << 22)
+#else
+#error "Invalid value for TIVA_USESYSDIV_ENABLE defined"
+#endif
+
+#if TIVA_SYSDIV2LSB_ENABLE == TRUE
+#define TIVA_SYSDIV2LSB         (1 << 22)
+#elif TIVA_SYSDIV2LSB_ENABLE == FALSE
+#define TIVA_SYSDIV2LSB         (0 << 22)
+#else
+#error "Invalid value for TIVA_SYSDIV2LSB_ENABLE defined"
+#endif
+
+#if TIVA_BYPASS_ENABLE == TRUE
+#define TIVA_SRC                16000000
+#define TIVA_BYPASS             (1 << 11)
+#elif TIVA_BYPASS_ENABLE == FALSE
+#define TIVA_SRC                (200000000 + ((TIVA_DIV400 >> 30) * 200000000))
+#define TIVA_BYPASS             (0 << 11)
+#else
+#error "Invalid value for TIVA_BYPASS_ENABLE defined"
+#endif
+
+#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE)
+#error "Main Oscillator selected but not enabled"
+#endif
+*/
+/*
+ * System Clock calculation
+ * TODO: dynamic TIVA_SYSCLK value
+ */
+#define TIVA_SYSCLK             120000000
+
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC && \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(TIVA_ST_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SysTick"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "tiva_isr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void tiva_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk
new file mode 100644
index 0000000..83331e0
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/platform.mk
@@ -0,0 +1,11 @@
+# List of all the TM4C129x platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x \
+              ${CHIBIOS}/community/os/hal/ports/TIVA/LLD
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
new file mode 100644
index 0000000..b995c4f
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h
@@ -0,0 +1,569 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TM4C129x/tiva_isr.h
+ * @brief   TM4C129x ISR remapper driver header.
+ *
+ * @addtogroup TM4C129x_ISR
+ * @{
+ */
+
+#ifndef _TIVA_ISR_H_
+#define _TIVA_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    ISR names and numbers remapping
+ * @{
+ */
+
+/* GPIO units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\
+  || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\
+  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+#define TIVA_GPIOG_HANDLER                  VectorBC
+#define TIVA_GPIOH_HANDLER                  VectorC0
+#define TIVA_GPIOJ_HANDLER                  Vector10C
+#define TIVA_GPIOK_HANDLER                  Vector110
+#define TIVA_GPIOL_HANDLER                  Vector114
+#define TIVA_GPIOM_HANDLER                  Vector160
+#define TIVA_GPION_HANDLER                  Vector164
+#define TIVA_GPIOP0_HANDLER                 Vector170
+#define TIVA_GPIOP1_HANDLER                 Vector174
+#define TIVA_GPIOP2_HANDLER                 Vector178
+#define TIVA_GPIOP3_HANDLER                 Vector17C
+#define TIVA_GPIOP4_HANDLER                 Vector180
+#define TIVA_GPIOP5_HANDLER                 Vector184
+#define TIVA_GPIOP6_HANDLER                 Vector188
+#define TIVA_GPIOP7_HANDLER                 Vector18C
+#define TIVA_GPIOQ0_HANDLER                 Vector190
+#define TIVA_GPIOQ1_HANDLER                 Vector194
+#define TIVA_GPIOQ2_HANDLER                 Vector198
+#define TIVA_GPIOQ3_HANDLER                 Vector19C
+#define TIVA_GPIOQ4_HANDLER                 Vector1A0
+#define TIVA_GPIOQ5_HANDLER                 Vector1A4
+#define TIVA_GPIOQ6_HANDLER                 Vector1A8
+#define TIVA_GPIOQ7_HANDLER                 Vector1AC
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#define TIVA_GPIOG_NUMBER                   31
+#define TIVA_GPIOH_NUMBER                   32
+#define TIVA_GPIOJ_NUMBER                   51
+#define TIVA_GPIOK_NUMBER                   52
+#define TIVA_GPIOL_NUMBER                   53
+#define TIVA_GPIOM_NUMBER                   72
+#define TIVA_GPION_NUMBER                   73
+#define TIVA_GPIOP0_NUMBER                  76
+#define TIVA_GPIOP1_NUMBER                  77
+#define TIVA_GPIOP2_NUMBER                  78
+#define TIVA_GPIOP3_NUMBER                  79
+#define TIVA_GPIOP4_NUMBER                  80
+#define TIVA_GPIOP5_NUMBER                  81
+#define TIVA_GPIOP6_NUMBER                  82
+#define TIVA_GPIOP7_NUMBER                  83
+#define TIVA_GPIOQ0_NUMBER                  84
+#define TIVA_GPIOQ1_NUMBER                  85
+#define TIVA_GPIOQ2_NUMBER                  86
+#define TIVA_GPIOQ3_NUMBER                  87
+#define TIVA_GPIOQ4_NUMBER                  88
+#define TIVA_GPIOQ5_NUMBER                  89
+#define TIVA_GPIOQ6_NUMBER                  90
+#define TIVA_GPIOQ7_NUMBER                  91
+#endif
+#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\
+  || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\
+  || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\
+  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_GPIOA_HANDLER                  Vector40
+#define TIVA_GPIOB_HANDLER                  Vector44
+#define TIVA_GPIOC_HANDLER                  Vector48
+#define TIVA_GPIOD_HANDLER                  Vector4C
+#define TIVA_GPIOE_HANDLER                  Vector50
+#define TIVA_GPIOF_HANDLER                  VectorB8
+#define TIVA_GPIOG_HANDLER                  VectorBC
+#define TIVA_GPIOH_HANDLER                  VectorC0
+#define TIVA_GPIOJ_HANDLER                  Vector10C
+#define TIVA_GPIOK_HANDLER                  Vector110
+#define TIVA_GPIOL_HANDLER                  Vector114
+#define TIVA_GPIOM_HANDLER                  Vector160
+#define TIVA_GPION_HANDLER                  Vector164
+#define TIVA_GPIOP0_HANDLER                 Vector170
+#define TIVA_GPIOP1_HANDLER                 Vector174
+#define TIVA_GPIOP2_HANDLER                 Vector178
+#define TIVA_GPIOP3_HANDLER                 Vector17C
+#define TIVA_GPIOP4_HANDLER                 Vector180
+#define TIVA_GPIOP5_HANDLER                 Vector184
+#define TIVA_GPIOP6_HANDLER                 Vector188
+#define TIVA_GPIOP7_HANDLER                 Vector18C
+#define TIVA_GPIOQ0_HANDLER                 Vector190
+#define TIVA_GPIOQ1_HANDLER                 Vector194
+#define TIVA_GPIOQ2_HANDLER                 Vector198
+#define TIVA_GPIOQ3_HANDLER                 Vector19C
+#define TIVA_GPIOQ4_HANDLER                 Vector1A0
+#define TIVA_GPIOQ5_HANDLER                 Vector1A4
+#define TIVA_GPIOQ6_HANDLER                 Vector1A8
+#define TIVA_GPIOQ7_HANDLER                 Vector1AC
+#define TIVA_GPIOR_HANDLER                  Vector1B0
+#define TIVA_GPIOS_HANDLER                  Vector1B4
+#define TIVA_GPIOT_HANDLER                  Vector1FC
+
+#define TIVA_GPIOA_NUMBER                   0
+#define TIVA_GPIOB_NUMBER                   1
+#define TIVA_GPIOC_NUMBER                   2
+#define TIVA_GPIOD_NUMBER                   3
+#define TIVA_GPIOE_NUMBER                   4
+#define TIVA_GPIOF_NUMBER                   30
+#define TIVA_GPIOG_NUMBER                   31
+#define TIVA_GPIOH_NUMBER                   32
+#define TIVA_GPIOJ_NUMBER                   51
+#define TIVA_GPIOK_NUMBER                   52
+#define TIVA_GPIOL_NUMBER                   53
+#define TIVA_GPIOM_NUMBER                   72
+#define TIVA_GPION_NUMBER                   73
+#define TIVA_GPIOP0_NUMBER                  76
+#define TIVA_GPIOP1_NUMBER                  77
+#define TIVA_GPIOP2_NUMBER                  78
+#define TIVA_GPIOP3_NUMBER                  79
+#define TIVA_GPIOP4_NUMBER                  80
+#define TIVA_GPIOP5_NUMBER                  81
+#define TIVA_GPIOP6_NUMBER                  82
+#define TIVA_GPIOP7_NUMBER                  83
+#define TIVA_GPIOQ0_NUMBER                  84
+#define TIVA_GPIOQ1_NUMBER                  85
+#define TIVA_GPIOQ2_NUMBER                  86
+#define TIVA_GPIOQ3_NUMBER                  87
+#define TIVA_GPIOQ4_NUMBER                  88
+#define TIVA_GPIOQ5_NUMBER                  89
+#define TIVA_GPIOQ6_NUMBER                  90
+#define TIVA_GPIOQ7_NUMBER                  91
+#define TIVA_GPIOR_NUMBER                   92
+#define TIVA_GPIOS_NUMBER                   93
+#define TIVA_GPIOT_NUMBER                   111
+#endif
+
+/* EPI units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_EPI0_HANDLER                   Vector108
+
+#define TIVA_EPI0_NUMBER                    50
+#endif
+
+/* CRC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+/* CRC has no interrupts.*/
+#endif
+
+/* AES Accelerator units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \
+  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+  || defined(TM4C129XNCZAD)
+#define TIVA_AES_HANDLER                    Vector1BC
+
+#define TIVA_AES_NUMBER                     95
+#endif
+
+/* DES Accelerator units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+  || defined(TM4C129XNCZAD)
+#define TIVA_DES_HANDLER                    Vector1C0
+
+#define TIVA_DES_NUMBER                     51
+#endif
+
+/* SHA/MD5 Accelerator units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+  || defined(TM4C129XNCZAD)
+#define TIVA_SHA_MD5_HANDLER                Vector1B8
+
+#define TIVA_SHA_MD5_NUMBER                 94
+#endif
+
+/* GPT units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_GPT0A_HANDLER                   Vector8C
+#define TIVA_GPT0B_HANDLER                   Vector90
+#define TIVA_GPT1A_HANDLER                   Vector94
+#define TIVA_GPT1B_HANDLER                   Vector98
+#define TIVA_GPT2A_HANDLER                   Vector9C
+#define TIVA_GPT2B_HANDLER                   VectorA0
+#define TIVA_GPT3A_HANDLER                   VectorCC
+#define TIVA_GPT3B_HANDLER                   VectorD0
+#define TIVA_GPT4A_HANDLER                   Vector13C
+#define TIVA_GPT4B_HANDLER                   Vector140
+#define TIVA_GPT5A_HANDLER                   Vector144
+#define TIVA_GPT5B_HANDLER                   Vector148
+#define TIVA_GPT6A_HANDLER                   Vector1C8
+#define TIVA_GPT6B_HANDLER                   Vector1CC
+#define TIVA_GPT7A_HANDLER                   Vector1D0
+#define TIVA_GPT7B_HANDLER                   Vector1D4
+
+#define TIVA_GPT0A_NUMBER                    19
+#define TIVA_GPT0B_NUMBER                    20
+#define TIVA_GPT1A_NUMBER                    21
+#define TIVA_GPT1B_NUMBER                    22
+#define TIVA_GPT2A_NUMBER                    23
+#define TIVA_GPT2B_NUMBER                    24
+#define TIVA_GPT3A_NUMBER                    35
+#define TIVA_GPT3B_NUMBER                    36
+#define TIVA_GPT4A_NUMBER                    63
+#define TIVA_GPT4B_NUMBER                    64
+#define TIVA_GPT5A_NUMBER                    65
+#define TIVA_GPT5B_NUMBER                    66
+#define TIVA_GPT6A_NUMBER                    98
+#define TIVA_GPT6B_NUMBER                    99
+#define TIVA_GPT7A_NUMBER                    100
+#define TIVA_GPT7B_NUMBER                    101
+#endif
+
+/* WDT units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_WDT_HANDLER                    Vector88
+
+#define TIVA_WDT_NUMBER                     18
+#endif
+
+/* ADC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_ADC0_SEQ0_HANDLER              Vector78
+#define TIVA_ADC0_SEQ1_HANDLER              Vector7C
+#define TIVA_ADC0_SEQ2_HANDLER              Vector80
+#define TIVA_ADC0_SEQ3_HANDLER              Vector84
+#define TIVA_ADC1_SEQ0_HANDLER              VectorF8
+#define TIVA_ADC1_SEQ1_HANDLER              VectorFC
+#define TIVA_ADC1_SEQ2_HANDLER              Vector100
+#define TIVA_ADC1_SEQ3_HANDLER              Vector104
+
+#define TIVA_ADC0_SEQ0_NUMBER               14
+#define TIVA_ADC0_SEQ1_NUMBER               15
+#define TIVA_ADC0_SEQ2_NUMBER               16
+#define TIVA_ADC0_SEQ3_NUMBER               17
+#define TIVA_ADC1_SEQ0_NUMBER               46
+#define TIVA_ADC1_SEQ1_NUMBER               47
+#define TIVA_ADC1_SEQ2_NUMBER               48
+#define TIVA_ADC1_SEQ3_NUMBER               49
+#endif
+
+/* UART units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_UART0_HANDLER                  Vector54
+#define TIVA_UART1_HANDLER                  Vector58
+#define TIVA_UART2_HANDLER                  VectorC4
+#define TIVA_UART3_HANDLER                  Vector120
+#define TIVA_UART4_HANDLER                  Vector124
+#define TIVA_UART5_HANDLER                  Vector128
+#define TIVA_UART6_HANDLER                  Vector12C
+#define TIVA_UART7_HANDLER                  Vector130
+
+#define TIVA_UART0_NUMBER                   5
+#define TIVA_UART1_NUMBER                   6
+#define TIVA_UART2_NUMBER                   33
+#define TIVA_UART3_NUMBER                   56
+#define TIVA_UART4_NUMBER                   57
+#define TIVA_UART5_NUMBER                   58
+#define TIVA_UART6_NUMBER                   59
+#define TIVA_UART7_NUMBER                   60
+#endif
+
+/* QSSI units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_QSSI0_HANDLER                  Vector5C
+#define TIVA_QSSI1_HANDLER                  VectorC8
+#define TIVA_QSSI2_HANDLER                  Vector118
+#define TIVA_QSSI3_HANDLER                  Vector11C
+
+#define TIVA_QSSI0_NUMBER                   7
+#define TIVA_QSSI1_NUMBER                   34
+#define TIVA_QSSI2_NUMBER                   54
+#define TIVA_QSSI3_NUMBER                   55
+#endif
+
+/* I2C units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_I2C0_HANDLER                   Vector60
+#define TIVA_I2C1_HANDLER                   VectorD4
+#define TIVA_I2C2_HANDLER                   Vector134
+#define TIVA_I2C3_HANDLER                   Vector138
+#define TIVA_I2C4_HANDLER                   Vector158
+#define TIVA_I2C5_HANDLER                   Vector15C
+#define TIVA_I2C6_HANDLER                   Vector1D8
+#define TIVA_I2C7_HANDLER                   Vector1DC
+#define TIVA_I2C8_HANDLER                   Vector1F4
+#define TIVA_I2C9_HANDLER                   Vector1F8
+
+#define TIVA_I2C0_NUMBER                    8
+#define TIVA_I2C1_NUMBER                    37
+#define TIVA_I2C2_NUMBER                    61
+#define TIVA_I2C3_NUMBER                    62
+#define TIVA_I2C4_NUMBER                    70
+#define TIVA_I2C5_NUMBER                    71
+#define TIVA_I2C6_NUMBER                    102
+#define TIVA_I2C7_NUMBER                    103
+#define TIVA_I2C8_NUMBER                    109
+#define TIVA_I2C9_NUMBER                    110
+#endif
+
+/* 1-Wire Master units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)
+#define TIVA_HAS_1WIRE                      FALSE
+#endif
+#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_1WIRE_HANDLER                  Vector1E4
+
+#define TIVA_1WIRE_NUMBER                   105
+#endif
+
+/* CAN units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_CAN0_HANDLER                   VectorD8
+#define TIVA_CAN1_HANDLER                   VectorDC
+
+#define TIVA_CAN0_NUMBER                    38
+#define TIVA_CAN1_NUMBER                    39
+#endif
+
+/* Ethernet MAC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\
+  || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)
+/* no interrupts.*/
+#endif
+#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\
+  || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\
+  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\
+  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_MAC_HANDLER                    VectorE0
+
+#define TIVA_MAC_NUMBER                     40
+#endif
+
+/* Ethernet PHY units.*/
+#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \
+  || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\
+  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)
+/* no interrupts.*/
+#endif
+#if  defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\
+  || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+/* no interrupts.*/
+#endif
+
+/* USB units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_USB0_HANDLER                   VectorE8
+
+#define TIVA_USB0_NUMBER                    42
+#endif
+
+/* LCD units.*/
+#if  defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\
+  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_LCD_HANDLER                    Vector1C4
+
+#define TIVA_LCD_NUMBER                     97
+#endif
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\
+  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)
+/* no interrupts.*/
+#endif
+
+/* AC units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_AC0_HANDLER                    VectorA4
+#define TIVA_AC1_HANDLER                    VectorA8
+#define TIVA_AC2_HANDLER                    VectorAC
+
+#define TIVA_AC0_NUMBER                     25
+#define TIVA_AC1_NUMBER                     26
+#define TIVA_AC2_NUMBER                     27
+#endif
+
+/* PWM units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_PWM0FAULT_HANDLER              Vector64
+#define TIVA_PWM0GEN0_HANDLER               Vector68
+#define TIVA_PWM0GEN1_HANDLER               Vector6C
+#define TIVA_PWM0GEN2_HANDLER               Vector70
+#define TIVA_PWM0GEN3_HANDLER               VectorEC
+
+#define TIVA_PWM0FAULT_NUMBER               9
+#define TIVA_PWM0GEN0_NUMBER                10
+#define TIVA_PWM0GEN1_NUMBER                11
+#define TIVA_PWM0GEN2_NUMBER                12
+#define TIVA_PWM0GEN3_NUMBER                43
+#endif
+
+/* QEI units.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_QEI0_HANLDER                   Vector74
+
+#define TIVA_QEI0_NUMBER                    13
+#endif
+
+/**
+ * @}
+ */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#endif /* _TIVA_ISR_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
new file mode 100644
index 0000000..e38ee51
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
@@ -0,0 +1,368 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    TM4C129x/tiva_registry.h
+ * @brief   TM4C123x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _TIVA_REGISTRY_H_
+#define _TIVA_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    TM4C129x capabilities
+ * @{
+ */
+ 
+/* GPIO attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\
+  || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\
+  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      TRUE
+#define TIVA_HAS_GPIOH                      TRUE
+#define TIVA_HAS_GPIOJ                      TRUE
+#define TIVA_HAS_GPIOK                      TRUE
+#define TIVA_HAS_GPIOL                      TRUE
+#define TIVA_HAS_GPIOM                      TRUE
+#define TIVA_HAS_GPION                      TRUE
+#define TIVA_HAS_GPIOP                      TRUE
+#define TIVA_HAS_GPIOQ                      TRUE
+#define TIVA_HAS_GPIOR                      FALSE
+#define TIVA_HAS_GPIOS                      FALSE
+#define TIVA_HAS_GPIOT                      FALSE
+#endif
+#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\
+  || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\
+  || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\
+  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_GPIOA                      TRUE
+#define TIVA_HAS_GPIOB                      TRUE
+#define TIVA_HAS_GPIOC                      TRUE
+#define TIVA_HAS_GPIOD                      TRUE
+#define TIVA_HAS_GPIOE                      TRUE
+#define TIVA_HAS_GPIOF                      TRUE
+#define TIVA_HAS_GPIOG                      TRUE
+#define TIVA_HAS_GPIOH                      TRUE
+#define TIVA_HAS_GPIOJ                      TRUE
+#define TIVA_HAS_GPIOK                      TRUE
+#define TIVA_HAS_GPIOL                      TRUE
+#define TIVA_HAS_GPIOM                      TRUE
+#define TIVA_HAS_GPION                      TRUE
+#define TIVA_HAS_GPIOP                      TRUE
+#define TIVA_HAS_GPIOQ                      TRUE
+#define TIVA_HAS_GPIOR                      TRUE
+#define TIVA_HAS_GPIOS                      TRUE
+#define TIVA_HAS_GPIOT                      TRUE
+#endif
+
+/* EPI attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_EPI0                       TRUE
+#endif
+
+/* CRC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_CRC0                       TRUE
+#endif
+
+/* AES Accelerator attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD)
+#define TIVA_HAS_AES                        FALSE
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \
+  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+  || defined(TM4C129XNCZAD)
+#define TIVA_HAS_AES                        TRUE
+#endif
+
+/* DES Accelerator attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD)
+#define TIVA_HAS_DES                        FALSE
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+  || defined(TM4C129XNCZAD)
+#define TIVA_HAS_DES                        TRUE
+#endif
+
+/* SHA/MD5 Accelerator attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD)
+#define TIVA_HAS_SHA_MD5                    FALSE
+#endif
+#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\
+  || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\
+  || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\
+  || defined(TM4C129XNCZAD)
+#define TIVA_HAS_SHA_MD5                    TRUE
+#endif
+
+/* GPT attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_GPT0                       TRUE
+#define TIVA_HAS_GPT1                       TRUE
+#define TIVA_HAS_GPT2                       TRUE
+#define TIVA_HAS_GPT3                       TRUE
+#define TIVA_HAS_GPT4                       TRUE
+#define TIVA_HAS_GPT5                       TRUE
+#define TIVA_HAS_GPT6                       TRUE
+#define TIVA_HAS_GPT7                       TRUE
+#define TIVA_HAS_WGPT0                      FALSE
+#define TIVA_HAS_WGPT1                      FALSE
+#define TIVA_HAS_WGPT2                      FALSE
+#define TIVA_HAS_WGPT3                      FALSE
+#define TIVA_HAS_WGPT4                      FALSE
+#define TIVA_HAS_WGPT5                      FALSE
+#endif
+
+/* WDT attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_WDT0                       TRUE
+#define TIVA_HAS_WDT1                       TRUE
+#endif
+
+/* ADC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_ADC0                       TRUE
+#define TIVA_HAS_ADC1                       TRUE
+#endif
+
+/* UART attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_UART0                      TRUE
+#define TIVA_HAS_UART1                      TRUE
+#define TIVA_HAS_UART2                      TRUE
+#define TIVA_HAS_UART3                      TRUE
+#define TIVA_HAS_UART4                      TRUE
+#define TIVA_HAS_UART5                      TRUE
+#define TIVA_HAS_UART6                      TRUE
+#define TIVA_HAS_UART7                      TRUE
+#endif
+
+/* QSSI attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_QSSI0                      TRUE
+#define TIVA_HAS_QSSI1                      TRUE
+#define TIVA_HAS_QSSI2                      TRUE
+#define TIVA_HAS_QSSI3                      TRUE
+#endif
+
+/* I2C attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_I2C0                       TRUE
+#define TIVA_HAS_I2C1                       TRUE
+#define TIVA_HAS_I2C2                       TRUE
+#define TIVA_HAS_I2C3                       TRUE
+#define TIVA_HAS_I2C4                       TRUE
+#define TIVA_HAS_I2C5                       TRUE
+#define TIVA_HAS_I2C6                       TRUE
+#define TIVA_HAS_I2C7                       TRUE
+#define TIVA_HAS_I2C8                       TRUE
+#define TIVA_HAS_I2C9                       TRUE
+#endif
+
+/* 1-Wire Master attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)
+#define TIVA_HAS_1WIRE                      FALSE
+#endif
+#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_1WIRE                      TRUE
+#endif
+
+/* CAN attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_CAN0                       TRUE
+#define TIVA_HAS_CAN1                       TRUE
+#endif
+
+/* Ethernet MAC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\
+  || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)
+#define TIVA_HAS_ETHERNET_MAC               FALSE
+#endif
+#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\
+  || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\
+  || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\
+  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_ETHERNET_MAC               TRUE
+#endif
+
+/* Ethernet PHY attributes.*/
+#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \
+  || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\
+  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)
+#define TIVA_HAS_ETHERNET_PHY               FALSE
+#endif
+#if  defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\
+  || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_ETHERNET_PHY               TRUE
+#endif
+
+/* USB attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_USB0                       TRUE
+#endif
+
+/* LCD attributes.*/
+#if  defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\
+  || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_LCD                        TRUE
+#endif
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\
+  || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)
+#define TIVA_HAS_LCD                        FALSE
+#endif
+
+/* AC attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_AC0                        TRUE
+#define TIVA_HAS_AC1                        TRUE
+#define TIVA_HAS_AC2                        TRUE
+#endif
+
+/* PWM attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_PWM0                       TRUE
+#define TIVA_HAS_PWM1                       FALSE
+#endif
+
+/* QEI attributes.*/
+#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\
+  || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\
+  || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\
+  || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\
+  || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\
+  || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\
+  || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD)
+#define TIVA_HAS_QEI0                       TRUE
+#define TIVA_HAS_QEI1                       FALSE
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _TIVA_REGISTRY_H_ */
+
+/**
+ * @}
+ */
diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
new file mode 100644
index 0000000..1d5c50a
--- /dev/null
+++ b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
@@ -0,0 +1,1066 @@
+/*
+    Copyright (C) 2014 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @addtogroup CMSIS
+ * @{
+ */
+
+/**
+ * @addtogroup TM4C129x
+ * @{
+ */
+
+#ifndef __TM4C129x_H
+#define __TM4C129x_H
+
+/** 
+ * @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __CM4_REV               0x0001  /**< Cortex-M4 Core Revision         */
+#define __MPU_PRESENT           1       /**< MPU present                     */
+#define __NVIC_PRIO_BITS        3       /**< Bits used for Priority Levels   */
+#define __Vendor_SysTickConfig  0       /**< Use different SysTick Config    */
+#define __FPU_PRESENT           1       /**< FPU present                     */
+
+/**
+ * @brief   TM4C129x Interrupt Number Definitions
+ */
+typedef enum IRQn
+{
+  /* TODO: check interrupt numbers with tm4c129 device */
+  /***** Cortex-M4 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14,  /**< Cortex-M4 Non-Maskable Interrupt        */
+  HardFault_IRQn        = -13,  /**< Cortex-M4 Hard Fault Interrupt          */
+  MemoryManagement_IRQn = -12,  /**< Cortex-M4 Memory Management Interrupt   */
+  BusFault_IRQn         = -11,  /**< Cortex-M4 Bus Fault Interrupt           */
+  UsageFault_IRQn       = -10,  /**< Cortex-M4 Usage Fault Interrupt         */
+  SVCall_IRQn           = -5,   /**< Cortex-M4 SV Call Interrupt             */
+  DebugMonitor_IRQn     = -4,   /**< Cortex-M4 Debug Monitor Interrupt       */
+  PendSV_IRQn           = -3,   /**< Cortex-M4 Pend SV Interrupt             */
+  SysTick_IRQn          = -1,   /**< Cortex-M4 System Tick Interrupt         */
+  /***** TM4C129x Specific Interrupt Numbers *********************************/
+  GPIOA_IRQn            = 0,    /**< GPIO Port A                             */
+  GPIOB_IRQn            = 1,    /**< GPIO Port B                             */
+  GPIOC_IRQn            = 2,    /**< GPIO Port C                             */
+  GPIOD_IRQn            = 3,    /**< GPIO Port D                             */
+  GPIOE_IRQn            = 4,    /**< GPIO Port E                             */
+  UART0_IRQn            = 5,    /**< UART0                                   */
+  UART1_IRQn            = 6,    /**< UART1                                   */
+  SSI0_IRQn             = 7,    /**< SSI0                                    */
+  I2C0_IRQn             = 8,    /**< I2C0                                    */
+  PWM0FAULT_IRQn        = 9,    /**< PWM0 Fault                              */
+  PWM0GEN0_IRQn         = 10,   /**< PWM0 Generator 0                        */
+  PWM0GEN1_IRQn         = 11,   /**< PWM0 Generator 1                        */
+  PWM0GEN2_IRQn         = 12,   /**< PWM0 Generator 2                        */
+  QEI0_IRQn             = 13,   /**< QEI0                                    */
+  ADC0SEQ0_IRQn         = 14,   /**< ADC0 Sequence 0                         */
+  ADC0SEQ1_IRQn         = 15,   /**< ADC0 Sequence 1                         */
+  ADC0SEQ2_IRQn         = 16,   /**< ADC0 Sequence 2                         */
+  ADC0SEQ3_IRQn         = 17,   /**< ADC0 Sequence 3                         */
+  WATCHDOG_IRQn         = 18,   /**< Watchdog Timers 0 and 1                 */
+  TIMER0A_IRQn          = 19,   /**< 16/32-Bit Timer 0A                      */
+  TIMER0B_IRQn          = 20,   /**< 16/32-Bit Timer 0B                      */
+  TIMER1A_IRQn          = 21,   /**< 16/32-Bit Timer 1A                      */
+  TIMER1B_IRQn          = 22,   /**< 16/32-Bit Timer 1B                      */
+  TIMER2A_IRQn          = 23,   /**< 16/32-Bit Timer 2A                      */
+  TIMER2B_IRQn          = 24,   /**< 16/32-Bit Timer 2B                      */
+  ACOMP0_IRQn           = 25,   /**< Analog Comparator 0                     */
+  ACOMP1_IRQn           = 26,   /**< Analog Comparator 1                     */
+  SYSCON_IRQn           = 28,   /**< System Control                          */
+  FMCEECON_IRQn         = 29,   /**< Flash Memory Control and EEPROM Control */
+  GPIOF_IRQn            = 30,   /**< GPIO Port F                             */
+  UART2_IRQn            = 33,   /**< UART2                                   */
+  SSI1_IRQn             = 34,   /**< SSI1                                    */
+  TIMER3A_IRQn          = 35,   /**< 16/32-Bit Timer 3A                      */
+  TIMER3B_IRQn          = 36,   /**< 16/32-Bit Timer 3B                      */
+  I2C1_IRQn             = 37,   /**< I2C1                                    */
+  QEI1_IRQn             = 38,   /**< QEI1                                    */
+  CAN0_IRQn             = 39,   /**< CAN0                                    */
+  CAN1_IRQn             = 40,   /**< CAN1                                    */
+  HIBMODULE_IRQn        = 43,   /**< Hibernation Module                      */
+  USB_IRQn              = 44,   /**< USB                                     */
+  PWM0GEN3_IRQn         = 45,   /**< PWM0 Generator 3                        */
+  UDMASFW_IRQn          = 46,   /**< UDMA Software                           */
+  UDMAERR_IRQn          = 47,   /**< UDMA Error                              */
+  ADC1SEQ0_IRQn         = 48,   /**< ADC1 Sequence 0                         */
+  ADC1SEQ1_IRQn         = 49,   /**< ADC1 Sequence 1                         */
+  ADC1SEQ2_IRQn         = 50,   /**< ADC1 Sequence 2                         */
+  ADC1SEQ3_IRQn         = 51,   /**< ADC1 Sequence 3                         */
+  SSI2_IRQn             = 57,   /**< SSI2                                    */
+  SSI3_IRQn             = 58,   /**< SSI3                                    */
+  UART3_IRQn            = 59,   /**< UART3                                   */
+  UART4_IRQn            = 60,   /**< UART4                                   */
+  UART5_IRQn            = 61,   /**< UART5                                   */
+  UART6_IRQn            = 62,   /**< UART6                                   */
+  UART7_IRQn            = 63,   /**< UART7                                   */
+  I2C2_IRQn             = 68,   /**< I2C2                                    */
+  I2C3_IRQn             = 69,   /**< I2C3                                    */
+  TIMER4A_IRQn          = 70,   /**< 16/32-Bit Timer 4A                      */
+  TIMER4B_IRQn          = 71,   /**< 16/32-Bit Timer 4B                      */
+  TIMER5A_IRQn          = 92,   /**< 16/32-Bit Timer 5A                      */
+  TIMER5B_IRQn          = 93,   /**< 16/32-Bit Timer 5B                      */
+  WTIMER0A_IRQn         = 94,   /**< 32/64-Bit Timer 0A                      */
+  WTIMER0B_IRQn         = 95,   /**< 32/64-Bit Timer 0B                      */
+  WTIMER1A_IRQn         = 96,   /**< 32/64-Bit Timer 1A                      */
+  WTIMER1B_IRQn         = 97,   /**< 32/64-Bit Timer 1B                      */
+  WTIMER2A_IRQn         = 98,   /**< 32/64-Bit Timer 2A                      */
+  WTIMER2B_IRQn         = 99,   /**< 32/64-Bit Timer 2B                      */
+  WTIMER3A_IRQn         = 100,  /**< 32/64-Bit Timer 3A                      */
+  WTIMER3B_IRQn         = 101,  /**< 32/64-Bit Timer 3B                      */
+  WTIMER4A_IRQn         = 102,  /**< 32/64-Bit Timer 4A                      */
+  WTIMER4B_IRQn         = 103,  /**< 32/64-Bit Timer 4B                      */
+  WTIMER5A_IRQn         = 104,  /**< 32/64-Bit Timer 5A                      */
+  WTIMER5B_IRQn         = 105,  /**< 32/64-Bit Timer 5B                      */
+  SYSEXCEPT_IRQn        = 106,  /**< System Exception (imprecise)            */
+  PWM1GEN0_IRQn         = 134,  /**< PWM1 Generator 0                        */
+  PWM1GEN1_IRQn         = 135,  /**< PWM1 Generator 1                        */
+  PWM1GEN2_IRQn         = 136,  /**< PWM1 Generator 2                        */
+  PWM1GEN3_IRQn         = 137,  /**< PWM1 Generator 3                        */
+  PWM1FAULT_IRQn        = 138   /**< PWM1 Fault                              */
+} IRQn_Type;
+ 
+/**
+ * @}
+ */
+
+#include "core_cm4.h"   /* Cortex-M4 processor and core peripherals.*/
+#include <stdint.h>
+
+/**
+ * @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/** 
+ * @brief System Control
+ */
+typedef struct
+{
+  __I  uint32_t DID0;           /**< Device Identification 0                 */
+  __I  uint32_t DID1;           /**< Device Identification 1                 */
+  __I  uint32_t RESERVED0[12];  /**< Reserved                                */
+  __IO uint32_t PBORCTL;        /**< Power-Temp Brown Out Control                 */
+  __I  uint32_t RESERVED1[5];   /**< Reserved                                */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t IMC;            /**< Interrupt Mask Control                  */
+  __IO uint32_t MISC;           /**< Interrupt Status and Clear              */
+  __IO uint32_t RESC;           /**< Reset Cause                             */
+  __IO uint32_t PWRTC;          /**< Power-Temperature Cause */
+  __IO uint32_t NMIC;           /**< NMI Cause Register */
+  __I  uint32_t RESERVED2[5];   /**< Reserved */
+  __IO uint32_t MOSCCTL;        /**< Main Oscillator Control */
+  __I  uint32_t RESERVED3[12];  /**< Reserved */
+  __IO uint32_t RSCLKCFG;       /**< Run and Sleep Mode Configuration Register */
+  __I  uint32_t RESERVEDx[3];
+  __IO uint32_t MEMTIM0;        /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
+  __I  uint32_t RESERVED4[29];  /**< Reserved */
+  __IO uint32_t ALTCLKCFG;      /**< Alternate Clock Configuration */
+  __I  uint32_t RESERVED5[2];   /**< Reserved                                */
+  __IO uint32_t DSLPCLKCFG;     /**< Deep Sleep Clock Configuration          */
+  __IO uint32_t DIVSCLK;        /**< Divisor and Source Clock Configuration  */
+  __I  uint32_t SYSPROP;        /**< System Properties                       */
+  __IO uint32_t PIOSCCAL;       /**< PIOSC Calibration                       */
+  __I  uint32_t PIOSCSTAT;      /**< PIOSC Statistics                        */
+  __I  uint32_t RESERVED6[2];   /**< Reserved                                */
+  __IO uint32_t PLLFREQ0;       /**< PLL Frequency 0                         */
+  __IO uint32_t PLLFREQ1;       /**< PLL Frequency 1                         */
+  __I  uint32_t PLLSTAT;        /**< PLL Frequency Status                    */
+  __I  uint32_t RESERVED7[7];   /**< Reserved                                */
+  __IO uint32_t SLPPWRCFG;      /**< Sleep Power Configuration               */
+  __IO uint32_t DSLPPWRCFG;     /**< Deep-Sleep Power Configuration          */
+  __I  uint32_t RESERVED8[4];   /**< Reserved                                */
+  __I  uint32_t NVMSTAT;        /**< Non-Volatile Memory Information */
+  __I  uint32_t RESERVED9[4];   /**< Reserved */
+  __IO uint32_t LDOSPCTL;       /**< LDO Sleep Power Control                 */
+  __I  uint32_t LDOSPCAL;       /**< LDO Sleep Power Calibration             */
+  __IO uint32_t LDODPCTL;       /**< LDO Deep-Sleep Power Control            */
+  __I  uint32_t LDODPCAL;       /**< LDO Deep-Sleep Power Calibration        */
+  __I  uint32_t RESERVED10[2];  /**< Reserved                                */
+  __I  uint32_t SDPMST;         /**< Sleep/Deep-Sleep Power Mode Status      */
+  __I  uint32_t RESERVED11[2];  /**< Reserved */
+  __IO uint32_t RESBEHAVCTL;    /**< Reset Behavior Control Register */
+  __I  uint32_t RESERVED12[6];  /**< Reserved */
+  __IO uint32_t HSSR;           /**< Hardware System Service Request */
+  __I  uint32_t RESERVED[34];   /**< Reserved */
+  __I  uint32_t USBPDS;         /**< USB Power Domain Status */
+  __IO uint32_t USBMPC;         /**< USB Memory Power Control */
+  __I  uint32_t EMACPDS;        /**< Ethernet MAC Power Domain Status */
+  __IO uint32_t EMACMPC;        /**< Ethernet MAC Memory Power Control */
+  __I  uint32_t RESERVED13[2];  /**< Reserved */
+  __I  uint32_t CAN0PDS;        /**< CAN 0 Power Domain Status */
+  __IO uint32_t CAN0MPC;        /**< CAN 0 Memory Power Control */
+  __I  uint32_t CAN1PDS;        /**< CAN 1 Power Domain Status */
+  __IO uint32_t CAN1MPC;        /**< CAN 1 Memory Power Control */
+  __I  uint32_t RESERVED14[22]; /**< Reserved */
+  __I  uint32_t PPWD;           /**< WDT Peripheral Present                  */
+  __I  uint32_t PPTIMER;        /**< GPT Peripheral Present                  */
+  __I  uint32_t PPGPIO;         /**< GPIO Peripheral Present                 */
+  __I  uint32_t PPDMA;          /**< UDMA Peripheral Present                 */
+  __I  uint32_t PPEPI;          /**< EPI Peripheral Present */
+  __I  uint32_t PPHIB;          /**< HIB Peripheral Present                  */
+  __I  uint32_t PPUART;         /**< UART Peripheral Present                 */
+  __I  uint32_t PPSSI;          /**< SSI Peripheral Present                  */
+  __I  uint32_t PPI2C;          /**< I2C Peripheral Present                  */
+  __I  uint32_t RESERVED15[1];  /**< Reserved                                */
+  __I  uint32_t PPUSB;          /**< USB Peripheral Present                  */
+  __I  uint32_t RESERVED16[1];  /**< Reserved                                */
+  __I  uint32_t PPEPHY;         /**< Ethernet PHY Peripheral Present */
+  __I  uint32_t PPCAN;          /**< CAN Peripheral Present                  */
+  __I  uint32_t PPADC;          /**< ADC Peripheral Present                  */
+  __I  uint32_t PPACMP;         /**< ACMP Peripheral Present                 */
+  __I  uint32_t PPPWM;          /**< PWM Peripheral Present                  */
+  __I  uint32_t PPQEI;          /**< QEI Peripheral Present                  */
+  __I  uint32_t PPLPC;          /**< Low Pin Count Interface Peripheral Present */
+  __I  uint32_t RESERVED17[1];  /**< Reserved */
+  __I  uint32_t PPPECI;         /**< Platform Environment Control Interface Peripheral Present */
+  __I  uint32_t PPFAN;          /**< Fan Control Peripheral Present */
+  __I  uint32_t PPEEPROM;       /**< EEPROM Peripheral Present               */
+  __I  uint32_t PPWTIMER;       /**< Wide GPT Peripheral Present             */
+  __I  uint32_t RESERVED18[4];  /**< Reserved */
+  __I  uint32_t PPRTS;          /**< Remote Temperature Sensor Peripheral Present */
+  __I  uint32_t PPCCM;          /**< CRC Module Peripheral Present */
+  __I  uint32_t RESERVED19[6];  /**< Reserved */
+  __I  uint32_t PPLCD;          /**< LCD Peripheral Present */
+  __I  uint32_t RESERVED20[1];  /**< Reserved */
+  __I  uint32_t PPOWIRE;        /**< 1-Wire Peripheral Present */
+  __I  uint32_t PPEMAC;         /**< Ethernet MAC Peripheral Present */
+  __I  uint32_t PPPRB;          /**< Power Regulator Bus Peripheral Present */
+  __I  uint32_t PPHIM;          /**< Human Interface Master Peripheral Present */
+  __I  uint32_t RESERVED21[86]; /**< Reserved */
+  __IO uint32_t SRWD;           /**< WDT Software Reset                      */
+  __IO uint32_t SRTIMER;        /**< GPT Software Reset                      */
+  __IO uint32_t SRGPIO;         /**< GPIO Software Reset                     */
+  __IO uint32_t SRDMA;          /**< UDMA Software Reset                     */
+  __IO uint32_t SREPI;          /**< EPI Software Reset */
+  __IO uint32_t SRHIB;          /**< HIB Software Reset                      */
+  __IO uint32_t SRUART;         /**< UART Software Reset                     */
+  __IO uint32_t SRSSI;          /**< SSI Software Reset                      */
+  __IO uint32_t SRI2C;          /**< I2C Software Reset                      */
+  __I  uint32_t RESERVED22[1];  /**< Reserved                                */
+  __IO uint32_t SRUSB;          /**< USB Software Reset                      */
+  __I  uint32_t RESERVED23[1];  /**< Reserved                                */
+  __IO uint32_t SREPHY;         /**< Ethernet PHY Software Reset */
+  __IO uint32_t SRCAN;          /**< CAN Software Reset                      */
+  __IO uint32_t SRADC;          /**< ADC Software Reset                      */
+  __IO uint32_t SRACMP;         /**< ACMP Software Reset                     */
+  __IO uint32_t SRPWM;          /**< PWM Software Reset                      */
+  __IO uint32_t SRQEI;          /**< QEI Software Reset                      */
+  __I  uint32_t RESERVED24[4];  /**< Reserved                                */
+  __IO uint32_t SREEPROM;       /**< EEPROM Software Reset                   */
+  __I  uint32_t RESERVED25[6];  /**< Reserved */
+  __IO uint32_t SRCCM;          /**< CRC Module Software Reset */
+  __I  uint32_t RESERVED26[9];  /**< Reserved */
+  __IO uint32_t SREMAC;         /**< Ethernet MAC Software Reset */
+  __I  uint32_t RESERVED27[24]; /**< Reserved                                */
+  __IO uint32_t RCGCWD;         /**< WDT Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCTIMER;      /**< GPT Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCGPIO;       /**< GPIO Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCDMA;        /**< UDMA Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCEPI;        /**< EPI Run Mode Clock Gating Control */
+  __IO uint32_t RCGCHIB;        /**< HIB Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCUART;       /**< UART Run Mode Control                   */
+  __IO uint32_t RCGCSSI;        /**< SSI Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCI2C;        /**< I2C Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED28[1];  /**< Reserved                                */
+  __IO uint32_t RCGCUSB;        /**< USB Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED29[1];  /**< Reserved                                */
+  __IO uint32_t RCGCEPHY;       /**< Ethernet PHY Run Mode Clock Gating Control */
+  __IO uint32_t RCGCCAN;        /**< CAN Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCADC;        /**< ADC Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCACMP;       /**< ACMP Run Mode Clock Gating Control      */
+  __IO uint32_t RCGCPWM;        /**< PWM Run Mode Clock Gating Control       */
+  __IO uint32_t RCGCQEI;        /**< QEI Run Mode Clock Gating Control       */
+  __I  uint32_t RESERVED30[4];  /**< Reserved                                */
+  __IO uint32_t RCGCEEPROM;     /**< EEPROM Run Mode Clock Gating Control    */
+  __I  uint32_t RESERVED31[6];  /**< Reserved */
+  __IO uint32_t RCGCCCM;        /**< CRC Module Run Mode Clock Gating Control */
+  __I  uint32_t RESERVED32[9];  /**< Reserved */
+  __IO uint32_t RCGCEMAC;       /**< Ethernet MAC Run Mode Clock Gating Control */
+  __I  uint32_t RESERVED33[24]; /**< Reserved */
+  __IO uint32_t SCGCWD;         /**< WDT Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCTIMER;      /**< GPT Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCGPIO;       /**< GPIO Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCDMA;        /**< UDMA Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCEPI;        /**< EPI Sleep Mode Clock Gating Control */
+  __IO uint32_t SCGCHIB;        /**< HIB Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCUART;       /**< UART Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCSSI;        /**< SSI Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCI2C;        /**< I2C Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED34[1];  /**< Reserved                                */
+  __IO uint32_t SCGCUSB;        /**< USB Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED35[1];  /**< Reserved                                */
+  __IO uint32_t SCGCEPHY;       /**< Ethernet PHY Sleep Mode Clock Gating Control */
+  __IO uint32_t SCGCCAN;        /**< CAN Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCADC;        /**< ADC Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCACMP;       /**< ACMP Sleep Mode Clock Gating Control    */
+  __IO uint32_t SCGCPWM;        /**< PWM Sleep Mode Clock Gating Control     */
+  __IO uint32_t SCGCQEI;        /**< QEI Sleep Mode Clock Gating Control     */
+  __I  uint32_t RESERVED36[4];  /**< Reserved                                */
+  __IO uint32_t SCGCEEPROM;     /**< EEPROM Sleep Mode Clock Gating Control  */
+  __I  uint32_t RESERVED37[6];  /**< Reserved */
+  __IO uint32_t SCGCCCM;        /**< CRC Module Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED38[9];  /**< Reserved */
+  __IO uint32_t SCGCEMAC;       /**< Ethernet MAC Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED39[24]; /**< Reserved                                */
+  __IO uint32_t DCGCWD;         /**< WDT Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCTIMER;      /**< GPT Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCGPIO;       /**< GPIO Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCDMA;        /**< UDMA Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCEPI;        /**< EPI Deep-Sleep Mode Clock Gating Control */
+  __IO uint32_t DCGCHIB;        /**< HIB Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCUART;       /**< UART Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCSSI;        /**< SSI Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCI2C;        /**< I2C Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED40[1];  /**< Reserved                                */
+  __IO uint32_t DCGCUSB;        /**< USB Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED41[1];  /**< Reserved                                */
+  __IO uint32_t DCGCEPHY;       /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
+  __IO uint32_t DCGCCAN;        /**< CAN Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCADC;        /**< ADC Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCACMP;       /**< ACMP Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __IO uint32_t DCGCPWM;        /**< PWM Deep-Sleep Mode Clock Gating Control*/
+  __IO uint32_t DCGCQEI;        /**< QEI Deep-Sleep Mode Clock Gating Control*/
+  __I  uint32_t RESERVED42[4];  /**< Reserved                                */
+  __IO uint32_t DCGCEEPROM;     /**< EEPROM Deep-Sleep Mode Clock Gating
+                                     Control                                 */
+  __I  uint32_t RESERVED43[6];  /**< Reserved */
+  __IO uint32_t DCGCCCM;        /**< CRC Module Deep-Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED44[9];  /**< Reserved */
+  __IO uint32_t DCGCEMAC;       /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
+  __I  uint32_t RESERVED45[24]; /**< Reserved                                */
+  __IO uint32_t PCWD;           /**< Watchdog Timer Power Control       */
+  __IO uint32_t PCTIMER;        /**< 16/32-Bit General-Purpose Timer Power Control       */
+  __IO uint32_t PCGPIO;         /**< General-Purpose Input/Output Power Control      */
+  __IO uint32_t PCDMA;          /**< Micro Direct Memory Access Power Control      */
+  __IO uint32_t PCEPI;          /**< External Peripheral Interface Power Control */
+  __IO uint32_t PCHIB;          /**< Hibernation Power Control       */
+  __IO uint32_t PCUART;         /**< Universal Asynchronous Receiver/Transmitter Power Control                   */
+  __IO uint32_t PCSSI;          /**< Synchronous Serial Interface Power Control       */
+  __IO uint32_t PCI2C;          /**< Inter-Integrated Circuit Power Control       */
+  __I  uint32_t RESERVED46[1];  /**< Reserved                                */
+  __IO uint32_t PCUSB;          /**< Universal Serial Bus Power Control       */
+  __I  uint32_t RESERVED47[1];  /**< Reserved                                */
+  __IO uint32_t PCEPHY;         /**< Ethernet PHY Power Control */
+  __IO uint32_t PCCAN;          /**< Controller Area Network Power Control       */
+  __IO uint32_t PCADC;          /**< Analog-to-Digital Converter Power Control       */
+  __IO uint32_t PCACMP;         /**< Analog Comparator Power Control      */
+  __IO uint32_t PCPWM;          /**< Pulse Width Modulator Power Control       */
+  __IO uint32_t PCQEI;          /**< Quadrature Encoder Interface Power Control       */
+  __I  uint32_t RESERVED48[4];  /**< Reserved                                */
+  __IO uint32_t PCEEPROM;       /**< EEPROM Power Control    */
+  __I  uint32_t RESERVED49[6];  /**< Reserved */
+  __IO uint32_t PCCCM;          /**< CRC Module Power Control */
+  __I  uint32_t RESERVED50[9];  /**< Reserved */
+  __IO uint32_t PCEMAC;         /**< Ethernet MAC Power Control */
+  __I  uint32_t RESERVED51[24]; /**< Reserved */
+  __IO uint32_t PRWD;           /**< WDT Peripheral Ready                    */
+  __IO uint32_t PRTIMER;        /**< GPT Peripheral Ready                    */
+  __IO uint32_t PRGPIO;         /**< GPIO Peripheral Ready                   */
+  __IO uint32_t PRDMA;          /**< UDMA Peripheral Ready                   */
+  __IO uint32_t PREPI;          /**< EPI Peripheral Ready                                */
+  __IO uint32_t PRHIB;          /**< HIB Peripheral Ready                    */
+  __IO uint32_t PRUART;         /**< UART Peripheral Ready                   */
+  __IO uint32_t PRSSI;          /**< SSI Peripheral Ready                    */
+  __IO uint32_t PRI2C;          /**< I2C Peripheral Ready                    */
+  __I  uint32_t RESERVED52[1];  /**< Reserved                                */
+  __IO uint32_t PRUSB;          /**< USB Peripheral Ready                    */
+  __I  uint32_t RESERVED53[1];  /**< Reserved                                */
+  __IO uint32_t PREPHY;         /**< Ethernet PHY Peripheral Ready */
+  __IO uint32_t PRCAN;          /**< CAN Peripheral Ready                    */
+  __IO uint32_t PRADC;          /**< ADC Peripheral Ready                    */
+  __IO uint32_t PRACMP;         /**< ACMP Peripheral Ready                   */
+  __IO uint32_t PRPWM;          /**< PWM Peripheral Ready                    */
+  __IO uint32_t PRQEI;          /**< QEI Peripheral Ready                    */
+  __I  uint32_t RESERVED54[4];  /**< Reserved                                */
+  __IO uint32_t PREEPROM;       /**< EEPROM Peripheral Ready                 */
+  __I  uint32_t RESERVED55[6];  /**< Reserved */
+  __IO uint32_t PRCCM;          /**< CRC Module Peripheral Ready               */
+  __I  uint32_t RESERVED56[9];  /**< Reserved */
+  __IO uint32_t PREMAC;         /**< Ethernet MAC Peripheral Ready */
+} SYSCTL_TypeDef;
+
+/**
+ * @brief Hibernation Module
+ */
+typedef struct
+{
+  __I  uint32_t RTCC;           /**< RTC Counter                             */
+  __IO uint32_t RTCM0;          /**< RTC Match 0                             */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t RTCLD;          /**< RTC Load                                */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __IO uint32_t IC;             /**< Interrupt Clear                         */
+  __IO uint32_t RTCT;           /**< RTC Trim                                */
+  __IO uint32_t RTCSS;          /**< RTC Sub Seconds                         */
+  __I  uint32_t RESERVED1[1];   /**< Reserved                                */
+  __IO uint32_t DATA;           /**< Data                                    */
+} HIB_TypeDef;
+
+/**
+ * @brief Flash Memory
+ */
+typedef struct
+{
+  __IO uint32_t FMA;            /**< Flash Memory Address                    */
+  __IO uint32_t FMD;            /**< Flash Memory Data                       */
+  __IO uint32_t FMC;            /**< Flash Memory Control                    */
+  __I  uint32_t FCRIS;          /**< Flash Controller Raw Interrupt Status   */
+  __IO uint32_t FCIM;           /**< Flash Controller Interrupt Mask         */
+  __IO uint32_t FCMISC;         /**< Masked Interrupt Status and Clear       */
+  __I  uint32_t RESERVED0[2];   /**< Reserved                                */
+  __IO uint32_t FMC2;           /**< Flash Memory Control 2                  */
+  __I  uint32_t RESERVED1[3];   /**< Reserved                                */
+  __IO uint32_t FWBVAL;         /**< Flash Write Buffer Valid                */
+  __I  uint32_t RESERVED2[51];  /**< Reserved                                */
+  __IO uint32_t FWBN;           /**< Flash Write Buffer n                    */
+  __I  uint32_t RESERVED3[943]; /**< Reserved                                */
+  __I  uint32_t FSIZE;          /**< Flash Size                              */
+  __I  uint32_t SSIZE;          /**< SRAM Size                               */
+  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
+  __IO uint32_t ROMSWMAP;       /**< ROM Software Map                        */
+} FLASH_TypeDef;
+
+/**
+ * @brief EEPROM Memory
+ */
+typedef struct
+{
+  __IO uint32_t EESIZE;         /**< Size Information                        */
+  __IO uint32_t EEBLOCK;        /**< Current Block                           */
+  __IO uint32_t EEOFFSET;       /**< Current Offset                          */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t EERDWR;         /**< Read-Write                              */
+  __IO uint32_t EERDWRINC;      /**< Read-Write with Increment               */
+  __IO uint32_t EEDONE;         /**< Done Status                             */
+  __IO uint32_t EESUPP;         /**< Support Control and Status              */
+  __IO uint32_t EEUNLOCK;       /**< Unlock                                  */
+  __I  uint32_t RESERVED1[3];   /**< Reserved                                */
+  __IO uint32_t EEPROT;         /**< Protection                              */
+  __IO uint32_t EEPASS0;        /**< Password                                */
+  __IO uint32_t EEPASS1;        /**< Password                                */
+  __IO uint32_t EEPASS2;        /**< Password                                */
+  __IO uint32_t EEINT;          /**< Interrupt                               */
+  __I  uint32_t RESERVED2[3];   /**< Reserved                                */
+  __IO uint32_t EEHIDE;         /**< Block Hide                              */
+  __I  uint32_t RESERVED3[11];  /**< Reserved                                */
+  __IO uint32_t EEDBGME;        /**< Debug Mass Erase                        */
+  __I  uint32_t RESERVED4[975]; /**< Reserved                                */
+  __IO uint32_t EEPROMPP;       /**< Peripheral Properties                   */
+} EEPROM_TypeDef;
+
+/**
+ * @brief Micro Direct Memory Access
+ */
+typedef struct 
+{
+  __IO uint32_t STAT;           /**< Status                                  */
+  __O  uint32_t CFG;            /**< Configuration                           */
+  __IO uint32_t CTLBASE;        /**< Channel Control Base Pointer            */
+  __IO uint32_t ALTBASE;        /**< Alternate Channel Control Base Pointer  */
+  __IO uint32_t WAITSTAT;       /**< Channel Wait-on-Request Status          */
+  __O  uint32_t SWREQ;          /**< Channel Software Request                */
+  __IO uint32_t USEBURSTSET;    /**< Channel Useburst Set                    */
+  __O  uint32_t USEBURSTCLR;    /**< Channel Useburst Clear                  */
+  __IO uint32_t REQMASKSET;     /**< Channel Request Mask Set                */
+  __O  uint32_t REQMASKCLR;     /**< Channel Request Mask Clear              */
+  __IO uint32_t ENASET;         /**< Channel Enable Set                      */
+  __O  uint32_t ENACLR;         /**< Channel Enable Clear                    */
+  __IO uint32_t ALTSET;         /**< Channel Primary Alternate Set           */
+  __O  uint32_t ALTCLR;         /**< Channel Primary Alternate Clear         */
+  __IO uint32_t PRIOSET;        /**< Channel Priority Set                    */
+  __O  uint32_t PRIOCLR;        /**< Channel Priority Clear                  */
+  __I  uint32_t RESERVED0[3];   /**< Reserved                                */
+  __IO uint32_t ERRCLR;         /**< Bus Error Clear                         */
+  __I  uint32_t RESERVED1[300]; /**< Reserved                                */
+  __IO uint32_t CHASGN;         /**< Channel Assignment                      */
+  __IO uint32_t CHIS;           /**< Channel Interrupt Status                */
+  __I  uint32_t RESERVED2[2];   /**< Reserved                                */
+  __IO uint32_t CHMAP0;         /**< Channel Map Select 0                    */
+  __IO uint32_t CHMAP1;         /**< Channel Map Select 1                    */
+  __IO uint32_t CHMAP2;         /**< Channel Map Select 2                    */
+  __IO uint32_t CHMAP3;         /**< Channel Map Select 3                    */
+} UDMA_TypeDef;
+
+/**
+ * @brief General Purpose Input/Outputs
+ */
+typedef struct 
+{
+  union {
+    __IO uint32_t MASKED_ACCESS[256];   /**< Masked access of Data Register  */
+    struct {
+      __I  uint32_t RESERVED0[255];     /**< Reserved                        */
+      __IO uint32_t DATA;       /**< Data                                    */
+    };
+  };
+  __IO uint32_t DIR;            /**< Direction                               */
+  __IO uint32_t IS;             /**< Interrupt Sense                         */
+  __IO uint32_t IBE;            /**< Interrupt Both Edges                    */
+  __IO uint32_t IEV;            /**< Interrupt Event                         */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __IO uint32_t AFSEL;          /**< Alternate Function Select               */
+  __I  uint32_t RESERVED1[55];  /**< Reserved                                */
+  __IO uint32_t DR2R;           /**< 2-mA Drive Select                       */
+  __IO uint32_t DR4R;           /**< 4-mA Drive Select                       */
+  __IO uint32_t DR8R;           /**< 8-mA Drive Select                       */
+  __IO uint32_t ODR;            /**< Open Drain Select                       */
+  __IO uint32_t PUR;            /**< Pull-Up Select                          */
+  __IO uint32_t PDR;            /**< Pull-Down Select                        */
+  __IO uint32_t SLR;            /**< Slew Rate Control Select                */
+  __IO uint32_t DEN;            /**< Digital Enable                          */
+  __IO uint32_t LOCK;           /**< Lock                                    */
+  __IO uint32_t CR;             /**< Commit                                  */
+  __IO uint32_t AMSEL;          /**< Analog Mode Select                      */
+  __IO uint32_t PCTL;           /**< Port Control                            */
+  __IO uint32_t ADCCTL;         /**< ADC Control                             */
+  __IO uint32_t DMACTL;         /**< DMA Control                             */
+  __IO uint32_t SI;             /**< */
+  __IO uint32_t DR12R;          /**< */
+  __IO uint32_t WAKEPEN;        /**< */
+  __IO uint32_t WAKELVL;        /**< */
+  __IO uint32_t WAKESTAT;       /**< */
+  __I  uint32_t RESERVED2[669]; /**< */
+  __I  uint32_t PP;             /**< */
+  __IO uint32_t PC;             /**< */
+} GPIO_TypeDef;
+
+/**
+ * @brief General Purpose Timer
+ */
+typedef struct
+{
+  __IO uint32_t CFG;            /**< Configuration                           */
+  __IO uint32_t TAMR;           /**< Timer A Mode                            */
+  __IO uint32_t TBMR;           /**< Timer B Mode                            */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t SYNC;           /**< Synchronize                             */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t IMR;            /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __IO uint32_t TAILR;          /**< Timer A Interval Load                   */
+  __IO uint32_t TBILR;          /**< Timer B Interval Load                   */
+  __IO uint32_t TAMATCHR;       /**< Timer A Match                           */
+  __IO uint32_t TBMATCHR;       /**< Timer B Match                           */
+  __IO uint32_t TAPR;           /**< Timer A Prescale                        */
+  __IO uint32_t TBPR;           /**< Timer B Prescale                        */
+  __IO uint32_t TAPMR;          /**< Timer A Prescale Match                  */
+  __IO uint32_t TBPMR;          /**< Timer B Prescale Match                  */
+  __I  uint32_t TAR;            /**< Timer A                                 */
+  __I  uint32_t TBR;            /**< Timer B                                 */
+  __IO uint32_t TAV;            /**< Timer A Value                           */
+  __IO uint32_t TBV;            /**< Timer B Value                           */
+  __I  uint32_t RTCPD;          /**< RTC Predivide                           */
+  __I  uint32_t TAPS;           /**< Timer A Prescale Snapshot               */
+  __I  uint32_t TBPS;           /**< Timer B Prescale Snapshot               */
+  __I  uint32_t TAPV;           /**< Timer A Prescale Value                  */
+  __I  uint32_t TBPV;           /**< Timer B Prescale Value                  */
+  __I  uint32_t RESERVED1[981]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+} GPT_TypeDef;
+
+/**
+ * @brief Watchdog Timer
+ */
+typedef struct
+{
+  __IO uint32_t LOAD;           /**< Load                                    */
+  __I  uint32_t VALUE;          /**< Value                                   */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __I  uint32_t RESERVED0[256]; /**< Reserved                                */
+  __IO uint32_t TEST;           /**< Test                                    */
+  __I  uint32_t RESERVED1[505]; /**< Reserved                                */
+  __IO uint32_t LOCK;           /**< Lock                                    */
+} WATCHDOG_TypeDef;
+
+/**
+ * @brief Analog-to-Digital Converter
+ */
+typedef struct
+{
+  __IO uint32_t ACTSS;          /**< Active Sample Sequencer                 */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+  __IO uint32_t OSTAT;          /**< Overflow Status                         */
+  __IO uint32_t EMUX;           /**< Event Multiplexer Select                */
+  __IO uint32_t USTAT;          /**< Underflow Status                        */
+  __IO uint32_t TSSEL;          /**< Trigger Source Select                   */
+  __IO uint32_t SSPRI;          /**< Sample Sequencer Priority               */
+  __IO uint32_t SPC;            /**< Sample Phase Control                    */
+  __IO uint32_t PSSI;           /**< Processor Sample Sequence Initiate      */
+  __I  uint32_t RESERVED1[1];   /**< Reserved                                */
+  __IO uint32_t SAC;            /**< Sample Averaging Control                */
+  __IO uint32_t DCISC;          /**< Digital Comparator Interrupt Status and 
+                                     Clear                                   */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __I  uint32_t RESERVED2[1];   /**< Reserved                                */
+  __IO uint32_t SSMUX0;         /**< Sample Sequence Input Multiplexer Select
+                                     0                                       */
+  __IO uint32_t SSCTL0;         /**< Sample Sequence Control 0               */
+  __I  uint32_t SSFIFO0;        /**< Sample Sequence Result FIFO 0           */
+  __I  uint32_t SSFSTAT0;       /**< Sample Sequence FIFO 0 Status           */
+  __IO uint32_t SSOP0;          /**< Sample Sequence 0 Operation             */
+  __IO uint32_t SSDC0;          /**< Sample Sequence 0 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED3[2];   /**< Reserved                                */
+  __IO uint32_t SSMUX1;         /**< Sample Sequence Input Multiplexer Select
+                                     1                                       */
+  __IO uint32_t SSCTL1;         /**< Sample Sequence Control 1               */
+  __I  uint32_t SSFIFO1;        /**< Sample Sequence Result FIFO 1           */
+  __I  uint32_t SSFSTAT1;       /**< Sample Sequence FIFO 1 Status           */
+  __IO uint32_t SSOP1;          /**< Sample Sequence 1 Operation             */
+  __IO uint32_t SSDC1;          /**< Sample Sequence 1 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED4[2];   /**< Reserved                                */
+  __IO uint32_t SSMUX2;         /**< Sample Sequence Input Multiplexer Select
+                                     2                                       */
+  __IO uint32_t SSCTL2;         /**< Sample Sequence Control 2               */
+  __I  uint32_t SSFIFO2;        /**< Sample Sequence Result FIFO 2           */
+  __I  uint32_t SSFSTAT2;       /**< Sample Sequence FIFO 2 Status           */
+  __IO uint32_t SSOP2;          /**< Sample Sequence 2 Operation             */
+  __IO uint32_t SSDC2;          /**< Sample Sequence 2 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED5[2];   /**< Reserved                                */
+  __IO uint32_t SSMUX3;         /**< Sample Sequence Input Multiplexer Select
+                                     3                                       */
+  __IO uint32_t SSCTL3;         /**< Sample Sequence Control 3               */
+  __I  uint32_t SSFIFO3;        /**< Sample Sequence Result FIFO 3           */
+  __I  uint32_t SSFSTAT3;       /**< Sample Sequence FIFO 3 Status           */
+  __IO uint32_t SSOP3;          /**< Sample Sequence 3 Operation             */
+  __IO uint32_t SSDC3;          /**< Sample Sequence 3 Digital Comparator
+                                     Select                                  */
+  __I  uint32_t RESERVED6[786]; /**< Reserved                                */
+  __O  uint32_t DCRIC;          /**< Digital Comparator Reset Initial
+                                     Conditions                              */
+  __I  uint32_t RESERVED7[63];  /**< Reserved                                */
+  __IO uint32_t DCCTL0;         /**< Digital Comparator Control 0            */
+  __IO uint32_t DCCTL1;         /**< Digital Comparator Control 1            */
+  __IO uint32_t DCCTL2;         /**< Digital Comparator Control 2            */
+  __IO uint32_t DCCTL3;         /**< Digital Comparator Control 3            */
+  __IO uint32_t DCCTL4;         /**< Digital Comparator Control 4            */
+  __IO uint32_t DCCTL5;         /**< Digital Comparator Control 5            */
+  __IO uint32_t DCCTL6;         /**< Digital Comparator Control 6            */
+  __IO uint32_t DCCTL7;         /**< Digital Comparator Control 7            */
+  __I  uint32_t RESERVED8[8];   /**< Reserved                                */
+  __IO uint32_t DCCMP0;         /**< Digital Comparator Range 0              */
+  __IO uint32_t DCCMP1;         /**< Digital Comparator Range 1              */
+  __IO uint32_t DCCMP2;         /**< Digital Comparator Range 2              */
+  __IO uint32_t DCCMP3;         /**< Digital Comparator Range 3              */
+  __IO uint32_t DCCMP4;         /**< Digital Comparator Range 4              */
+  __IO uint32_t DCCMP5;         /**< Digital Comparator Range 5              */
+  __IO uint32_t DCCMP6;         /**< Digital Comparator Range 6              */
+  __IO uint32_t DCCMP7;         /**< Digital Comparator Range 7              */
+  __I  uint32_t RESERVED9[88];  /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __IO uint32_t PC;             /**< Peripheral Configuration                */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} ADC_TypeDef;
+
+/** 
+ * @brief Universal Asynchronous Receiver/Transmitter
+ */
+typedef struct 
+{
+  __IO uint32_t DR;             /**< Data                                    */
+  union  {
+    __I  uint32_t RSR;          /**< Receive Status                          */
+    __O  uint32_t ECR;          /**< Error Clear                             */
+  };
+  __I  uint32_t RESERVED0[4];   /**< Reserved                                */
+  __I  uint32_t FR;             /**< Flag                                    */
+  __I  uint32_t RESERVED1[1];   /**< Reserved                                */
+  __IO uint32_t ILPR;           /**< IrDA Low-Power Register                 */
+  __IO uint32_t IBRD;           /**< Integer Baud-Rate Divisor               */
+  __IO uint32_t FBRD;           /**< Fractional Baud-Rate Divisor            */
+  __IO uint32_t LCRH;           /**< Line Control                            */
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t IFLS;           /**< Interrupt FIFO Level Select             */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O uint32_t ICR;             /**< Interrupt Clear                         */
+  __IO uint32_t DMACTL;         /**< DMA Control                             */
+  __I  uint32_t RESERVED2[22];  /**< Reserved                                */
+  __IO uint32_t BIT9ADDR;       /**< 9-Bit Self Address                      */
+  __IO uint32_t BIT9AMASK;      /**< 9-Bit Self Address Mask                 */
+  __I  uint32_t RESERVED3[965]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __I  uint32_t RESERVED4[1];   /**< Reserved                                */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} UART_TypeDef;
+
+/** 
+ * @brief Synchronous Serial Interface
+ */
+typedef struct 
+{
+  __IO uint32_t CR0;            /**< Control 0                               */
+  __IO uint32_t CR1;            /**< Control 1                               */
+  __IO uint32_t DR;             /**< Data                                    */
+  __I  uint32_t SR;             /**< Status                                  */
+  __IO uint32_t CPSR;           /**< Clock Prescale                          */
+  __IO uint32_t IM;             /**< Interrupt Mask                          */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __I  uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __O  uint32_t ICR;            /**< Interrupt Clear                         */
+  __IO uint32_t DMACTL;         /**< DMA Control                             */
+  __I  uint32_t RESERVED1[1000];/**< Reserved                                */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} SSI_TypeDef;
+
+/** 
+ * @brief Inter-Integrated Circuit
+ */
+typedef struct 
+{
+  __IO uint32_t MSA;            /**< Master Slave Address                    */
+  __IO uint32_t MCS;            /**< Master Control/Status                   */
+  __IO uint32_t MDR;            /**< Master Data                             */
+  __IO uint32_t MTPR;           /**< Master Timer Period                     */
+  __IO uint32_t MIMR;           /**< Master Interrupt Mask                   */
+  __I  uint32_t MRIS;           /**< Master Raw Interrupt Status             */
+  __IO uint32_t MMIS;           /**< Master Masked Interrupt Status          */
+  __O  uint32_t MICR;           /**< Master Interrupt Clear                  */
+  __IO uint32_t MCR;            /**< Master Configuration                    */
+  __IO uint32_t MCLKOCNT;       /**< Master Clock Low Timeout Count          */
+  __I  uint32_t RESERVED0;      /**< Reserved                                */
+  __I  uint32_t MBMON;          /**< Master Bus Monitor                      */
+  __IO uint32_t MCR2;           /**< Master Configuration 2                  */
+  __I  uint32_t RESERVED1[497]; /**< Reserved                                */
+  __IO uint32_t SOAR;           /**< Slave Own Address                       */
+  __IO uint32_t SCSR;           /**< Slave Control/Status                    */
+  __IO uint32_t SDR;            /**< Slave Data                              */
+  __IO uint32_t SIMR;           /**< Slave Interrupt Mask                    */
+  __I  uint32_t SRIS;           /**< Slave Raw Interrupt Status              */
+  __I  uint32_t SMIS;           /**< Slave Masked Interrupt Status           */
+  __O  uint32_t SICR;           /**< Slave Interrupt Clear                   */
+  __IO uint32_t SOAR2;          /**< Slave Own Address 2                     */
+  __IO uint32_t SACKCTL;        /**< Slave ACK Control                       */
+  __I  uint32_t RESERVED2[487]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __I  uint32_t PC;             /**< Peripheral Configuration                */
+} I2C_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t STS;            /**< Status                                  */
+  __I  uint32_t ERR;            /**< Error Counter                           */
+  __IO uint32_t BIT;            /**< Bit Timing                              */
+  __I  uint32_t INT;            /**< Interrupt                               */
+  __IO uint32_t TST;            /**< Test                                    */
+  __IO uint32_t BRPE;           /**< Baud Rate Prescaler Extension           */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t IF1CRQ;         /**< IF1 Command Request                     */
+  __IO uint32_t IF1CMSK;        /**< IF1 Command Mask                        */
+  __IO uint32_t IF1MSK1;        /**< IF1 Mask 1                              */
+  __IO uint32_t IF1MSK2;        /**< IF1 Mask 2                              */
+  __IO uint32_t IF1ARB1;        /**< IF1 Arbitration 1                       */
+  __IO uint32_t IF1ARB2;        /**< IF1 Arbitration 2                       */
+  __IO uint32_t IF1MCTL;        /**< IF1 Message Control                     */
+  __IO uint32_t IF1DA1;         /**< IF1 Data A1                             */
+  __IO uint32_t IF1DA2;         /**< IF1 Data A2                             */
+  __IO uint32_t IF1DB1;         /**< IF1 Data B1                             */
+  __IO uint32_t IF1DB2;         /**< IF1 Data B2                             */
+  __I  uint32_t RESERVED1[13];  /**< Reserved                                */
+  __IO uint32_t IF2CRQ;         /**< IF2 Command Request                     */
+  __IO uint32_t IF2CMSK;        /**< IF2 Command Mask                        */
+  __IO uint32_t IF2MSK1;        /**< IF2 Mask 1                              */
+  __IO uint32_t IF2MSK2;        /**< IF2 Mask 2                              */
+  __IO uint32_t IF2ARB1;        /**< IF2 Arbitration 1                       */
+  __IO uint32_t IF2ARB2;        /**< IF2 Arbitration 2                       */
+  __IO uint32_t IF2MCTL;        /**< IF2 Message Control                     */
+  __IO uint32_t IF2DA1;         /**< IF2 Data A1                             */
+  __IO uint32_t IF2DA2;         /**< IF2 Data A2                             */
+  __IO uint32_t IF2DB1;         /**< IF2 Data B1                             */
+  __IO uint32_t IF2DB2;         /**< IF2 Data B2                             */
+  __I  uint32_t RESERVED2[21];  /**< Reserved                                */
+  __I  uint32_t TXRQ1;          /**< Transmission Request 1                  */
+  __I  uint32_t TXRQ2;          /**< Transmission Request 2                  */
+  __I  uint32_t RESERVED3[6];   /**< Reserved                                */
+  __I  uint32_t NWDA1;          /**< New Data 1                              */
+  __I  uint32_t NWDA2;          /**< New Data 2                              */
+  __I  uint32_t RESERVED4[6];   /**< Reserved                                */
+  __I  uint32_t MSG1INT;        /**< Message 1 Interrupt Pending             */
+  __I  uint32_t MSG2INT;        /**< Message 2 Interrupt Pending             */
+  __I  uint32_t RESERVED5[6];   /**< Reserved                                */
+  __I  uint32_t MSG1VAL;        /**< Message 1 Valid                         */
+  __I  uint32_t MSG2VAL;        /**< Message 2 Valid                         */
+} CAN_TypeDef;
+
+// USB
+
+/**
+ * @brief Analog Comparator
+ */
+typedef struct
+{
+  __IO uint32_t MIS;            /**< Masked Interrupt Status                 */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
+  __I  uint32_t RESERVED0[1];   /**< Reserved                                */
+  __IO uint32_t REFCTL;         /**< Reference Voltage Control               */
+  __I  uint32_t RESERVED1[3];   /**< Reserved                                */
+  __I  uint32_t STAT0;          /**< Status 0                                */
+  __IO uint32_t CTL0;           /**< Control 0                               */
+  __I  uint32_t RESERVED2[6];   /**< Reserved                                */
+  __I  uint32_t STAT1;          /**< Status 1                                */
+  __IO uint32_t CTL1;           /**< Control 1                               */
+  __I  uint32_t RESERVED3[990]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+} AC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Control                                 */
+  __IO uint32_t INTEN;          /**< Interrupt and Trigger Enable            */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+  __IO uint32_t LOAD;           /**< Load                                    */
+  __I  uint32_t COUNT;          /**< Counter                                 */
+  __IO uint32_t CMP[2];         /**< Compare A, B                            */
+  __IO uint32_t GEN[2];         /**< Generator A, B Control                  */
+  __IO uint32_t DBCTL;          /**< Dead-Band Control                       */
+  __IO uint32_t DBRISE;         /**< Dead-Band Rising-Edge Delay             */
+  __IO uint32_t DBFALL;         /**< Dead-Band Falling-Edge Delay            */
+  __IO uint32_t FLTSRC[2];      /**< Fault Source 0, 1                       */
+  __IO uint32_t MINFLTPER;      /**< Minimum Fault Period                    */
+} PWM_GENERATOR_T;
+
+/*
+ * @brief Pulse Width Modulator
+ */
+typedef struct
+{
+  __IO uint32_t CTL;            /**< Master Control                          */
+  __IO uint32_t SYNC;           /**< Time Base Sync                          */
+  __IO uint32_t ENABLE;         /**< Output Enable                           */
+  __IO uint32_t INVERT;         /**< Output Inversion                        */
+  __IO uint32_t FAULT;          /**< Output Fault                            */
+  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+  __I  uint32_t STATUS;         /**< Status                                  */
+  __IO uint32_t FAULTVAL;       /**< Fault Condition Value                   */
+  __IO uint32_t ENUPD;          /**< Enable Update                           */
+  __I  uint32_t RESERVED0[5];   /**< Reserved                                */
+  __IO PWM_GENERATOR_T PWM[4];  /**< PWM Generator 0, 1, 2 and 3             */
+  __I  uint32_t RESERVED1[432]; /**< Reserved                                */
+  __IO uint32_t _0FLTSEN;       /**< Fault Pin Logic Sense                   */
+  __IO uint32_t _0FLTSTAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED2[29];  /**< Reserved                                */
+  __IO uint32_t _1FLTSEN;       /**< Fault Pin Logic Sense                   */
+  __IO uint32_t _1FLSTSAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED3[30];  /**< Reserved                                */
+  __IO uint32_t _2FLTSTAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED4[30];  /**< Reserved                                */
+  __IO uint32_t _3FLTSTAT[2];   /**< Fault Status 0, 1                       */
+  __I  uint32_t RESERVED5[397]; /**< Reserved                                */
+  __I  uint32_t PP;             /**< Peripheral Properties                   */
+  __IO uint32_t CC;             /**< Clock Configuration                     */
+} PWM_TypeDef;
+
+/** 
+ * @brief Quadrature Encoder Interface
+ */
+typedef struct 
+{
+  __IO uint32_t CTL;            /**< Control                                 */
+  __I  uint32_t STAT;           /**< Status                                  */
+  __IO uint32_t POS;            /**< Position                                */
+  __IO uint32_t MAXPOS;         /**< Maximum Position                        */
+  __IO uint32_t LOAD;           /**< Timer Load                              */
+  __I  uint32_t TIME;           /**< Timer                                   */
+  __I  uint32_t COUNT;          /**< Velocity Counter                        */
+  __I  uint32_t SPEED;          /**< Velocity                                */
+  __IO uint32_t INTEN;          /**< Interrupt Enable                        */
+  __I  uint32_t RIS;            /**< Raw Interrupt Status                    */
+  __IO uint32_t ISC;            /**< Interrupt Status and Clear              */
+} QEI_TypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup Peripheral_memorymap
+ * @{
+ */
+
+#define SYSCTL_BASE 0x400FE000
+#define HIB_BASE    0x400FC000
+#define FLASH_BASE  0x400FD000
+#define EEPROM_BASE 0x400AF000
+#define UDMA_BASE   0x400FF000
+#define GPIOA_BASE  0x40058000
+#define GPIOB_BASE  0x40059000
+#define GPIOC_BASE  0x4005A000
+#define GPIOD_BASE  0x4005B000
+#define GPIOE_BASE  0x4005C000
+#define GPIOF_BASE  0x4005D000
+#define GPIOG_BASE  0x4005E000
+#define GPIOH_BASE  0x4005F000
+#define GPIOJ_BASE  0x40060000
+#define GPIOK_BASE  0x40061000
+#define GPIOL_BASE  0x40062000
+#define GPIOM_BASE  0x40063000
+#define GPION_BASE  0x40064000
+#define GPIOP_BASE  0x40065000
+#define GPIOQ_BASE  0x40066000
+#define GPT0_BASE   0x40030000
+#define GPT1_BASE   0x40031000
+#define GPT2_BASE   0x40032000
+#define GPT3_BASE   0x40033000
+#define GPT4_BASE   0x40034000
+#define GPT5_BASE   0x40035000
+#define WGPT0_BASE  0x40036000
+#define WGPT1_BASE  0x40037000
+#define WGPT2_BASE  0x4004C000
+#define WGPT3_BASE  0x4004D000
+#define WGPT4_BASE  0x4004E000
+#define WGPT5_BASE  0x4004F000
+#define WDT0_BASE   0x40000000
+#define WDT1_BASE   0x40001000
+#define ADC0_BASE   0x40038000
+#define ADC1_BASE   0x40039000
+#define UART0_BASE  0x4000C000
+#define UART1_BASE  0x4000D000
+#define UART2_BASE  0x4000E000
+#define UART3_BASE  0x4000F000
+#define UART4_BASE  0x40010000
+#define UART5_BASE  0x40011000
+#define UART6_BASE  0x40012000
+#define UART7_BASE  0x40013000
+#define SSI0_BASE   0x40008000
+#define SSI1_BASE   0x40009000
+#define SSI2_BASE   0x4000A000
+#define SSI3_BASE   0x4000B000
+#define I2C0_BASE   0x40020000
+#define I2C1_BASE   0x40021000
+#define I2C2_BASE   0x40022000
+#define I2C3_BASE   0x40023000
+#define CAN0_BASE   0x40040000
+#define CAN1_BASE   0x40041000
+// usb
+#define AC_BASE     0x4003C000
+#define PWM0_BASE   0x40028000
+#define QEI0_BASE   0x4002C000
+#define QEI1_BASE   0x4002D000
+
+/**
+ * @}
+ */
+
+/** 
+ * @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define SYSCTL  ((SYSCTL_TypeDef *) SYSCTL_BASE)
+#define HIB     ((HIB_TypeDef *)    HIB_BASE)
+#define FLASH   ((FLASH_TypeDef *)  FLASH_BASE)
+#define EEPROM  ((EEPROM_TypeDef *) EEPROM_BASE)
+#define UDMA    ((UDMA_TypeDef *)   UDMA_BASE)										
+#define GPIOA   ((GPIO_TypeDef *)   GPIOA_BASE)
+#define GPIOB   ((GPIO_TypeDef *)   GPIOB_BASE)
+#define GPIOC   ((GPIO_TypeDef *)   GPIOC_BASE)
+#define GPIOD   ((GPIO_TypeDef *)   GPIOD_BASE)
+#define GPIOE   ((GPIO_TypeDef *)   GPIOE_BASE)
+#define GPIOF   ((GPIO_TypeDef *)   GPIOF_BASE)
+#define GPIOG   ((GPIO_TypeDef *)   GPIOG_BASE)
+#define GPIOH   ((GPIO_TypeDef *)   GPIOH_BASE)
+#define GPIOJ   ((GPIO_TypeDef *)   GPIOJ_BASE)
+#define GPIOK   ((GPIO_TypeDef *)   GPIOK_BASE)
+#define GPIOL   ((GPIO_TypeDef *)   GPIOL_BASE)
+#define GPIOM   ((GPIO_TypeDef *)   GPIOM_BASE)
+#define GPION   ((GPIO_TypeDef *)   GPION_BASE)
+#define GPIOP   ((GPIO_TypeDef *)   GPIOP_BASE)
+#define GPIOQ   ((GPIO_TypeDef *)   GPIOQ_BASE)
+#define GPT0    ((GPT_TypeDef *)    GPT0_BASE)
+#define GPT1    ((GPT_TypeDef *)    GPT1_BASE)
+#define GPT2    ((GPT_TypeDef *)    GPT2_BASE)
+#define GPT3    ((GPT_TypeDef *)    GPT3_BASE)
+#define GPT4    ((GPT_TypeDef *)    GPT4_BASE)
+#define GPT5    ((GPT_TypeDef *)    GPT5_BASE)
+#define WGPT0   ((GPT_TypeDef *)    WGPT0_BASE)
+#define WGPT1   ((GPT_TypeDef *)    WGPT1_BASE)
+#define WGPT2   ((GPT_TypeDef *)    WGPT2_BASE)
+#define WGPT3   ((GPT_TypeDef *)    WGPT3_BASE)
+#define WGPT4   ((GPT_TypeDef *)    WGPT4_BASE)
+#define WGPT5   ((GPT_TypeDef *)    WGPT5_BASE)
+#define ADC0    ((ADC_TypeDef*)     ADC0_BASE)
+#define ADC1    ((ADC_TypeDef*)     ADC1_BASE)
+#define UART0   ((UART_TypeDef *)   UART0_BASE)
+#define UART1   ((UART_TypeDef *)   UART1_BASE)
+#define UART2   ((UART_TypeDef *)   UART2_BASE)
+#define UART3   ((UART_TypeDef *)   UART3_BASE)
+#define UART4   ((UART_TypeDef *)   UART4_BASE)
+#define UART5   ((UART_TypeDef *)   UART5_BASE)
+#define UART6   ((UART_TypeDef *)   UART6_BASE)
+#define UART7   ((UART_TypeDef *)   UART7_BASE)
+#define SSI0    ((SSI_TypeDef *)    SSI0_BASE)
+#define SSI1    ((SSI_TypeDef *)    SSI1_BASE)
+#define SSI2    ((SSI_TypeDef *)    SSI2_BASE)
+#define SSI3    ((SSI_TypeDef *)    SSI3_BASE)
+#define I2C0    ((I2C_TypeDef *)    I2C0_BASE)
+#define I2C1    ((I2C_TypeDef *)    I2C1_BASE)
+#define I2C2    ((I2C_TypeDef *)    I2C2_BASE)
+#define I2C3    ((I2C_TypeDef *)    I2C3_BASE)
+#define CAN0    ((CAN_TypeDef *)    CAN0_BASE)
+#define CAN1    ((CAN_TypeDef *)    CAN1_BASE)
+// usb
+#define AC      ((AC_TypeDef *)     AC_BASE)
+#define PWM0    ((PWM_TypeDef *)    PWM0_BASE)
+#define QEI0    ((QEI_TypeDef *)    QEI0_BASE)
+#define QEI1    ((QEI_TypeDef *)    QEI1_BASE)
+
+/**
+ * @}
+ */
+
+#endif /* __TM4C129x_H */
+
+/**
+ * @}
+ */
+ 
+/**
+ * @}
+ */