FSMC. SDRAM. Fixed bug with registers' memory layout

2 files changed, 10 insertions, 12 deletions

diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
index 6ddd566..9ac64f7 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
@@ -164,13 +164,10 @@ typedef struct {
      defined(STM32F429xx) || defined(STM32F439xx))
 
 typedef struct {
-  __IO uint32_t SDCR;         /**< SDRAM control register */
-  uint32_t      RESERVED;     /**< Reserved */
-  __IO uint32_t SDTR;         /**< SDRAM timing register */
-} FSMC_SDRAM_BANK_TypeDef;
-
-typedef struct {
-  FSMC_SDRAM_BANK_TypeDef banks[2]; /**< Banks mapping */
+  __IO uint32_t SDCR1;              /**< SDRAM control register (bank 1) */
+  __IO uint32_t SDCR2;              /**< SDRAM control register (bank 2) */
+  __IO uint32_t SDTR1;              /**< SDRAM timing register (bank 1) */
+  __IO uint32_t SDTR2;              /**< SDRAM timing register (bank 2) */
   __IO uint32_t SDCMR;              /**< SDRAM comand mode register */
   __IO uint32_t SDRTR;              /**< SDRAM refresh timer register */
   __IO uint32_t SDSR;               /**< SDRAM status register */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
index e635323..ed415eb 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
@@ -103,7 +103,7 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
   SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
 
   /* Step 4: Insert delay (tipically 100uS).*/
-  osalSysPolledDelayX(US2RTC(STM32_SYSCLK, 100));
+  osalThreadSleepMilliseconds(100);
 
   /* Step 5: Configure a PALL (precharge all) command.*/
   _sdram_wait_ready();
@@ -115,6 +115,7 @@ static void _sdram_init_sequence(const SDRAMConfig *cfgp) {
       (cfgp->sdcmr & FMC_SDCMR_NRFS);
 
   /* Step 6.2: Send the second command.*/
+  _sdram_wait_ready();
   SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
       (cfgp->sdcmr & FMC_SDCMR_NRFS);
 
@@ -168,10 +169,10 @@ void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
     /* Even if you need only bank2 you must properly set up SDCR and SDTR
        regitsters for bank1 too. Both banks will be tuned equally assuming
        connected memory ICs are equal.*/
-    sdramp->sdram->banks[0].SDCR = cfgp->sdcr;
-    sdramp->sdram->banks[0].SDTR = cfgp->sdtr;
-    sdramp->sdram->banks[1].SDCR = cfgp->sdcr;
-    sdramp->sdram->banks[1].SDTR = cfgp->sdtr;
+    sdramp->sdram->SDCR1 = cfgp->sdcr;
+    sdramp->sdram->SDTR1 = cfgp->sdtr;
+    sdramp->sdram->SDCR2 = cfgp->sdcr;
+    sdramp->sdram->SDTR2 = cfgp->sdtr;
 
     _sdram_init_sequence(cfgp);