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| author | flabbergast <s3+flabbergast@sdfeu.org> | 2016-03-21 19:18:01 +0000 |
|---|---|---|
| committer | flabbergast <s3+flabbergast@sdfeu.org> | 2016-03-21 19:18:01 +0000 |
| commit | 9281b8f751ea63b2fef32e46b8710deef99bf258 (patch) | |
| tree | 850b15bf514a2994c0eb768761aaf7902f98b714 /testhal/KINETIS/I2C/mcuconf.h | |
| parent | 18b41efefaa25be8fec0e89444bcc7b88fa7842e (diff) | |
| parent | c63d6a590810570aa1dfec2d07f5bac1f8d698ad (diff) | |
| download | ChibiOS-Contrib-9281b8f751ea63b2fef32e46b8710deef99bf258.tar.gz ChibiOS-Contrib-9281b8f751ea63b2fef32e46b8710deef99bf258.tar.bz2 ChibiOS-Contrib-9281b8f751ea63b2fef32e46b8710deef99bf258.zip | |
Merge remote-tracking branch 'utzig/kinetis' into kinetis
Diffstat (limited to 'testhal/KINETIS/I2C/mcuconf.h')
| -rw-r--r-- | testhal/KINETIS/I2C/mcuconf.h | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/testhal/KINETIS/I2C/mcuconf.h b/testhal/KINETIS/I2C/mcuconf.h new file mode 100644 index 0000000..c5d56f2 --- /dev/null +++ b/testhal/KINETIS/I2C/mcuconf.h @@ -0,0 +1,76 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+#define K20x_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+
+/* Select the MCU clocking mode below by enabling the appropriate block. */
+
+/* Enable clock initialization by HAL */
+#define KINETIS_NO_INIT FALSE
+
+/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
+#if 1
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#define KINETIS_XTAL_FREQUENCY 8000000UL
+#define KINETIS_SYSCLK_FREQUENCY 48000000UL
+#endif
+
+/* FEI mode - 48 MHz with internal 32.768 kHz oscillator */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#endif /* 0 */
+
+/* FEE mode - 24 MHz with external 32.768 kHz crystal */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
+#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
+#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
+#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
+#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
+#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
+#endif /* 0 */
+
+/* FEE mode - 48 MHz */
+#if 0
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
+#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
+#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
+#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
+#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
+#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
+#endif /* 0 */
+
+/*
+ * SERIAL driver system settings.
+ */
+#define KINETIS_SERIAL_USE_UART0 FALSE
+#define KINETIS_I2C_USE_I2C0 TRUE
+#define KINETIS_I2C_I2C0_PRIORITY 8
+
+#endif /* _MCUCONF_H_ */
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