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authorDiego Ismirlian <dismirlian@gmail.com>2019-08-24 17:45:41 -0300
committerDiego Ismirlian <dismirlian@gmail.com>2019-08-24 17:45:41 -0300
commit7b2c61a676e024163057ec5ccc508a29ab3b9ed4 (patch)
tree5d1f5423a4e720d657681794ac81dc2a2004cbb0 /testhal/NRF52/NRF52832
parent81391097156ce2c9fc71c3350457522841e10095 (diff)
parente346e779339636f578536785014609e46866fb9c (diff)
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Merge branch 'master' of https://github.com/ChibiOS/ChibiOS-Contrib
Diffstat (limited to 'testhal/NRF52/NRF52832')
-rw-r--r--testhal/NRF52/NRF52832/I2C/Makefile207
-rw-r--r--testhal/NRF52/NRF52832/I2C/chconf.h696
-rw-r--r--testhal/NRF52/NRF52832/I2C/halconf.h327
-rw-r--r--testhal/NRF52/NRF52832/I2C/halconf_community.h173
-rw-r--r--testhal/NRF52/NRF52832/I2C/main.c165
-rw-r--r--testhal/NRF52/NRF52832/I2C/mcuconf.h25
-rw-r--r--testhal/NRF52/NRF52832/I2C/readme.txt21
-rw-r--r--testhal/NRF52/NRF52832/PWM-ICU/Makefile228
-rw-r--r--testhal/NRF52/NRF52832/PWM-ICU/chconf.h696
-rw-r--r--testhal/NRF52/NRF52832/PWM-ICU/halconf.h327
-rw-r--r--testhal/NRF52/NRF52832/PWM-ICU/halconf_community.h173
-rw-r--r--testhal/NRF52/NRF52832/PWM-ICU/main.c122
-rw-r--r--testhal/NRF52/NRF52832/PWM-ICU/mcuconf.h33
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/Makefile212
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/chconf.h696
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/halconf.h327
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/halconf_community.h173
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/main.c122
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/mcuconf.h28
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c1111
-rw-r--r--testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h256
21 files changed, 6118 insertions, 0 deletions
diff --git a/testhal/NRF52/NRF52832/I2C/Makefile b/testhal/NRF52/NRF52832/I2C/Makefile
new file mode 100644
index 0000000..edb407e
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/Makefile
@@ -0,0 +1,207 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Licensing files.
+include $(CHIBIOS)/os/license/license.mk
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF52832/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/NRF52-E73-2G4M04S/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+#include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/NRF52832.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(ALLCSRC) \
+ $(TESTSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC = $(ALLCPPSRC)
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(ALLASMSRC)
+ASMXSRC = $(ALLXASMSRC)
+
+INCDIR = $(ALLINC) $(TESTINC) \
+ $(TESTHAL)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/NRF52/NRF52832/I2C/chconf.h b/testhal/NRF52/NRF52832/I2C/chconf.h
new file mode 100644
index 0000000..1750f63
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/chconf.h
@@ -0,0 +1,696 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
+#define _CHIBIOS_RT_CONF_VER_5_1_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(CH_CFG_ST_RESOLUTION)
+#define CH_CFG_ST_RESOLUTION 32
+#endif
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_CFG_ST_FREQUENCY)
+#define CH_CFG_ST_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Time intervals data size.
+ * @note Allowed values are 16, 32 or 64 bits.
+ */
+#if !defined(CH_CFG_INTERVALS_SIZE)
+#define CH_CFG_INTERVALS_SIZE 32
+#endif
+
+/**
+ * @brief Time types data size.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(CH_CFG_TIME_TYPES_SIZE)
+#define CH_CFG_TIME_TYPES_SIZE 32
+#endif
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#if !defined(CH_CFG_ST_TIMEDELTA)
+#define CH_CFG_ST_TIMEDELTA 0
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#if !defined(CH_CFG_TIME_QUANTUM)
+#define CH_CFG_TIME_QUANTUM 2
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#if !defined(CH_CFG_MEMCORE_SIZE)
+#define CH_CFG_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#if !defined(CH_CFG_NO_IDLE_THREAD)
+#define CH_CFG_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_OPTIMIZE_SPEED)
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_TM)
+#define CH_CFG_USE_TM FALSE
+#endif
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_REGISTRY)
+#define CH_CFG_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_WAITEXIT)
+#define CH_CFG_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_SEMAPHORES)
+#define CH_CFG_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MUTEXES)
+#define CH_CFG_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#if !defined(CH_CFG_USE_CONDVARS)
+#define CH_CFG_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_EVENTS)
+#define CH_CFG_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MESSAGES)
+#define CH_CFG_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#if !defined(CH_CFG_USE_MAILBOXES)
+#define CH_CFG_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMCORE)
+#define CH_CFG_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_CFG_USE_HEAP)
+#define CH_CFG_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMPOOLS)
+#define CH_CFG_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Objects FIFOs APIs.
+ * @details If enabled then the objects FIFOs APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_OBJ_FIFOS)
+#define CH_CFG_USE_OBJ_FIFOS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#if !defined(CH_CFG_USE_DYNAMIC)
+#define CH_CFG_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Objects factory options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Objects Factory APIs.
+ * @details If enabled then the objects factory APIs are included in the
+ * kernel.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_CFG_USE_FACTORY)
+#define CH_CFG_USE_FACTORY TRUE
+#endif
+
+/**
+ * @brief Maximum length for object names.
+ * @details If the specified length is zero then the name is stored by
+ * pointer but this could have unintended side effects.
+ */
+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
+#endif
+
+/**
+ * @brief Enables the registry of generic objects.
+ */
+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Enables factory for generic buffers.
+ */
+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
+#endif
+
+/**
+ * @brief Enables factory for semaphores.
+ */
+#if !defined(CH_CFG_FACTORY_SEMAPHORES)
+#define CH_CFG_FACTORY_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Enables factory for mailboxes.
+ */
+#if !defined(CH_CFG_FACTORY_MAILBOXES)
+#define CH_CFG_FACTORY_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief Enables factory for objects FIFOs.
+ */
+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_STATISTICS)
+#define CH_DBG_STATISTICS FALSE
+#endif
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS)
+#define CH_DBG_ENABLE_CHECKS TRUE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS)
+#define CH_DBG_ENABLE_ASSERTS TRUE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the trace buffer is activated.
+ *
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_MASK)
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
+#endif
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
+#define CH_DBG_TRACE_BUFFER_SIZE 128
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK)
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS)
+#define CH_DBG_FILL_THREADS TRUE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING)
+#define CH_DBG_THREADS_PROFILING FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System structure extension.
+ * @details User fields added to the end of the @p ch_system_t structure.
+ */
+#define CH_CFG_SYSTEM_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief System initialization hook.
+ * @details User initialization code added to the @p chSysInit() function
+ * just before interrupts are enabled globally.
+ */
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p _thread_init() function.
+ *
+ * @note It is invoked from within @p _thread_init() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* CHCONF_H */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/I2C/halconf.h b/testhal/NRF52/NRF52832/I2C/halconf.h
new file mode 100644
index 0000000..1c3036a
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/halconf.h
@@ -0,0 +1,327 @@
+/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C TRUE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/I2C/halconf_community.h b/testhal/NRF52/NRF52832/I2C/halconf_community.h
new file mode 100644
index 0000000..43fdbf8
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/halconf_community.h
@@ -0,0 +1,173 @@
+/*
+ ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
+
+/**
+ * @brief Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY TRUE
+#endif
+
+/**
+ * @brief Enables the FSMC subsystem.
+ */
+#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
+#define HAL_USE_FSMC FALSE
+#endif
+
+/**
+ * @brief Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND FALSE
+#endif
+
+/**
+ * @brief Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE FALSE
+#endif
+
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
+/**
+ * @brief Enables the CRC subsystem.
+ */
+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
+#define HAL_USE_CRC FALSE
+#endif
+
+/**
+ * @brief Enables the RNG subsystem.
+ */
+#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
+#define HAL_USE_RNG FALSE
+#endif
+
+/**
+ * @brief Enables the EEPROM subsystem.
+ */
+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
+#define HAL_USE_EEPROM FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
+#define HAL_USE_TIMCAP FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
+#define HAL_USE_COMP FALSE
+#endif
+
+/**
+ * @brief Enables the QEI subsystem.
+ */
+#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
+#define HAL_USE_QEI FALSE
+#endif
+
+/**
+ * @brief Enables the USBH subsystem.
+ */
+#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
+#define HAL_USE_USBH FALSE
+#endif
+
+/**
+ * @brief Enables the USB_MSD subsystem.
+ */
+#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
+#define HAL_USE_USB_MSD FALSE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings. */
+/*===========================================================================*/
+/**
+ * @brief Enables strong pull up feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP FALSE
+
+/**
+ * @brief Enables search ROM feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM TRUE
+
+/*===========================================================================*/
+/* QEI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables discard of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_DISCARD FALSE
+#endif
+
+/**
+ * @brief Enables min max of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_MINMAX FALSE
+#endif
+
+/*===========================================================================*/
+/* EEProm driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables 24xx series I2C eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE24XX FALSE
+ /**
+ * @brief Enables 25xx series SPI eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE25XX FALSE
+
+#endif /* HALCONF_COMMUNITY_H */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/I2C/main.c b/testhal/NRF52/NRF52832/I2C/main.c
new file mode 100644
index 0000000..88fb1e8
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/main.c
@@ -0,0 +1,165 @@
+/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ This demo:
+ 1) Writes bytes to the EEPROM
+ 2) Reads the same bytes back
+ 3) Inverts the byte values
+ 4) Writes them
+ 5) Reads them back
+ */
+
+#include <stdlib.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#define I2C_ADDR 0x50
+#define I2C_FAKE_ADDR 0x4C
+#define EEPROM_START_ADDR 0x00
+
+/*
+ * EEPROM thread.
+ */
+static THD_WORKING_AREA(PollEepromThreadWA, 1024);
+static THD_FUNCTION(PollEepromThread, arg) {
+
+ unsigned i;
+ uint8_t tx_data[6];
+ uint8_t rx_data[4];
+ msg_t status;
+
+ (void)arg;
+
+ chRegSetThreadName("PollEeprom");
+
+ /* set initial data to write */
+ tx_data[0] = EEPROM_START_ADDR;
+ tx_data[1] = EEPROM_START_ADDR;
+ tx_data[2] = 0xA0;
+ tx_data[3] = 0xA1;
+ tx_data[4] = 0xA2;
+ tx_data[5] = 0xA3;
+
+ while (true) {
+
+ /* write out initial data */
+ i2cAcquireBus(&I2CD1);
+ status = i2cMasterTransmitTimeout(&I2CD1, I2C_ADDR, tx_data, sizeof(tx_data), NULL, 0, TIME_INFINITE);
+ i2cReleaseBus(&I2CD1);
+ osalDbgCheck(MSG_OK == status);
+
+ /* read back inital data */
+ osalThreadSleepMilliseconds(2);
+ i2cAcquireBus(&I2CD1);
+ status = i2cMasterTransmitTimeout(&I2CD1, I2C_ADDR, tx_data, 2, rx_data, sizeof(rx_data), TIME_INFINITE);
+ i2cReleaseBus(&I2CD1);
+ osalDbgCheck(MSG_OK == status);
+
+ /* invert the data */
+ for (i = 2; i < sizeof(tx_data); i++)
+ tx_data[i] ^= 0xff;
+
+ /* write out inverted data */
+ osalThreadSleepMilliseconds(2);
+ i2cAcquireBus(&I2CD1);
+ status = i2cMasterTransmitTimeout(&I2CD1, I2C_ADDR, tx_data, sizeof(tx_data), NULL, 0, TIME_INFINITE);
+ i2cReleaseBus(&I2CD1);
+ osalDbgCheck(MSG_OK == status);
+
+ /* read back inverted data */
+ osalThreadSleepMilliseconds(2);
+ i2cAcquireBus(&I2CD1);
+ status = i2cMasterTransmitTimeout(&I2CD1, I2C_ADDR, tx_data, 2, rx_data, sizeof(rx_data), TIME_INFINITE);
+ i2cReleaseBus(&I2CD1);
+ osalDbgCheck(MSG_OK == status);
+
+ osalThreadSleepMilliseconds(TIME_INFINITE);
+ }
+}
+
+/*
+ * Fake polling thread.
+ */
+static THD_WORKING_AREA(PollFakeThreadWA, 256);
+static THD_FUNCTION(PollFakeThread, arg) {
+
+ (void)arg;
+
+ chRegSetThreadName("PollFake");
+ while (true) {
+
+ msg_t status;
+ uint8_t rx_data[2];
+ i2cflags_t errors;
+
+ i2cAcquireBus(&I2CD1);
+ status = i2cMasterReceiveTimeout(&I2CD1, I2C_FAKE_ADDR, rx_data, 2, TIME_MS2I(4));
+ i2cReleaseBus(&I2CD1);
+
+ if (status == MSG_RESET){
+ errors = i2cGetErrors(&I2CD1);
+ osalDbgCheck(I2C_ACK_FAILURE == errors);
+ }
+
+ palTogglePad(IOPORT1, LED1); /* on */
+ osalThreadSleepMilliseconds(1000);
+ }
+}
+
+/*
+ * I2C1 config.
+ */
+static const I2CConfig i2cfg = {
+ 100000,
+ I2C_SCL,
+ I2C_SDA,
+};
+
+/*
+ * Entry point, note, the main() function is already a thread in the system
+ * on entry.
+ */
+int main(void) {
+
+ halInit();
+ chSysInit();
+
+ i2cStart(&I2CD1, &i2cfg);
+
+ /* Create EEPROM thread. */
+ chThdCreateStatic(PollEepromThreadWA,
+ sizeof(PollEepromThreadWA),
+ NORMALPRIO,
+ PollEepromThread,
+ NULL);
+
+ /* Create not responding thread. */
+ chThdCreateStatic(PollFakeThreadWA,
+ sizeof(PollFakeThreadWA),
+ NORMALPRIO,
+ PollFakeThread,
+ NULL);
+
+ /* main loop handles LED */
+ while (true) {
+ palTogglePad(IOPORT1, LED2); /* on */
+ osalThreadSleepMilliseconds(500);
+ }
+
+ return 0;
+}
diff --git a/testhal/NRF52/NRF52832/I2C/mcuconf.h b/testhal/NRF52/NRF52832/I2C/mcuconf.h
new file mode 100644
index 0000000..fd238a2
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/mcuconf.h
@@ -0,0 +1,25 @@
+/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * HAL driver system settings.
+ */
+#define NRF5_I2C_USE_I2C0 TRUE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/NRF52/NRF52832/I2C/readme.txt b/testhal/NRF52/NRF52832/I2C/readme.txt
new file mode 100644
index 0000000..281bd3e
--- /dev/null
+++ b/testhal/NRF52/NRF52832/I2C/readme.txt
@@ -0,0 +1,21 @@
+*****************************************************************************
+** ChibiOS/HAL - I2C driver demo for NRF52832. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an EByte E73-2G4M04S board.
+
+** The Demo **
+
+The application demonstrates the use of the NRF52832 I2C driver.
+
+** Board Setup **
+
+- Connect AT24CXX EEPROM board to I2C port on E73-2G4M04S board
+
+** Build Procedure **
+
+The demo has been tested using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
diff --git a/testhal/NRF52/NRF52832/PWM-ICU/Makefile b/testhal/NRF52/NRF52832/PWM-ICU/Makefile
new file mode 100644
index 0000000..237bcbe
--- /dev/null
+++ b/testhal/NRF52/NRF52832/PWM-ICU/Makefile
@@ -0,0 +1,228 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
+# Licensing files.
+include $(CHIBIOS)/os/license/license.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF52832/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/NRF52-E73-2G4M04S/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+#include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/NRF52832.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(ALLCSRC) \
+ $(TESTSRC) \
+ $(CHIBIOS)/os/hal/lib/streams/memstreams.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC = $(ALLCPPSRC)
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(ALLASMSRC)
+ASMXSRC = $(ALLXASMSRC)
+
+INCDIR = $(ALLINC) $(TESTINC) \
+ $(CHIBIOS)/os/hal/lib/streams \
+ $(TESTHAL)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
+
+
+include $(CHIBIOS_CONTRIB)/os/various/jlink.mk
+
+
+JLINK_DEVICE = nrf51422
+JLINK_PRE_FLASH = w4 4001e504 1
+JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
+
+flash: all jlink-flash
+
diff --git a/testhal/NRF52/NRF52832/PWM-ICU/chconf.h b/testhal/NRF52/NRF52832/PWM-ICU/chconf.h
new file mode 100644
index 0000000..1750f63
--- /dev/null
+++ b/testhal/NRF52/NRF52832/PWM-ICU/chconf.h
@@ -0,0 +1,696 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
+#define _CHIBIOS_RT_CONF_VER_5_1_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(CH_CFG_ST_RESOLUTION)
+#define CH_CFG_ST_RESOLUTION 32
+#endif
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_CFG_ST_FREQUENCY)
+#define CH_CFG_ST_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Time intervals data size.
+ * @note Allowed values are 16, 32 or 64 bits.
+ */
+#if !defined(CH_CFG_INTERVALS_SIZE)
+#define CH_CFG_INTERVALS_SIZE 32
+#endif
+
+/**
+ * @brief Time types data size.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(CH_CFG_TIME_TYPES_SIZE)
+#define CH_CFG_TIME_TYPES_SIZE 32
+#endif
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#if !defined(CH_CFG_ST_TIMEDELTA)
+#define CH_CFG_ST_TIMEDELTA 0
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#if !defined(CH_CFG_TIME_QUANTUM)
+#define CH_CFG_TIME_QUANTUM 2
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#if !defined(CH_CFG_MEMCORE_SIZE)
+#define CH_CFG_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#if !defined(CH_CFG_NO_IDLE_THREAD)
+#define CH_CFG_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_OPTIMIZE_SPEED)
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_TM)
+#define CH_CFG_USE_TM FALSE
+#endif
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_REGISTRY)
+#define CH_CFG_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_WAITEXIT)
+#define CH_CFG_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_SEMAPHORES)
+#define CH_CFG_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MUTEXES)
+#define CH_CFG_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#if !defined(CH_CFG_USE_CONDVARS)
+#define CH_CFG_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_EVENTS)
+#define CH_CFG_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MESSAGES)
+#define CH_CFG_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#if !defined(CH_CFG_USE_MAILBOXES)
+#define CH_CFG_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMCORE)
+#define CH_CFG_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_CFG_USE_HEAP)
+#define CH_CFG_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMPOOLS)
+#define CH_CFG_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Objects FIFOs APIs.
+ * @details If enabled then the objects FIFOs APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_OBJ_FIFOS)
+#define CH_CFG_USE_OBJ_FIFOS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#if !defined(CH_CFG_USE_DYNAMIC)
+#define CH_CFG_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Objects factory options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Objects Factory APIs.
+ * @details If enabled then the objects factory APIs are included in the
+ * kernel.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_CFG_USE_FACTORY)
+#define CH_CFG_USE_FACTORY TRUE
+#endif
+
+/**
+ * @brief Maximum length for object names.
+ * @details If the specified length is zero then the name is stored by
+ * pointer but this could have unintended side effects.
+ */
+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
+#endif
+
+/**
+ * @brief Enables the registry of generic objects.
+ */
+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Enables factory for generic buffers.
+ */
+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
+#endif
+
+/**
+ * @brief Enables factory for semaphores.
+ */
+#if !defined(CH_CFG_FACTORY_SEMAPHORES)
+#define CH_CFG_FACTORY_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Enables factory for mailboxes.
+ */
+#if !defined(CH_CFG_FACTORY_MAILBOXES)
+#define CH_CFG_FACTORY_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief Enables factory for objects FIFOs.
+ */
+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_STATISTICS)
+#define CH_DBG_STATISTICS FALSE
+#endif
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS)
+#define CH_DBG_ENABLE_CHECKS TRUE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS)
+#define CH_DBG_ENABLE_ASSERTS TRUE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the trace buffer is activated.
+ *
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_MASK)
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
+#endif
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
+#define CH_DBG_TRACE_BUFFER_SIZE 128
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK)
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS)
+#define CH_DBG_FILL_THREADS TRUE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING)
+#define CH_DBG_THREADS_PROFILING FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System structure extension.
+ * @details User fields added to the end of the @p ch_system_t structure.
+ */
+#define CH_CFG_SYSTEM_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief System initialization hook.
+ * @details User initialization code added to the @p chSysInit() function
+ * just before interrupts are enabled globally.
+ */
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p _thread_init() function.
+ *
+ * @note It is invoked from within @p _thread_init() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* CHCONF_H */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/PWM-ICU/halconf.h b/testhal/NRF52/NRF52832/PWM-ICU/halconf.h
new file mode 100644
index 0000000..6674ab5
--- /dev/null
+++ b/testhal/NRF52/NRF52832/PWM-ICU/halconf.h
@@ -0,0 +1,327 @@
+/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU TRUE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM TRUE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/PWM-ICU/halconf_community.h b/testhal/NRF52/NRF52832/PWM-ICU/halconf_community.h
new file mode 100644
index 0000000..43fdbf8
--- /dev/null
+++ b/testhal/NRF52/NRF52832/PWM-ICU/halconf_community.h
@@ -0,0 +1,173 @@
+/*
+ ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
+
+/**
+ * @brief Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY TRUE
+#endif
+
+/**
+ * @brief Enables the FSMC subsystem.
+ */
+#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
+#define HAL_USE_FSMC FALSE
+#endif
+
+/**
+ * @brief Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND FALSE
+#endif
+
+/**
+ * @brief Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE FALSE
+#endif
+
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
+/**
+ * @brief Enables the CRC subsystem.
+ */
+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
+#define HAL_USE_CRC FALSE
+#endif
+
+/**
+ * @brief Enables the RNG subsystem.
+ */
+#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
+#define HAL_USE_RNG FALSE
+#endif
+
+/**
+ * @brief Enables the EEPROM subsystem.
+ */
+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
+#define HAL_USE_EEPROM FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
+#define HAL_USE_TIMCAP FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
+#define HAL_USE_COMP FALSE
+#endif
+
+/**
+ * @brief Enables the QEI subsystem.
+ */
+#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
+#define HAL_USE_QEI FALSE
+#endif
+
+/**
+ * @brief Enables the USBH subsystem.
+ */
+#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
+#define HAL_USE_USBH FALSE
+#endif
+
+/**
+ * @brief Enables the USB_MSD subsystem.
+ */
+#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
+#define HAL_USE_USB_MSD FALSE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings. */
+/*===========================================================================*/
+/**
+ * @brief Enables strong pull up feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP FALSE
+
+/**
+ * @brief Enables search ROM feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM TRUE
+
+/*===========================================================================*/
+/* QEI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables discard of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_DISCARD FALSE
+#endif
+
+/**
+ * @brief Enables min max of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_MINMAX FALSE
+#endif
+
+/*===========================================================================*/
+/* EEProm driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables 24xx series I2C eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE24XX FALSE
+ /**
+ * @brief Enables 25xx series SPI eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE25XX FALSE
+
+#endif /* HALCONF_COMMUNITY_H */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/PWM-ICU/main.c b/testhal/NRF52/NRF52832/PWM-ICU/main.c
new file mode 100644
index 0000000..6ad8a4c
--- /dev/null
+++ b/testhal/NRF52/NRF52832/PWM-ICU/main.c
@@ -0,0 +1,122 @@
+/*
+ Copyright (C) 2018 andru
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "chprintf.h"
+
+static icucnt_t last_width, last_period;
+
+static SerialConfig serial_config = {
+ .speed = 38400,
+ .tx_pad = UART_TX,
+ .rx_pad = UART_RX,
+#if NRF5_SERIAL_USE_HWFLOWCTRL == TRUE
+ .rts_pad = UART_RTS,
+ .cts_pad = UART_CTS,
+#endif
+};
+
+static void pwm_cb_period(PWMDriver *pwmp) {
+ (void)pwmp;
+ palTogglePad(IOPORT1, LED1);
+}
+
+void icu_width_cb(ICUDriver *icup) {
+ last_width = icuGetWidthX(icup);
+}
+
+void icu_period_cb(ICUDriver *icup) {
+ last_period = icuGetPeriodX(icup);
+}
+
+ICUConfig icucfg = {
+ .frequency = ICU_FREQUENCY_250KHZ,
+ .width_cb = icu_width_cb,
+ .period_cb = icu_period_cb,
+ NULL,
+ .iccfgp = {
+ {
+ .ioline = { BTN1, BTN2 },
+ .mode = ICU_INPUT_ACTIVE_HIGH,
+ .gpiote_channel = { 0, 1 },
+ .ppi_channel = { 0, 1 },
+ },
+ },
+};
+
+PWMConfig pwmcfg = {
+ .frequency = PWM_FREQUENCY_125KHZ,
+ .period = 12500,
+ .callback = pwm_cb_period,
+ {
+ { .mode = PWM_OUTPUT_DISABLED,
+ },
+ { .mode = PWM_OUTPUT_ACTIVE_HIGH,
+ .ioline = LINE_LED2,
+ },
+ },
+};
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ sdStart(&SD1, &serial_config);
+
+ /*
+ *
+ */
+ pwmStart(&PWMD1, &pwmcfg);
+ pwmEnablePeriodicNotification(&PWMD1);
+
+ icuStart(&ICUD1, &icucfg);
+ icuStartCapture(&ICUD1);
+
+ pwmEnableChannel(&PWMD1, 1, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 2500)); // 25%
+ chThdSleepMilliseconds(5000);
+ chprintf((BaseSequentialStream *) &SD1, "period=%d, width=%d\r\n", last_period, last_width);
+
+ pwmEnableChannel(&PWMD1, 1, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 5000)); // 50%
+ chThdSleepMilliseconds(5000);
+ chprintf((BaseSequentialStream *) &SD1, "period=%d, width=%d\r\n", last_period, last_width);
+
+ pwmEnableChannel(&PWMD1, 1, PWM_PERCENTAGE_TO_WIDTH(&PWMD1, 7500)); // 75%
+ chThdSleepMilliseconds(5000);
+ chprintf((BaseSequentialStream *) &SD1, "period=%d, width=%d\r\n", last_period, last_width);
+
+ pwmChangePeriod(&PWMD1, 5000);
+ chThdSleepMilliseconds(5000);
+
+ pwmDisableChannel(&PWMD1, 1);
+ pwmStop(&PWMD1);
+ icuStopCapture(&ICUD1);
+ icuStop(&ICUD1);
+
+ while (true) {
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/testhal/NRF52/NRF52832/PWM-ICU/mcuconf.h b/testhal/NRF52/NRF52832/PWM-ICU/mcuconf.h
new file mode 100644
index 0000000..e2fbdb8
--- /dev/null
+++ b/testhal/NRF52/NRF52832/PWM-ICU/mcuconf.h
@@ -0,0 +1,33 @@
+/*
+ Copyright (C) 2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * HAL driver system settings.
+ */
+#define NRF5_SERIAL_USE_UART0 TRUE
+#define NRF5_ST_USE_RTC0 TRUE
+#define NRF5_ST_USE_RTC1 FALSE
+#define NRF5_ST_USE_TIMER0 FALSE
+#define NRF5_PWM_USE_PWM0 TRUE
+#define NRF5_PWM_PWM0_PRIORITY 6
+#define NRF5_ICU_USE_TIMER0 TRUE
+#define NRF5_ICU_GPIOTE_IRQ_PRIORITY 4
+#define NRF5_ICU_TIMER0_IRQ_PRIORITY 4
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/Makefile b/testhal/NRF52/NRF52832/RADIO-ESB/Makefile
new file mode 100644
index 0000000..a01eb88
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/Makefile
@@ -0,0 +1,212 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU on Cortex-M4 (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../../../../ChibiOS
+CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib
+# Licensing files.
+include $(CHIBIOS)/os/license/license.mk
+# Startup files.
+include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/NRF5/NRF52832/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/boards/NRF52-E73-2G4M04S/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+#include $(CHIBIOS)/test/rt/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/NRF52832.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(ALLCSRC) \
+ $(TESTSRC) \
+ $(CHIBIOS)/os/various/syscalls.c \
+ $(CHIBIOS)/os/hal/lib/streams/memstreams.c \
+ $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
+ nrf52_radio.c \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC = $(ALLCPPSRC)
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(ALLASMSRC)
+ASMXSRC = $(ALLXASMSRC)
+
+INCDIR = $(ALLINC) $(TESTINC) \
+ $(CHIBIOS)/os/hal/lib/streams \
+ $(TESTHAL)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+SREC = $(CP) -O srec
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/chconf.h b/testhal/NRF52/NRF52832/RADIO-ESB/chconf.h
new file mode 100644
index 0000000..1750f63
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/chconf.h
@@ -0,0 +1,696 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
+#define _CHIBIOS_RT_CONF_VER_5_1_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(CH_CFG_ST_RESOLUTION)
+#define CH_CFG_ST_RESOLUTION 32
+#endif
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_CFG_ST_FREQUENCY)
+#define CH_CFG_ST_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Time intervals data size.
+ * @note Allowed values are 16, 32 or 64 bits.
+ */
+#if !defined(CH_CFG_INTERVALS_SIZE)
+#define CH_CFG_INTERVALS_SIZE 32
+#endif
+
+/**
+ * @brief Time types data size.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#if !defined(CH_CFG_TIME_TYPES_SIZE)
+#define CH_CFG_TIME_TYPES_SIZE 32
+#endif
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#if !defined(CH_CFG_ST_TIMEDELTA)
+#define CH_CFG_ST_TIMEDELTA 0
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#if !defined(CH_CFG_TIME_QUANTUM)
+#define CH_CFG_TIME_QUANTUM 2
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#if !defined(CH_CFG_MEMCORE_SIZE)
+#define CH_CFG_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#if !defined(CH_CFG_NO_IDLE_THREAD)
+#define CH_CFG_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_OPTIMIZE_SPEED)
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_TM)
+#define CH_CFG_USE_TM FALSE
+#endif
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_REGISTRY)
+#define CH_CFG_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_WAITEXIT)
+#define CH_CFG_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_SEMAPHORES)
+#define CH_CFG_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MUTEXES)
+#define CH_CFG_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#if !defined(CH_CFG_USE_CONDVARS)
+#define CH_CFG_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_EVENTS)
+#define CH_CFG_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MESSAGES)
+#define CH_CFG_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#if !defined(CH_CFG_USE_MAILBOXES)
+#define CH_CFG_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMCORE)
+#define CH_CFG_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_CFG_USE_HEAP)
+#define CH_CFG_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_MEMPOOLS)
+#define CH_CFG_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Objects FIFOs APIs.
+ * @details If enabled then the objects FIFOs APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_CFG_USE_OBJ_FIFOS)
+#define CH_CFG_USE_OBJ_FIFOS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#if !defined(CH_CFG_USE_DYNAMIC)
+#define CH_CFG_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Objects factory options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Objects Factory APIs.
+ * @details If enabled then the objects factory APIs are included in the
+ * kernel.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_CFG_USE_FACTORY)
+#define CH_CFG_USE_FACTORY TRUE
+#endif
+
+/**
+ * @brief Maximum length for object names.
+ * @details If the specified length is zero then the name is stored by
+ * pointer but this could have unintended side effects.
+ */
+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
+#endif
+
+/**
+ * @brief Enables the registry of generic objects.
+ */
+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Enables factory for generic buffers.
+ */
+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
+#endif
+
+/**
+ * @brief Enables factory for semaphores.
+ */
+#if !defined(CH_CFG_FACTORY_SEMAPHORES)
+#define CH_CFG_FACTORY_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Enables factory for mailboxes.
+ */
+#if !defined(CH_CFG_FACTORY_MAILBOXES)
+#define CH_CFG_FACTORY_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief Enables factory for objects FIFOs.
+ */
+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_STATISTICS)
+#define CH_DBG_STATISTICS FALSE
+#endif
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS)
+#define CH_DBG_ENABLE_CHECKS TRUE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS)
+#define CH_DBG_ENABLE_ASSERTS TRUE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the trace buffer is activated.
+ *
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_MASK)
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL
+#endif
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
+#define CH_DBG_TRACE_BUFFER_SIZE 128
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK)
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS)
+#define CH_DBG_FILL_THREADS TRUE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING)
+#define CH_DBG_THREADS_PROFILING FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System structure extension.
+ * @details User fields added to the end of the @p ch_system_t structure.
+ */
+#define CH_CFG_SYSTEM_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief System initialization hook.
+ * @details User initialization code added to the @p chSysInit() function
+ * just before interrupts are enabled globally.
+ */
+#define CH_CFG_SYSTEM_INIT_HOOK() { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p _thread_init() function.
+ *
+ * @note It is invoked from within @p _thread_init() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* CHCONF_H */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/halconf.h b/testhal/NRF52/NRF52832/RADIO-ESB/halconf.h
new file mode 100644
index 0000000..d7d0f43
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/halconf.h
@@ -0,0 +1,327 @@
+/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/halconf_community.h b/testhal/NRF52/NRF52832/RADIO-ESB/halconf_community.h
new file mode 100644
index 0000000..43fdbf8
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/halconf_community.h
@@ -0,0 +1,173 @@
+/*
+ ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
+
+/**
+ * @brief Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY TRUE
+#endif
+
+/**
+ * @brief Enables the FSMC subsystem.
+ */
+#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
+#define HAL_USE_FSMC FALSE
+#endif
+
+/**
+ * @brief Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND FALSE
+#endif
+
+/**
+ * @brief Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE FALSE
+#endif
+
+/**
+ * @brief Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU FALSE
+#endif
+
+/**
+ * @brief Enables the CRC subsystem.
+ */
+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
+#define HAL_USE_CRC FALSE
+#endif
+
+/**
+ * @brief Enables the RNG subsystem.
+ */
+#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
+#define HAL_USE_RNG FALSE
+#endif
+
+/**
+ * @brief Enables the EEPROM subsystem.
+ */
+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
+#define HAL_USE_EEPROM FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
+#define HAL_USE_TIMCAP FALSE
+#endif
+
+/**
+ * @brief Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
+#define HAL_USE_COMP FALSE
+#endif
+
+/**
+ * @brief Enables the QEI subsystem.
+ */
+#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
+#define HAL_USE_QEI FALSE
+#endif
+
+/**
+ * @brief Enables the USBH subsystem.
+ */
+#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
+#define HAL_USE_USBH FALSE
+#endif
+
+/**
+ * @brief Enables the USB_MSD subsystem.
+ */
+#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
+#define HAL_USE_USB_MSD FALSE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings. */
+/*===========================================================================*/
+/**
+ * @brief Enables strong pull up feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP FALSE
+
+/**
+ * @brief Enables search ROM feature.
+ * @note Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM TRUE
+
+/*===========================================================================*/
+/* QEI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables discard of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_DISCARD FALSE
+#endif
+
+/**
+ * @brief Enables min max of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_MINMAX FALSE
+#endif
+
+/*===========================================================================*/
+/* EEProm driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables 24xx series I2C eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE24XX FALSE
+ /**
+ * @brief Enables 25xx series SPI eeprom device driver.
+ * @note Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE25XX FALSE
+
+#endif /* HALCONF_COMMUNITY_H */
+
+/** @} */
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/main.c b/testhal/NRF52/NRF52832/RADIO-ESB/main.c
new file mode 100644
index 0000000..8971fef
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/main.c
@@ -0,0 +1,122 @@
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "ch.h"
+#include "hal.h"
+#include "chprintf.h"
+
+#include "nrf52_radio.h"
+
+static SerialConfig serial_config = {
+ .speed = 38400,
+ .tx_pad = UART_TX,
+ .rx_pad = UART_RX,
+#if NRF5_SERIAL_USE_HWFLOWCTRL == TRUE
+ .rts_pad = UART_RTS,
+ .cts_pad = UART_CTS,
+#endif
+};
+
+static THD_WORKING_AREA(waLEDThread, 64);
+static THD_FUNCTION(LEDThread, arg) {
+ (void)arg;
+
+ chRegSetThreadName("blinker");
+ palSetPadMode(IOPORT1, LED1, PAL_MODE_OUTPUT_PUSHPULL);
+
+ while (1) {
+ palTogglePad(IOPORT1, LED1);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+static nrf52_config_t radiocfg = {
+ .protocol = NRF52_PROTOCOL_ESB_DPL,
+ .mode = NRF52_MODE_PRX,
+ .bitrate = NRF52_BITRATE_1MBPS,
+ .crc = NRF52_CRC_8BIT,
+ .tx_power = NRF52_TX_POWER_0DBM,
+ .tx_mode = NRF52_TXMODE_MANUAL_START,
+ .selective_auto_ack = false,
+ .retransmit = { 1000, 3 },
+ .payload_length = 0,
+ .address = {
+ .base_addr_p0 = { 0xF3, 0xF3, 0xF3, 0x01 },
+ .base_addr_p1 = { 0x3F, 0x3F, 0x3F, 0x01 },
+ .pipe_prefixes = { 0xF3, 0x3F, },
+ .num_pipes = 2,
+ .addr_length = 5,
+ .rx_pipes = 1 << 0,
+ .rf_channel = 1,
+ },
+};
+
+static uint16_t cnt, fail_pkt, good_pkt;
+static nrf52_payload_t tx_payload = {
+ .pipe = 1,
+};
+static nrf52_payload_t rx_payload;
+
+static THD_WORKING_AREA(waRadioThread, 256);
+static THD_FUNCTION(RadioThread, arg) {
+ (void)arg;
+
+ event_listener_t el;
+ chEvtRegisterMask(&RFD1.eventsrc, &el, EVENT_MASK(0));
+
+ chRegSetThreadName("radio");
+
+ while (1) {
+ chEvtWaitAny(EVENT_MASK(0));
+ eventflags_t flags = chEvtGetAndClearFlags(&el);
+ if (flags & NRF52_EVENT_TX_SUCCESS) {
+ radio_start_rx();
+ good_pkt++;
+ }
+ if (flags & NRF52_EVENT_TX_FAILED) {
+ radio_start_rx();
+ fail_pkt++;
+ }
+ if (flags & NRF52_EVENT_RX_RECEIVED) {
+ memset(rx_payload.data, 0, 32);
+ radio_read_rx_payload(&rx_payload);
+ }
+ }
+}
+
+/**@brief Function for application main entry.
+ */
+int main(void) {
+
+ halInit();
+ chSysInit();
+
+ sdStart(&SD1, &serial_config);
+
+ chThdCreateStatic(waLEDThread, sizeof(waLEDThread), NORMALPRIO, LEDThread, NULL);
+ chThdCreateStatic(waRadioThread, sizeof(waRadioThread), NORMALPRIO, RadioThread, NULL);
+
+ radio_init(&radiocfg);
+ radio_flush_tx();
+ radio_flush_rx();
+ radio_start_rx();
+
+ cnt = good_pkt = fail_pkt = 0;
+
+ while (true) {
+ memset(tx_payload.data, 0, 32);
+ sprintf((char*)tx_payload.data, "counter value=%d" , cnt++);
+ tx_payload.length = strlen((char *)tx_payload.data);
+ radio_stop_rx();
+ radio_write_payload(&tx_payload);
+ radio_start_tx();
+ chprintf((BaseSequentialStream *)&SD1, "packets: good=%d, fail=%d, sent=%s\r\n", good_pkt, fail_pkt, tx_payload.data);
+ chThdSleepMilliseconds(500);
+ if (strlen((char*) rx_payload.data)) {
+ chprintf((BaseSequentialStream *)&SD1, "rssi=%d, received=%s\r\n", rx_payload.rssi, rx_payload.data);
+ rx_payload.data[0] = 0;
+ }
+ }
+}
+
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/mcuconf.h b/testhal/NRF52/NRF52832/RADIO-ESB/mcuconf.h
new file mode 100644
index 0000000..1ba934e
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/mcuconf.h
@@ -0,0 +1,28 @@
+/*
+ Copyright (C) 2015 Stephen Caudle
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * HAL driver system settings.
+ */
+#define NRF5_SERIAL_USE_UART0 TRUE
+#define NRF5_ST_USE_RTC0 TRUE
+#define NRF5_ST_USE_RTC1 FALSE
+#define NRF5_ST_USE_TIMER0 FALSE
+
+#endif /* _MCUCONF_H_ */
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c
new file mode 100644
index 0000000..e55870f
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.c
@@ -0,0 +1,1111 @@
+/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ * Enhanced ShockBurst proprietary protocol to ChibiOS port
+ *
+ * ported on: 25/10/2018, by andru
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#include "nrf52_radio.h"
+
+
+#define BIT_MASK_UINT_8(x) (0xFF >> (8 - (x)))
+#define NRF52_PIPE_COUNT 9
+
+#define RADIO_SHORTS_COMMON ( RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk | \
+ RADIO_SHORTS_ADDRESS_RSSISTART_Msk | RADIO_SHORTS_DISABLED_RSSISTOP_Msk )
+
+// Constant parameters
+#define RX_WAIT_FOR_ACK_TIMEOUT_US_2MBPS (48) /**< 2MBit RX wait for ack timeout value. Smallest reliable value - 43 */
+#define RX_WAIT_FOR_ACK_TIMEOUT_US_1MBPS (64) /**< 1MBit RX wait for ack timeout value. Smallest reliable value - 59 */
+
+#define NRF52_ADDR_UPDATE_MASK_BASE0 (1 << 0) /*< Mask value to signal updating BASE0 radio address. */
+#define NRF52_ADDR_UPDATE_MASK_BASE1 (1 << 1) /*< Mask value to signal updating BASE1 radio address. */
+#define NRF52_ADDR_UPDATE_MASK_PREFIX (1 << 2) /*< Mask value to signal updating radio prefixes */
+
+#define NRF52_PID_RESET_VALUE 0xFF /**< Invalid PID value which is guaranteed to not collide with any valid PID value. */
+#define NRF52_PID_MAX 3 /**< Maximum value for PID. */
+#define NRF52_CRC_RESET_VALUE 0xFFFF /**< CRC reset value*/
+
+#ifndef NRF52_RADIO_USE_TIMER0
+#define NRF52_RADIO_USE_TIMER0 FALSE
+#endif
+
+#ifndef NRF52_RADIO_USE_TIMER1
+#define NRF52_RADIO_USE_TIMER1 FALSE
+#endif
+
+#ifndef NRF52_RADIO_USE_TIMER2
+#define NRF52_RADIO_USE_TIMER2 FALSE
+#endif
+
+#ifndef NRF52_RADIO_USE_TIMER3
+#define NRF52_RADIO_USE_TIMER3 FALSE
+#endif
+
+#ifndef NRF52_RADIO_USE_TIMER4
+#define NRF52_RADIO_USE_TIMER4 FALSE
+#endif
+
+#ifndef NRF52_RADIO_IRQ_PRIORITY
+#define NRF52_RADIO_IRQ_PRIORITY 3 /**< RADIO interrupt priority. */
+#endif
+
+#ifndef NRF52_RADIO_PPI_TIMER_START
+#error "PPI channel NRF52_RADIO_PPI_TIMER_START need to be defined"
+#endif
+
+#ifndef NRF52_RADIO_PPI_TIMER_STOP
+#error "PPI channel NRF52_RADIO_PPI_TIMER_STOP need to be defined"
+#endif
+
+#ifndef NRF52_RADIO_PPI_RX_TIMEOUT
+#error "PPI channel NRF52_RADIO_PPI_RX_TIMEOUT need to be defined"
+#endif
+
+#ifndef NRF52_RADIO_PPI_TX_START
+#error "PPI channel NRF52_RADIO_PPI_TX_START need to be defined"
+#endif
+
+#if (NRF52_RADIO_USE_TIMER0 == FALSE) && (NRF52_RADIO_USE_TIMER1 == FALSE) && \
+ (NRF52_RADIO_USE_TIMER2 == FALSE) && (NRF52_RADIO_USE_TIMER3 == FALSE) && \
+ (NRF52_RADIO_USE_TIMER4 == FALSE)
+#error "At least one hardware TIMER must be defined"
+#endif
+
+#ifndef NRF52_RADIO_INTTHD_PRIORITY
+#error "Interrupt handle thread priority need to be defined"
+#endif
+
+#ifndef NRF52_RADIO_EVTTHD_PRIORITY
+#error "Event thread priority need to be defined"
+#endif
+
+#define VERIFY_PAYLOAD_LENGTH(p) \
+do \
+{ \
+ if(p->length == 0 || \
+ p->length > NRF52_MAX_PAYLOAD_LENGTH || \
+ (RFD1.config.protocol == NRF52_PROTOCOL_ESB && \
+ p->length > RFD1.config.payload_length)) \
+ { \
+ return NRF52_ERROR_INVALID_LENGTH; \
+ } \
+}while(0)
+
+//Structure holding pipe info PID and CRC and ack payload.
+typedef struct
+{
+ uint16_t m_crc;
+ uint8_t m_pid;
+ uint8_t m_ack_payload;
+} pipe_info_t;
+
+// First in first out queue of payloads to be transmitted.
+typedef struct
+{
+ nrf52_payload_t * p_payload[NRF52_TX_FIFO_SIZE]; /**< Pointer to the actual queue. */
+ uint32_t entry_point; /**< Current start of queue. */
+ uint32_t exit_point; /**< Current end of queue. */
+ uint32_t count; /**< Current number of elements in the queue. */
+} nrf52_payload_tx_fifo_t;
+
+// First in first out queue of received payloads.
+typedef struct
+{
+ nrf52_payload_t * p_payload[NRF52_RX_FIFO_SIZE]; /**< Pointer to the actual queue. */
+ uint32_t entry_point; /**< Current start of queue. */
+ uint32_t exit_point; /**< Current end of queue. */
+ uint32_t count; /**< Current number of elements in the queue. */
+} nrf52_payload_rx_fifo_t;
+
+// These function pointers are changed dynamically, depending on protocol configuration and state.
+//static void (*on_radio_end)(RFDriver *rfp) = NULL;
+static void (*set_rf_payload_format)(RFDriver *rfp, uint32_t payload_length) = NULL;
+
+// The following functions are assigned to the function pointers above.
+static void on_radio_disabled_tx_noack(RFDriver *rfp);
+static void on_radio_disabled_tx(RFDriver *rfp);
+static void on_radio_disabled_tx_wait_for_ack(RFDriver *rfp);
+static void on_radio_disabled_rx(RFDriver *rfp);
+static void on_radio_disabled_rx_ack(RFDriver *rfp);
+
+static volatile uint16_t wait_for_ack_timeout_us;
+static nrf52_payload_t * p_current_payload;
+
+// TX FIFO
+static nrf52_payload_t tx_fifo_payload[NRF52_TX_FIFO_SIZE];
+static nrf52_payload_tx_fifo_t tx_fifo;
+
+// RX FIFO
+static nrf52_payload_t rx_fifo_payload[NRF52_RX_FIFO_SIZE];
+static nrf52_payload_rx_fifo_t rx_fifo;
+
+// Payload buffers
+static uint8_t tx_payload_buffer[NRF52_MAX_PAYLOAD_LENGTH + 2];
+static uint8_t rx_payload_buffer[NRF52_MAX_PAYLOAD_LENGTH + 2];
+
+static uint8_t pids[NRF52_PIPE_COUNT];
+static pipe_info_t rx_pipe_info[NRF52_PIPE_COUNT];
+
+ // disable and events semaphores.
+static binary_semaphore_t disable_sem;
+static binary_semaphore_t events_sem;
+
+RFDriver RFD1;
+
+// Function to do bytewise bit-swap on a unsigned 32 bit value
+static uint32_t bytewise_bit_swap(uint8_t const * p_inp) {
+ uint32_t inp = (*(uint32_t*)p_inp);
+
+ return __REV((uint32_t)__RBIT(inp)); //lint -esym(628, __rev) -esym(526, __rev) -esym(628, __rbit) -esym(526, __rbit) */
+}
+
+// Internal function to convert base addresses from nRF24L type addressing to nRF52 type addressing
+static uint32_t addr_conv(uint8_t const* p_addr) {
+ return __REV(bytewise_bit_swap(p_addr)); //lint -esym(628, __rev) -esym(526, __rev) */
+}
+
+static thread_t *rfEvtThread_p;
+static THD_WORKING_AREA(waRFEvtThread, 64);
+static THD_FUNCTION(rfEvtThread, arg) {
+ (void)arg;
+
+ chRegSetThreadName("rfevent");
+
+ while (!chThdShouldTerminateX()) {
+ chBSemWait(&events_sem);
+
+ nrf52_int_flags_t interrupts = RFD1.flags;
+ RFD1.flags = 0;
+
+ if (interrupts & NRF52_INT_TX_SUCCESS_MSK) {
+ chEvtBroadcastFlags(&RFD1.eventsrc, (eventflags_t) NRF52_EVENT_TX_SUCCESS);
+ }
+ if (interrupts & NRF52_INT_TX_FAILED_MSK) {
+ chEvtBroadcastFlags(&RFD1.eventsrc, (eventflags_t) NRF52_EVENT_TX_FAILED);
+ }
+ if (interrupts & NRF52_INT_RX_DR_MSK) {
+ chEvtBroadcastFlags(&RFD1.eventsrc, (eventflags_t) NRF52_EVENT_RX_RECEIVED);
+ }
+ }
+ chThdExit((msg_t) 0);
+}
+
+static thread_t *rfIntThread_p;
+static THD_WORKING_AREA(waRFIntThread, 64);
+static THD_FUNCTION(rfIntThread, arg) {
+ (void)arg;
+
+ chRegSetThreadName("rfint");
+
+ while (!chThdShouldTerminateX()) {
+ chBSemWait(&disable_sem);
+ switch (RFD1.state) {
+ case NRF52_STATE_PTX_TX:
+ on_radio_disabled_tx_noack(&RFD1);
+ break;
+ case NRF52_STATE_PTX_TX_ACK:
+ on_radio_disabled_tx(&RFD1);
+ break;
+ case NRF52_STATE_PTX_RX_ACK:
+ on_radio_disabled_tx_wait_for_ack(&RFD1);
+ break;
+ case NRF52_STATE_PRX:
+ on_radio_disabled_rx(&RFD1);
+ break;
+ case NRF52_STATE_PRX_SEND_ACK:
+ on_radio_disabled_rx_ack(&RFD1);
+ break;
+ default:
+ break;
+ }
+ }
+ chThdExit((msg_t) 0);
+}
+
+static void serve_radio_interrupt(RFDriver *rfp) {
+ (void) rfp;
+ if ((NRF_RADIO->INTENSET & RADIO_INTENSET_READY_Msk) && NRF_RADIO->EVENTS_READY) {
+ NRF_RADIO->EVENTS_READY = 0;
+ (void) NRF_RADIO->EVENTS_READY;
+ }
+ if ((NRF_RADIO->INTENSET & RADIO_INTENSET_DISABLED_Msk) && NRF_RADIO->EVENTS_DISABLED) {
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void) NRF_RADIO->EVENTS_DISABLED;
+ chSysLockFromISR();
+ chBSemSignalI(&disable_sem);
+ chSysUnlockFromISR();
+ }
+}
+
+/**
+ * @brief RADIO events interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_radio_interrupt(&RFD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+static void set_rf_payload_format_esb_dpl(RFDriver *rfp, uint32_t payload_length) {
+ (void)payload_length;
+#if (NRF52_MAX_PAYLOAD_LENGTH <= 32)
+ // Using 6 bits for length
+ NRF_RADIO->PCNF0 = (0 << RADIO_PCNF0_S0LEN_Pos) |
+ (6 << RADIO_PCNF0_LFLEN_Pos) |
+ (3 << RADIO_PCNF0_S1LEN_Pos) ;
+#else
+ // Using 8 bits for length
+ NRF_RADIO->PCNF0 = (0 << RADIO_PCNF0_S0LEN_Pos) |
+ (8 << RADIO_PCNF0_LFLEN_Pos) |
+ (3 << RADIO_PCNF0_S1LEN_Pos) ;
+#endif
+ NRF_RADIO->PCNF1 = (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) |
+ (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) |
+ ((rfp->config.address.addr_length - 1) << RADIO_PCNF1_BALEN_Pos) |
+ (0 << RADIO_PCNF1_STATLEN_Pos) |
+ (NRF52_MAX_PAYLOAD_LENGTH << RADIO_PCNF1_MAXLEN_Pos);
+}
+
+static void set_rf_payload_format_esb(RFDriver *rfp, uint32_t payload_length) {
+ NRF_RADIO->PCNF0 = (1 << RADIO_PCNF0_S0LEN_Pos) |
+ (0 << RADIO_PCNF0_LFLEN_Pos) |
+ (1 << RADIO_PCNF0_S1LEN_Pos);
+
+ NRF_RADIO->PCNF1 = (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) |
+ (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) |
+ ((rfp->config.address.addr_length - 1) << RADIO_PCNF1_BALEN_Pos) |
+ (payload_length << RADIO_PCNF1_STATLEN_Pos) |
+ (payload_length << RADIO_PCNF1_MAXLEN_Pos);
+}
+
+/* Set BASE0 and BASE1 addresses & prefixes registers
+ * NRF52 { prefixes[0], base0_addr[0], base0_addr[1], base0_addr[2], base0_addr[3] } ==
+ * NRF24 { addr[0], addr[1], addr[2], addr[3], addr[4] }
+ */
+static void set_addresses(RFDriver *rfp, uint8_t update_mask) {
+ if (update_mask & NRF52_ADDR_UPDATE_MASK_BASE0) {
+ NRF_RADIO->BASE0 = addr_conv(rfp->config.address.base_addr_p0);
+ NRF_RADIO->DAB[0] = addr_conv(rfp->config.address.base_addr_p0);
+ }
+
+ if (update_mask & NRF52_ADDR_UPDATE_MASK_BASE1) {
+ NRF_RADIO->BASE1 = addr_conv(rfp->config.address.base_addr_p1);
+ NRF_RADIO->DAB[1] = addr_conv(rfp->config.address.base_addr_p1);
+ }
+
+ if (update_mask & NRF52_ADDR_UPDATE_MASK_PREFIX) {
+ NRF_RADIO->PREFIX0 = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[0]);
+ NRF_RADIO->DAP[0] = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[0]);
+ NRF_RADIO->PREFIX1 = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[4]);
+ NRF_RADIO->DAP[1] = bytewise_bit_swap(&rfp->config.address.pipe_prefixes[4]);
+ }
+}
+
+static void set_tx_power(RFDriver *rfp) {
+ NRF_RADIO->TXPOWER = rfp->config.tx_power << RADIO_TXPOWER_TXPOWER_Pos;
+}
+
+static void set_bitrate(RFDriver *rfp) {
+ NRF_RADIO->MODE = rfp->config.bitrate << RADIO_MODE_MODE_Pos;
+
+ switch (rfp->config.bitrate) {
+ case NRF52_BITRATE_2MBPS:
+ wait_for_ack_timeout_us = RX_WAIT_FOR_ACK_TIMEOUT_US_2MBPS;
+ break;
+ case NRF52_BITRATE_1MBPS:
+ wait_for_ack_timeout_us = RX_WAIT_FOR_ACK_TIMEOUT_US_1MBPS;
+ break;
+ }
+}
+
+static void set_protocol(RFDriver *rfp) {
+ switch (rfp->config.protocol) {
+ case NRF52_PROTOCOL_ESB_DPL:
+ set_rf_payload_format = set_rf_payload_format_esb_dpl;
+ break;
+ case NRF52_PROTOCOL_ESB:
+ set_rf_payload_format = set_rf_payload_format_esb;
+ break;
+ }
+}
+
+static void set_crc(RFDriver *rfp) {
+ NRF_RADIO->CRCCNF = rfp->config.crc << RADIO_CRCCNF_LEN_Pos;
+
+ if (rfp->config.crc == RADIO_CRCCNF_LEN_Two)
+ {
+ NRF_RADIO->CRCINIT = 0xFFFFUL; // Initial value
+ NRF_RADIO->CRCPOLY = 0x11021UL; // CRC poly: x^16+x^12^x^5+1
+ }
+ else if (rfp->config.crc == RADIO_CRCCNF_LEN_One)
+ {
+ NRF_RADIO->CRCINIT = 0xFFUL; // Initial value
+ NRF_RADIO->CRCPOLY = 0x107UL; // CRC poly: x^8+x^2^x^1+1
+ }
+}
+
+static void ppi_init(RFDriver *rfp) {
+ NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_START].EEP = (uint32_t)&NRF_RADIO->EVENTS_READY;
+ NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_START].TEP = (uint32_t)&rfp->timer->TASKS_START;
+
+ NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_STOP].EEP = (uint32_t)&NRF_RADIO->EVENTS_ADDRESS;
+ NRF_PPI->CH[NRF52_RADIO_PPI_TIMER_STOP].TEP = (uint32_t)&rfp->timer->TASKS_STOP;
+
+ NRF_PPI->CH[NRF52_RADIO_PPI_RX_TIMEOUT].EEP = (uint32_t)&rfp->timer->EVENTS_COMPARE[0];
+ NRF_PPI->CH[NRF52_RADIO_PPI_RX_TIMEOUT].TEP = (uint32_t)&NRF_RADIO->TASKS_DISABLE;
+
+ NRF_PPI->CH[NRF52_RADIO_PPI_TX_START].EEP = (uint32_t)&rfp->timer->EVENTS_COMPARE[1];
+ NRF_PPI->CH[NRF52_RADIO_PPI_TX_START].TEP = (uint32_t)&NRF_RADIO->TASKS_TXEN;
+}
+
+static void set_parameters(RFDriver *rfp) {
+ set_tx_power(rfp);
+ set_bitrate(rfp);
+ set_protocol(rfp);
+ set_crc(rfp);
+ set_rf_payload_format(rfp, rfp->config.payload_length);
+}
+
+static void reset_fifo(void) {
+ tx_fifo.entry_point = 0;
+ tx_fifo.exit_point = 0;
+ tx_fifo.count = 0;
+
+ rx_fifo.entry_point = 0;
+ rx_fifo.exit_point = 0;
+ rx_fifo.count = 0;
+}
+
+static void init_fifo(void) {
+ uint8_t i;
+ reset_fifo();
+
+ for (i = 0; i < NRF52_TX_FIFO_SIZE; i++) {
+ tx_fifo.p_payload[i] = &tx_fifo_payload[i];
+ }
+
+ for (i = 0; i < NRF52_RX_FIFO_SIZE; i++) {
+ rx_fifo.p_payload[i] = &rx_fifo_payload[i];
+ }
+}
+
+static void tx_fifo_remove_last(void) {
+ if (tx_fifo.count > 0) {
+ nvicDisableVector(RADIO_IRQn);
+
+ tx_fifo.count--;
+ if (++tx_fifo.exit_point >= NRF52_TX_FIFO_SIZE) {
+ tx_fifo.exit_point = 0;
+ }
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+ }
+}
+
+/** @brief Function to push the content of the rx_buffer to the RX FIFO.
+ *
+ * The module will point the register NRF_RADIO->PACKETPTR to a buffer for receiving packets.
+ * After receiving a packet the module will call this function to copy the received data to
+ * the RX FIFO.
+ *
+ * @param pipe Pipe number to set for the packet.
+ * @param pid Packet ID.
+ *
+ * @retval true Operation successful.
+ * @retval false Operation failed.
+ */
+static bool rx_fifo_push_rfbuf(RFDriver *rfp, uint8_t pipe, uint8_t pid) {
+ if (rx_fifo.count < NRF52_RX_FIFO_SIZE) {
+ if (rfp->config.protocol == NRF52_PROTOCOL_ESB_DPL) {
+ if (rx_payload_buffer[0] > NRF52_MAX_PAYLOAD_LENGTH) {
+ return false;
+ }
+
+ rx_fifo.p_payload[rx_fifo.entry_point]->length = rx_payload_buffer[0];
+ }
+ else if (rfp->state == NRF52_STATE_PTX_RX_ACK) {
+ // Received packet is an acknowledgment
+ rx_fifo.p_payload[rx_fifo.entry_point]->length = 0;
+ }
+ else {
+ rx_fifo.p_payload[rx_fifo.entry_point]->length = rfp->config.payload_length;
+ }
+
+ memcpy(rx_fifo.p_payload[rx_fifo.entry_point]->data, &rx_payload_buffer[2],
+ rx_fifo.p_payload[rx_fifo.entry_point]->length);
+
+ rx_fifo.p_payload[rx_fifo.entry_point]->pipe = pipe;
+ rx_fifo.p_payload[rx_fifo.entry_point]->rssi = NRF_RADIO->RSSISAMPLE;
+ rx_fifo.p_payload[rx_fifo.entry_point]->pid = pid;
+ if (++rx_fifo.entry_point >= NRF52_RX_FIFO_SIZE) {
+ rx_fifo.entry_point = 0;
+ }
+ rx_fifo.count++;
+
+ return true;
+ }
+
+ return false;
+}
+
+static void timer_init(RFDriver *rfp) {
+ // Configure the system timer with a 1 MHz base frequency
+ rfp->timer->PRESCALER = 4;
+ rfp->timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
+ rfp->timer->SHORTS = TIMER_SHORTS_COMPARE1_CLEAR_Msk | TIMER_SHORTS_COMPARE1_STOP_Msk;
+}
+
+static void start_tx_transaction(RFDriver *rfp) {
+ bool ack;
+
+ rfp->tx_attempt = 1;
+ rfp->tx_remaining = rfp->config.retransmit.count;
+
+ // Prepare the payload
+ p_current_payload = tx_fifo.p_payload[tx_fifo.exit_point];
+
+ // Handling ack if noack is set to false or if selctive auto ack is turned turned off
+ ack = !p_current_payload->noack || !rfp->config.selective_auto_ack;
+
+ switch (rfp->config.protocol) {
+ case NRF52_PROTOCOL_ESB:
+ set_rf_payload_format(rfp, p_current_payload->length);
+ tx_payload_buffer[0] = p_current_payload->pid;
+ tx_payload_buffer[1] = 0;
+ memcpy(&tx_payload_buffer[2], p_current_payload->data, p_current_payload->length);
+
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk;
+ NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk | RADIO_INTENSET_READY_Msk;
+
+ // Configure the retransmit counter
+ rfp->tx_remaining = rfp->config.retransmit.count;
+ rfp->state = NRF52_STATE_PTX_TX_ACK;
+ break;
+
+ case NRF52_PROTOCOL_ESB_DPL:
+ tx_payload_buffer[0] = p_current_payload->length;
+ tx_payload_buffer[1] = p_current_payload->pid << 1;
+ tx_payload_buffer[1] |= ack ? 0x00 : 0x01;
+ memcpy(&tx_payload_buffer[2], p_current_payload->data, p_current_payload->length);
+
+ if (ack) {
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk;
+ NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk | RADIO_INTENSET_READY_Msk;
+
+ // Configure the retransmit counter
+ rfp->tx_remaining = rfp->config.retransmit.count;
+ rfp->state = NRF52_STATE_PTX_TX_ACK;
+ }
+ else {
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON;
+ NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk;
+ rfp->state = NRF52_STATE_PTX_TX;
+ }
+ break;
+ }
+
+ NRF_RADIO->TXADDRESS = p_current_payload->pipe;
+ NRF_RADIO->RXADDRESSES = 1 << p_current_payload->pipe;
+
+ NRF_RADIO->FREQUENCY = rfp->config.address.rf_channel;
+ NRF_RADIO->PACKETPTR = (uint32_t)tx_payload_buffer;
+
+ NRF_RADIO->EVENTS_READY = 0;
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void)NRF_RADIO->EVENTS_READY;
+ (void)NRF_RADIO->EVENTS_DISABLED;
+
+ nvicClearPending(RADIO_IRQn);
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ NRF_RADIO->TASKS_TXEN = 1;
+}
+
+static void on_radio_disabled_tx_noack(RFDriver *rfp) {
+ rfp->flags |= NRF52_INT_TX_SUCCESS_MSK;
+ tx_fifo_remove_last();
+
+ chBSemSignal(&events_sem);
+
+ if (tx_fifo.count == 0) {
+ rfp->state = NRF52_STATE_IDLE;
+ }
+ else {
+ start_tx_transaction(rfp);
+ }
+}
+
+static void on_radio_disabled_tx(RFDriver *rfp) {
+ // Remove the DISABLED -> RXEN shortcut, to make sure the radio stays
+ // disabled after the RX window
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON;
+
+ // Make sure the timer is started the next time the radio is ready,
+ // and that it will disable the radio automatically if no packet is
+ // received by the time defined in m_wait_for_ack_timeout_us
+ rfp->timer->CC[0] = wait_for_ack_timeout_us + 130;
+ rfp->timer->CC[1] = rfp->config.retransmit.delay - 130;
+ rfp->timer->TASKS_CLEAR = 1;
+ rfp->timer->EVENTS_COMPARE[0] = 0;
+ rfp->timer->EVENTS_COMPARE[1] = 0;
+ (void)rfp->timer->EVENTS_COMPARE[0];
+ (void)rfp->timer->EVENTS_COMPARE[1];
+
+ NRF_PPI->CHENSET = (1 << NRF52_RADIO_PPI_TIMER_START) |
+ (1 << NRF52_RADIO_PPI_RX_TIMEOUT) |
+ (1 << NRF52_RADIO_PPI_TIMER_STOP);
+ NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TX_START);
+
+ NRF_RADIO->EVENTS_END = 0;
+ (void)NRF_RADIO->EVENTS_END;
+
+ if (rfp->config.protocol == NRF52_PROTOCOL_ESB) {
+ set_rf_payload_format(rfp, 0);
+ }
+
+ NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer;
+ rfp->state = NRF52_STATE_PTX_RX_ACK;
+}
+
+static void on_radio_disabled_tx_wait_for_ack(RFDriver *rfp) {
+ // This marks the completion of a TX_RX sequence (TX with ACK)
+
+ // Make sure the timer will not deactivate the radio if a packet is received
+ NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TIMER_START) |
+ (1 << NRF52_RADIO_PPI_RX_TIMEOUT) |
+ (1 << NRF52_RADIO_PPI_TIMER_STOP);
+
+ // If the radio has received a packet and the CRC status is OK
+ if (NRF_RADIO->EVENTS_END && NRF_RADIO->CRCSTATUS != 0) {
+ rfp->timer->TASKS_STOP = 1;
+ NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TX_START);
+ rfp->flags |= NRF52_INT_TX_SUCCESS_MSK;
+ rfp->tx_attempt++;// = rfp->config.retransmit.count - rfp->tx_remaining + 1;
+
+ tx_fifo_remove_last();
+
+ if (rfp->config.protocol != NRF52_PROTOCOL_ESB && rx_payload_buffer[0] > 0) {
+ if (rx_fifo_push_rfbuf(rfp, (uint8_t)NRF_RADIO->TXADDRESS, 0)) {
+ rfp->flags |= NRF52_INT_RX_DR_MSK;
+ }
+ }
+
+ chBSemSignal(&events_sem);
+
+ if ((tx_fifo.count == 0) || (rfp->config.tx_mode == NRF52_TXMODE_MANUAL)) {
+ rfp->state = NRF52_STATE_IDLE;
+ }
+ else {
+ start_tx_transaction(rfp);
+ }
+ }
+ else {
+ if (rfp->tx_remaining-- == 0) {
+ rfp->timer->TASKS_STOP = 1;
+ NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TX_START);
+ // All retransmits are expended, and the TX operation is suspended
+ rfp->tx_attempt = rfp->config.retransmit.count + 1;
+ rfp->flags |= NRF52_INT_TX_FAILED_MSK;
+
+ chBSemSignal(&events_sem);
+
+ rfp->state = NRF52_STATE_IDLE;
+ }
+ else {
+ // There are still have more retransmits left, TX mode should be
+ // entered again as soon as the system timer reaches CC[1].
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk;
+ set_rf_payload_format(rfp, p_current_payload->length);
+ NRF_RADIO->PACKETPTR = (uint32_t)tx_payload_buffer;
+ rfp->state = NRF52_STATE_PTX_TX_ACK;
+ rfp->timer->TASKS_START = 1;
+ NRF_PPI->CHENSET = (1 << NRF52_RADIO_PPI_TX_START);
+ if (rfp->timer->EVENTS_COMPARE[1])
+ NRF_RADIO->TASKS_TXEN = 1;
+ }
+ }
+}
+
+static void clear_events_restart_rx(RFDriver *rfp) {
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON;
+ set_rf_payload_format(rfp, rfp->config.payload_length);
+ NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer;
+
+ NRF_RADIO->INTENCLR = RADIO_INTENCLR_DISABLED_Msk;
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void) NRF_RADIO->EVENTS_DISABLED;
+
+ NRF_RADIO->TASKS_DISABLE = 1;
+ while (NRF_RADIO->EVENTS_DISABLED == 0);
+
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void) NRF_RADIO->EVENTS_DISABLED;
+ NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk;
+
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_TXEN_Msk;
+ NRF_RADIO->TASKS_RXEN = 1;
+}
+
+static void on_radio_disabled_rx(RFDriver *rfp) {
+ bool ack = false;
+ bool retransmit_payload = false;
+ bool send_rx_event = true;
+ pipe_info_t * p_pipe_info;
+
+ if (NRF_RADIO->CRCSTATUS == 0) {
+ clear_events_restart_rx(rfp);
+ return;
+ }
+
+ if(rx_fifo.count >= NRF52_RX_FIFO_SIZE) {
+ clear_events_restart_rx(rfp);
+ return;
+ }
+
+ p_pipe_info = &rx_pipe_info[NRF_RADIO->RXMATCH];
+ if (NRF_RADIO->RXCRC == p_pipe_info->m_crc &&
+ (rx_payload_buffer[1] >> 1) == p_pipe_info->m_pid ) {
+ retransmit_payload = true;
+ send_rx_event = false;
+ }
+
+ p_pipe_info->m_pid = rx_payload_buffer[1] >> 1;
+ p_pipe_info->m_crc = NRF_RADIO->RXCRC;
+
+ if(rfp->config.selective_auto_ack == false || ((rx_payload_buffer[1] & 0x01) == 0))
+ ack = true;
+
+ if(ack) {
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_RXEN_Msk;
+
+ switch(rfp->config.protocol) {
+ case NRF52_PROTOCOL_ESB_DPL:
+ {
+ if (tx_fifo.count > 0 &&
+ (tx_fifo.p_payload[tx_fifo.exit_point]->pipe == NRF_RADIO->RXMATCH))
+ {
+ // Pipe stays in ACK with payload until TX fifo is empty
+ // Do not report TX success on first ack payload or retransmit
+ if (p_pipe_info->m_ack_payload != 0 && !retransmit_payload) {
+ if(++tx_fifo.exit_point >= NRF52_TX_FIFO_SIZE) {
+ tx_fifo.exit_point = 0;
+ }
+
+ tx_fifo.count--;
+
+ // ACK payloads also require TX_DS
+ // (page 40 of the 'nRF24LE1_Product_Specification_rev1_6.pdf').
+ rfp->flags |= NRF52_INT_TX_SUCCESS_MSK;
+ }
+
+ p_pipe_info->m_ack_payload = 1;
+
+ p_current_payload = tx_fifo.p_payload[tx_fifo.exit_point];
+
+ set_rf_payload_format(rfp, p_current_payload->length);
+ tx_payload_buffer[0] = p_current_payload->length;
+ memcpy(&tx_payload_buffer[2],
+ p_current_payload->data,
+ p_current_payload->length);
+ }
+ else {
+ p_pipe_info->m_ack_payload = 0;
+ set_rf_payload_format(rfp, 0);
+ tx_payload_buffer[0] = 0;
+ }
+
+ tx_payload_buffer[1] = rx_payload_buffer[1];
+ }
+ break;
+
+ case NRF52_PROTOCOL_ESB:
+ {
+ set_rf_payload_format(rfp, 0);
+ tx_payload_buffer[0] = rx_payload_buffer[0];
+ tx_payload_buffer[1] = 0;
+ }
+ break;
+ }
+
+ rfp->state = NRF52_STATE_PRX_SEND_ACK;
+ NRF_RADIO->TXADDRESS = NRF_RADIO->RXMATCH;
+ NRF_RADIO->PACKETPTR = (uint32_t)tx_payload_buffer;
+ }
+ else {
+ clear_events_restart_rx(rfp);
+ }
+
+ if (send_rx_event) {
+ // Push the new packet to the RX buffer and trigger a received event if the operation was
+ // successful.
+ if (rx_fifo_push_rfbuf(rfp, NRF_RADIO->RXMATCH, p_pipe_info->m_pid)) {
+ rfp->flags |= NRF52_INT_RX_DR_MSK;
+ chBSemSignal(&events_sem);
+ }
+ }
+}
+
+static void on_radio_disabled_rx_ack(RFDriver *rfp) {
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_TXEN_Msk;
+ set_rf_payload_format(rfp, rfp->config.payload_length);
+
+ NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer;
+
+ rfp->state = NRF52_STATE_PRX;
+}
+
+nrf52_error_t radio_disable(void) {
+ RFD1.state = NRF52_STATE_IDLE;
+
+ // Clear PPI
+ NRF_PPI->CHENCLR = (1 << NRF52_RADIO_PPI_TIMER_START) |
+ (1 << NRF52_RADIO_PPI_TIMER_STOP) |
+ (1 << NRF52_RADIO_PPI_RX_TIMEOUT);
+
+ reset_fifo();
+
+ memset(rx_pipe_info, 0, sizeof(rx_pipe_info));
+ memset(pids, 0, sizeof(pids));
+
+ // Disable the radio
+ NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Enabled << RADIO_SHORTS_READY_START_Pos |
+ RADIO_SHORTS_END_DISABLE_Enabled << RADIO_SHORTS_END_DISABLE_Pos;
+
+ nvicDisableVector(RADIO_IRQn);
+
+ // Terminate interrupts handle thread
+ chThdTerminate(rfIntThread_p);
+ chBSemSignal(&disable_sem);
+ chThdWait(rfIntThread_p);
+
+ // Terminate events handle thread
+ chThdTerminate(rfEvtThread_p);
+ RFD1.flags = 0;
+ chBSemSignal(&events_sem);
+ chThdWait(rfEvtThread_p);
+
+ RFD1.state = NRF52_STATE_UNINIT;
+
+ return NRF52_SUCCESS;
+}
+
+//
+nrf52_error_t radio_init(nrf52_config_t const *config) {
+ osalDbgAssert(config != NULL,
+ "config must be defined");
+ osalDbgAssert(&config->address != NULL,
+ "address must be defined");
+ osalDbgAssert(NRF52_RADIO_IRQ_PRIORITY <= 7,
+ "wrong radio irq priority");
+
+ if (RFD1.state != NRF52_STATE_UNINIT) {
+ nrf52_error_t err = radio_disable();
+ if (err != NRF52_SUCCESS)
+ return err;
+ }
+
+ RFD1.radio = NRF_RADIO;
+ RFD1.config = *config;
+ RFD1.flags = 0;
+
+ init_fifo();
+
+#if NRF52_RADIO_USE_TIMER0
+ RFD1.timer = NRF_TIMER0;
+#endif
+#if NRF52_RADIO_USE_TIMER1
+ RFD1.timer = NRF_TIMER1;
+#endif
+#if NRF52_RADIO_USE_TIMER2
+ RFD1.timer = NRF_TIMER2;
+#endif
+#if NRF52_RADIO_USE_TIMER3
+ RFD1.timer = NRF_TIMER3;
+#endif
+#if NRF52_RADIO_USE_TIMER4
+ RFD1.timer = NRF_TIMER4;
+#endif
+
+ set_parameters(&RFD1);
+
+ set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE0);
+ set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE1);
+ set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_PREFIX);
+
+ ppi_init(&RFD1);
+ timer_init(&RFD1);
+
+ chBSemObjectInit(&disable_sem, TRUE);
+ chBSemObjectInit(&events_sem, TRUE);
+
+ chEvtObjectInit(&RFD1.eventsrc);
+
+ // interrupt handle thread
+ rfIntThread_p = chThdCreateStatic(waRFIntThread, sizeof(waRFIntThread),
+ NRF52_RADIO_INTTHD_PRIORITY, rfIntThread, NULL);
+
+ // events handle thread
+ rfEvtThread_p = chThdCreateStatic(waRFEvtThread, sizeof(waRFEvtThread),
+ NRF52_RADIO_EVTTHD_PRIORITY, rfEvtThread, NULL);
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ RFD1.state = NRF52_STATE_IDLE;
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_write_payload(nrf52_payload_t const * p_payload) {
+ if (RFD1.state == NRF52_STATE_UNINIT)
+ return NRF52_INVALID_STATE;
+ if(p_payload == NULL)
+ return NRF52_ERROR_NULL;
+ VERIFY_PAYLOAD_LENGTH(p_payload);
+ if (tx_fifo.count >= NRF52_TX_FIFO_SIZE)
+ return NRF52_ERROR_INVALID_LENGTH;
+
+ if (RFD1.config.mode == NRF52_MODE_PTX &&
+ p_payload->noack && !RFD1.config.selective_auto_ack )
+ {
+ return NRF52_ERROR_NOT_SUPPORTED;
+ }
+
+ nvicDisableVector(RADIO_IRQn);
+
+ memcpy(tx_fifo.p_payload[tx_fifo.entry_point], p_payload, sizeof(nrf52_payload_t));
+
+ pids[p_payload->pipe] = (pids[p_payload->pipe] + 1) % (NRF52_PID_MAX + 1);
+ tx_fifo.p_payload[tx_fifo.entry_point]->pid = pids[p_payload->pipe];
+
+ if (++tx_fifo.entry_point >= NRF52_TX_FIFO_SIZE) {
+ tx_fifo.entry_point = 0;
+ }
+
+ tx_fifo.count++;
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ if (RFD1.config.mode == NRF52_MODE_PTX &&
+ RFD1.config.tx_mode == NRF52_TXMODE_AUTO &&
+ RFD1.state == NRF52_STATE_IDLE)
+ {
+ start_tx_transaction(&RFD1);
+ }
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_read_rx_payload(nrf52_payload_t * p_payload) {
+ if (RFD1.state == NRF52_STATE_UNINIT)
+ return NRF52_INVALID_STATE;
+ if (p_payload == NULL)
+ return NRF52_ERROR_NULL;
+
+ if (rx_fifo.count == 0) {
+ return NRF52_ERROR_INVALID_LENGTH;
+ }
+
+ nvicDisableVector(RADIO_IRQn);
+
+ p_payload->length = rx_fifo.p_payload[rx_fifo.exit_point]->length;
+ p_payload->pipe = rx_fifo.p_payload[rx_fifo.exit_point]->pipe;
+ p_payload->rssi = rx_fifo.p_payload[rx_fifo.exit_point]->rssi;
+ p_payload->pid = rx_fifo.p_payload[rx_fifo.exit_point]->pid;
+ memcpy(p_payload->data, rx_fifo.p_payload[rx_fifo.exit_point]->data, p_payload->length);
+
+ if (++rx_fifo.exit_point >= NRF52_RX_FIFO_SIZE) {
+ rx_fifo.exit_point = 0;
+ }
+
+ rx_fifo.count--;
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_start_tx(void) {
+ if (RFD1.state != NRF52_STATE_IDLE)
+ return NRF52_ERROR_BUSY;
+
+ if (tx_fifo.count == 0) {
+ return NRF52_ERROR_INVALID_LENGTH;
+ }
+
+ start_tx_transaction(&RFD1);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_start_rx(void) {
+ if (RFD1.state != NRF52_STATE_IDLE)
+ return NRF52_ERROR_BUSY;
+
+ NRF_RADIO->INTENCLR = 0xFFFFFFFF;
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void) NRF_RADIO->EVENTS_DISABLED;
+
+ NRF_RADIO->SHORTS = RADIO_SHORTS_COMMON | RADIO_SHORTS_DISABLED_TXEN_Msk;
+ NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk;
+ RFD1.state = NRF52_STATE_PRX;
+
+ NRF_RADIO->RXADDRESSES = RFD1.config.address.rx_pipes;
+ NRF_RADIO->FREQUENCY = RFD1.config.address.rf_channel;
+ NRF_RADIO->PACKETPTR = (uint32_t)rx_payload_buffer;
+
+ nvicClearPending(RADIO_IRQn);
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ NRF_RADIO->EVENTS_ADDRESS = 0;
+ NRF_RADIO->EVENTS_PAYLOAD = 0;
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void) NRF_RADIO->EVENTS_ADDRESS;
+ (void) NRF_RADIO->EVENTS_PAYLOAD;
+ (void) NRF_RADIO->EVENTS_DISABLED;
+
+ NRF_RADIO->TASKS_RXEN = 1;
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_stop_rx(void) {
+ if (RFD1.state != NRF52_STATE_PRX) {
+ return NRF52_INVALID_STATE;
+ }
+
+ NRF_RADIO->SHORTS = 0;
+ NRF_RADIO->INTENCLR = 0xFFFFFFFF;
+ NRF_RADIO->EVENTS_DISABLED = 0;
+ (void) NRF_RADIO->EVENTS_DISABLED;
+ NRF_RADIO->TASKS_DISABLE = 1;
+ while (NRF_RADIO->EVENTS_DISABLED == 0);
+ RFD1.state = NRF52_STATE_IDLE;
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_flush_tx(void) {
+ if (RFD1.state == NRF52_STATE_UNINIT)
+ return NRF52_INVALID_STATE;
+
+ nvicDisableVector(RADIO_IRQn);
+
+ tx_fifo.count = 0;
+ tx_fifo.entry_point = 0;
+ tx_fifo.exit_point = 0;
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_pop_tx(void) {
+ if (RFD1.state == NRF52_STATE_UNINIT)
+ return NRF52_INVALID_STATE;
+ if (tx_fifo.count == 0)
+ return NRF52_ERROR_INVALID_LENGTH;
+
+ nvicDisableVector(RADIO_IRQn);
+
+ if (++tx_fifo.entry_point >= NRF52_TX_FIFO_SIZE) {
+ tx_fifo.entry_point = 0;
+ }
+ tx_fifo.count--;
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_flush_rx(void) {
+ if (RFD1.state == NRF52_STATE_UNINIT)
+ return NRF52_INVALID_STATE;
+
+ nvicDisableVector(RADIO_IRQn);
+
+ rx_fifo.count = 0;
+ rx_fifo.entry_point = 0;
+ rx_fifo.exit_point = 0;
+
+ memset(rx_pipe_info, 0, sizeof(rx_pipe_info));
+
+ nvicEnableVector(RADIO_IRQn, NRF52_RADIO_IRQ_PRIORITY);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_set_base_address_0(uint8_t const * p_addr) {
+ if (RFD1.state != NRF52_STATE_IDLE)
+ return NRF52_ERROR_BUSY;
+ if (p_addr == NULL)
+ return NRF52_ERROR_NULL;
+
+ memcpy(RFD1.config.address.base_addr_p0, p_addr, 4);
+ set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE0);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_set_base_address_1(uint8_t const * p_addr) {
+ if (RFD1.state != NRF52_STATE_IDLE)
+ return NRF52_ERROR_BUSY;
+ if (p_addr == NULL)
+ return NRF52_ERROR_NULL;
+
+ memcpy(RFD1.config.address.base_addr_p1, p_addr, 4);
+ set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_BASE1);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_set_prefixes(uint8_t const * p_prefixes, uint8_t num_pipes) {
+ if (RFD1.state != NRF52_STATE_IDLE)
+ return NRF52_ERROR_BUSY;
+ if (p_prefixes == NULL)
+ return NRF52_ERROR_NULL;
+ if (num_pipes > 8)
+ return NRF52_ERROR_INVALID_PARAM;
+
+ memcpy(RFD1.config.address.pipe_prefixes, p_prefixes, num_pipes);
+ RFD1.config.address.num_pipes = num_pipes;
+ RFD1.config.address.rx_pipes = BIT_MASK_UINT_8(num_pipes);
+
+ set_addresses(&RFD1, NRF52_ADDR_UPDATE_MASK_PREFIX);
+
+ return NRF52_SUCCESS;
+}
+
+nrf52_error_t radio_set_prefix(uint8_t pipe, uint8_t prefix) {
+ if (RFD1.state != NRF52_STATE_IDLE)
+ return NRF52_ERROR_BUSY;
+ if (pipe > 8)
+ return NRF52_ERROR_INVALID_PARAM;
+
+ RFD1.config.address.pipe_prefixes[pipe] = prefix;
+
+ NRF_RADIO->PREFIX0 = bytewise_bit_swap(&RFD1.config.address.pipe_prefixes[0]);
+ NRF_RADIO->PREFIX1 = bytewise_bit_swap(&RFD1.config.address.pipe_prefixes[4]);
+
+ return NRF52_SUCCESS;
+}
diff --git a/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h
new file mode 100644
index 0000000..2f94465
--- /dev/null
+++ b/testhal/NRF52/NRF52832/RADIO-ESB/nrf52_radio.h
@@ -0,0 +1,256 @@
+/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ * @brief Enhanced ShockBurst (ESB) is a basic protocol supporting two-way data
+ * packet communication including packet buffering, packet acknowledgment
+ * and automatic retransmission of lost packets.
+ *
+ * ported on: 25/10/2018, by andru
+ *
+ */
+
+#ifndef NRF52_RADIO_H_
+#define NRF52_RADIO_H_
+
+// Hard coded parameters - change if necessary
+#ifndef NRF52_MAX_PAYLOAD_LENGTH
+#define NRF52_MAX_PAYLOAD_LENGTH 32 /**< The max size of the payload. Valid values are 1 to 252 */
+#endif
+
+#define NRF52_CRC_RESET_VALUE 0xFFFF /**< CRC reset value*/
+
+#define NRF52_TX_FIFO_SIZE 8 /**< The size of the transmission first in first out buffer. */
+#define NRF52_RX_FIFO_SIZE 8 /**< The size of the reception first in first out buffer. */
+
+#define NRF52_RADIO_USE_TIMER0 FALSE /**< TIMER0 will be used by the module. */
+#define NRF52_RADIO_USE_TIMER1 TRUE /**< TIMER1 will be used by the module. */
+#define NRF52_RADIO_USE_TIMER2 FALSE /**< TIMER2 will be used by the module. */
+#define NRF52_RADIO_USE_TIMER3 FALSE /**< TIMER3 will be used by the module. */
+#define NRF52_RADIO_USE_TIMER4 FALSE /**< TIMER4 will be used by the module. */
+
+#define NRF52_RADIO_IRQ_PRIORITY 3 /**< RADIO interrupt priority. */
+#define NRF52_RADIO_INTTHD_PRIORITY (NORMALPRIO+2) /**< Interrupts handle thread priority. */
+#define NRF52_RADIO_EVTTHD_PRIORITY (NORMALPRIO+1) /**< Events handle thread priority */
+
+#define NRF52_RADIO_PPI_TIMER_START 10 /**< The PPI channel used for timer start. */
+#define NRF52_RADIO_PPI_TIMER_STOP 11 /**< The PPI channel used for timer stop. */
+#define NRF52_RADIO_PPI_RX_TIMEOUT 12 /**< The PPI channel used for RX timeout. */
+#define NRF52_RADIO_PPI_TX_START 13 /**< The PPI channel used for starting TX. */
+
+
+typedef enum {
+ NRF52_SUCCESS, /* Call was successful. */
+ NRF52_INVALID_STATE, /* Module is not initialized. */
+ NRF52_ERROR_BUSY, /* Module was not in idle state. */
+ NRF52_ERROR_NULL, /* Required parameter was NULL. */
+ NRF52_ERROR_INVALID_PARAM, /* Required parameter is invalid */
+ NRF52_ERROR_NOT_SUPPORTED, /* p_payload->noack was false while selective ack was not enabled. */
+ NRF52_ERROR_INVALID_LENGTH, /* Payload length was invalid (zero or larger than max allowed). */
+} nrf52_error_t;
+
+// Internal radio module state.
+typedef enum {
+ NRF52_STATE_UNINIT, /**< Module not initialized. */
+ NRF52_STATE_IDLE, /**< Module idle. */
+ NRF52_STATE_PTX_TX, /**< Module transmitting without ack. */
+ NRF52_STATE_PTX_TX_ACK, /**< Module transmitting with ack. */
+ NRF52_STATE_PTX_RX_ACK, /**< Module transmitting with ack and reception of payload with the ack response. */
+ NRF52_STATE_PRX, /**< Module receiving packets without ack. */
+ NRF52_STATE_PRX_SEND_ACK, /**< Module transmitting ack in RX mode. */
+} nrf52_state_t;
+
+/**@brief Events to indicate the last transmission/receiving status. */
+typedef enum {
+ NRF52_EVENT_TX_SUCCESS = 0x01, /**< Event triggered on TX success. */
+ NRF52_EVENT_TX_FAILED = 0x02, /**< Event triggered on TX failed. */
+ NRF52_EVENT_RX_RECEIVED = 0x04, /**< Event triggered on RX Received. */
+} nrf52_event_t;
+
+// Interrupt flags
+typedef enum {
+ NRF52_INT_TX_SUCCESS_MSK = 0x01, /**< The flag used to indicate a success since last event. */
+ NRF52_INT_TX_FAILED_MSK = 0x02, /**< The flag used to indicate a failiure since last event. */
+ NRF52_INT_RX_DR_MSK = 0x04, /**< The flag used to indicate a received packet since last event. */
+} nrf52_int_flags_t;
+
+/**Macro to create initializer for a TX data packet.
+ *
+ * @details This macro generates an initializer. It is more efficient
+ * than setting the individual parameters dynamically.
+ *
+ * @param[in] _pipe The pipe to use for the data packet.
+ * @param[in] ... Comma separated list of character data to put in the TX buffer.
+ * Supported values are from 1 to 63 characters.
+ *
+ * @return Initializer that sets up pipe, length and the byte array for content of the TX data.
+ */
+#define NRF52_CREATE_PAYLOAD(_pipe, ...) \
+ {.pipe = _pipe, .length = NUM_VA_ARGS(__VA_ARGS__), .data = {__VA_ARGS__}}; \
+ STATIC_ASSERT(NUM_VA_ARGS(__VA_ARGS__) > 0 && NUM_VA_ARGS(__VA_ARGS__) <= 63)
+
+/**@brief Enhanced ShockBurst protocol. */
+typedef enum {
+ NRF52_PROTOCOL_ESB, /*< Enhanced ShockBurst with fixed payload length. */
+ NRF52_PROTOCOL_ESB_DPL /*< Enhanced ShockBurst with dynamic payload length. */
+} nrf52_protocol_t;
+
+/**@brief Enhanced ShockBurst mode. */
+typedef enum {
+ NRF52_MODE_PTX, /*< Primary transmitter mode. */
+ NRF52_MODE_PRX /*< Primary receiver mode. */
+} nrf52_mode_t;
+
+/**@brief Enhanced ShockBurst bitrate mode. */
+typedef enum {
+ NRF52_BITRATE_2MBPS = RADIO_MODE_MODE_Nrf_2Mbit, /**< 2Mbit radio mode. */
+ NRF52_BITRATE_1MBPS = RADIO_MODE_MODE_Nrf_1Mbit, /**< 1Mbit radio mode. */
+} nrf52_bitrate_t;
+
+/**@brief Enhanced ShockBurst CRC modes. */
+typedef enum {
+ NRF52_CRC_16BIT = RADIO_CRCCNF_LEN_Two, /**< Use two byte CRC. */
+ NRF52_CRC_8BIT = RADIO_CRCCNF_LEN_One, /**< Use one byte CRC. */
+ NRF52_CRC_OFF = RADIO_CRCCNF_LEN_Disabled /**< Disable CRC. */
+} nrf52_crc_t;
+
+/**@brief Enhanced ShockBurst radio transmission power modes. */
+typedef enum {
+ NRF52_TX_POWER_4DBM = RADIO_TXPOWER_TXPOWER_Pos4dBm, /**< 4 dBm radio transmit power. */
+ NRF52_TX_POWER_0DBM = RADIO_TXPOWER_TXPOWER_0dBm, /**< 0 dBm radio transmit power. */
+ NRF52_TX_POWER_NEG4DBM = RADIO_TXPOWER_TXPOWER_Neg4dBm, /**< -4 dBm radio transmit power. */
+ NRF52_TX_POWER_NEG8DBM = RADIO_TXPOWER_TXPOWER_Neg8dBm, /**< -8 dBm radio transmit power. */
+ NRF52_TX_POWER_NEG12DBM = RADIO_TXPOWER_TXPOWER_Neg12dBm, /**< -12 dBm radio transmit power. */
+ NRF52_TX_POWER_NEG16DBM = RADIO_TXPOWER_TXPOWER_Neg16dBm, /**< -16 dBm radio transmit power. */
+ NRF52_TX_POWER_NEG20DBM = RADIO_TXPOWER_TXPOWER_Neg20dBm, /**< -20 dBm radio transmit power. */
+ NRF52_TX_POWER_NEG30DBM = RADIO_TXPOWER_TXPOWER_Neg30dBm /**< -30 dBm radio transmit power. */
+} nrf52_tx_power_t;
+
+/**@brief Enhanced ShockBurst transmission modes. */
+typedef enum {
+ NRF52_TXMODE_AUTO, /*< Automatic TX mode - When the TX fifo is non-empty and the radio is idle packets will be sent automatically. */
+ NRF52_TXMODE_MANUAL, /*< Manual TX mode - Packets will not be sent until radio_start_tx() is called. Can be used to ensure consistent packet timing. */
+ NRF52_TXMODE_MANUAL_START /*< Manual start TX mode - Packets will not be sent until radio_start_tx() is called, but transmission will continue automatically until the TX fifo is empty. */
+} nrf52_tx_mode_t;
+
+/**@brief Enhanced ShockBurst addresses.
+ *
+ * @details The module is able to transmit packets with the TX address stored in tx_address.
+ The module can also receive packets from peers with up to eight different tx_addresses
+ stored in esb_addr_p0 - esb_addr_p7. esb_addr_p0 can have 5 arbitrary bytes
+ independent of the other addresses. esb_addr_p1 - esb_addr_p7 will share the
+ same four byte base address found in the last four bytes of esb_addr_p1.
+ They have an independent prefix byte found in esb_addr_p1[0] and esb_addr_p2 -
+ esb_addr_p7.
+*/
+typedef struct {
+ uint8_t base_addr_p0[4]; /**< Base address for pipe 0 encoded in big endian. */
+ uint8_t base_addr_p1[4]; /**< Base address for pipe 1-7 encoded in big endian. */
+ uint8_t pipe_prefixes[8]; /**< Address prefix for pipe P0 to P7. */
+ uint8_t num_pipes; /**< Number of pipes available. */
+ uint8_t addr_length; /**< Length of address including prefix */
+ uint8_t rx_pipes; /**< Bitfield for enabled RX pipes. */
+ uint8_t rf_channel; /**< Which channel is to be used. Must be in range 0 and 125 to be valid. */
+} nrf52_address_t;
+
+/**@brief Enhanced ShockBurst payload.
+ *
+ * @note The payload is used both for transmission and receive with ack and payload.
+*/
+typedef struct
+{
+ uint8_t length; /**< Length of the packet. Should be equal or less than NRF_ESB_MAX_PAYLOAD_LENGTH. */
+ uint8_t pipe; /**< Pipe used for this payload. */
+ int8_t rssi; /**< RSSI for received packet. */
+ uint8_t noack; /**< Flag indicating that this packet will not be acknowledged. */
+ uint8_t pid; /**< PID assigned during communication. */
+ uint8_t data[NRF52_MAX_PAYLOAD_LENGTH]; /**< The payload data. */
+} nrf52_payload_t;
+
+/**@brief Retransmit attempts delay and counter. */
+typedef struct {
+ uint16_t delay; /**< The delay between each retransmission of unacked packets. */
+ uint16_t count; /**< The number of retransmissions attempts before transmission fail. */
+} nrf52_retransmit_t;
+
+/**@brief Main nrf_esb configuration struct. */
+typedef struct {
+ nrf52_protocol_t protocol; /**< Enhanced ShockBurst protocol. */
+ nrf52_mode_t mode; /**< Enhanced ShockBurst default RX or TX mode. */
+
+ // General RF parameters
+ nrf52_bitrate_t bitrate; /**< Enhanced ShockBurst bitrate mode. */
+ nrf52_crc_t crc; /**< Enhanced ShockBurst CRC mode. */
+ nrf52_tx_power_t tx_power; /**< Enhanced ShockBurst radio transmission power mode.*/
+
+ // Control settings
+ nrf52_tx_mode_t tx_mode; /**< Enhanced ShockBurst transmit mode. */
+
+ bool selective_auto_ack; /**< Enable or disable selective auto acknowledgement. */
+
+ nrf52_retransmit_t retransmit; /**< Packet retransmit parameters */
+
+ uint8_t payload_length; /**< Enhanced ShockBurst static payload length */
+
+ nrf52_address_t address; /**< Address parameters structure */
+} nrf52_config_t;
+
+typedef struct {
+ /**
+ * @brief NRF52 radio peripheral.
+ */
+ NRF_RADIO_Type *radio;
+ /**
+ * @brief NRF52 timer peripheral.
+ */
+ NRF_TIMER_Type *timer;
+ /**
+ * @brief Driver state.
+ */
+ nrf52_state_t state;
+ /**
+ * @brief RF parameters.
+ */
+ nrf52_config_t config;
+ /**
+ * @brief Interrupts flag.
+ */
+ nrf52_int_flags_t flags;
+ /**
+ * @brief TX attempt number.
+ */
+ uint16_t tx_attempt;
+ /**
+ * @brief TX retransmits remaining.
+ */
+ uint16_t tx_remaining;
+ /**
+ * @brief Radio events source.
+ */
+ event_source_t eventsrc;
+} RFDriver;
+
+extern RFDriver RFD1;
+
+nrf52_error_t radio_init(nrf52_config_t const *config);
+nrf52_error_t radio_disable(void);
+nrf52_error_t radio_write_payload(nrf52_payload_t const * p_payload);
+nrf52_error_t radio_read_rx_payload(nrf52_payload_t * p_payload);
+nrf52_error_t radio_start_tx(void);
+nrf52_error_t radio_start_rx(void);
+nrf52_error_t radio_stop_rx(void);
+nrf52_error_t radio_flush_tx(void);
+nrf52_error_t radio_flush_rx(void);
+nrf52_error_t radio_pop_tx(void);
+nrf52_error_t radio_set_base_address_0(uint8_t const * p_addr);
+nrf52_error_t radio_set_base_address_1(uint8_t const * p_addr);
+nrf52_error_t radio_set_prefixes(uint8_t const * p_prefixes, uint8_t num_pipes);
+nrf52_error_t radio_set_prefix(uint8_t pipe, uint8_t prefix);
+
+#endif /* NRF52_RADIO_H_ */