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| author | barthess <barthess@yandex.ru> | 2014-10-24 21:46:17 +0300 |
|---|---|---|
| committer | barthess <barthess@yandex.ru> | 2014-10-24 21:46:17 +0300 |
| commit | e9f9ddaa12464a5706617814d2244b0937cdf9fc (patch) | |
| tree | f5333b295a7e0501d3631246b6983a443c1664ae /testhal/STM32/STM32F4xx | |
| parent | 5f231b6aaf4f3506b462faed77db0b3a5595d918 (diff) | |
| download | ChibiOS-Contrib-e9f9ddaa12464a5706617814d2244b0937cdf9fc.tar.gz ChibiOS-Contrib-e9f9ddaa12464a5706617814d2244b0937cdf9fc.tar.bz2 ChibiOS-Contrib-e9f9ddaa12464a5706617814d2244b0937cdf9fc.zip | |
FSMC. SDRAM architecture reworked. Needs review.
Diffstat (limited to 'testhal/STM32/STM32F4xx')
| -rw-r--r-- | testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 4a3497d..ba2b2b4 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -62,7 +62,7 @@ static const size_t extram_size = 1024*1024; * SDRAM driver configuration structure. */ static const SDRAMConfig sdram_cfg = { - .sdcr = (uint32_t) FMC_ColumnBits_Number_9b | + .sdcr1 = (uint32_t) FMC_ColumnBits_Number_9b | FMC_RowBits_Number_13b | FMC_SDMemory_Width_16b | FMC_InternalBank_Number_4 | @@ -71,7 +71,7 @@ static const SDRAMConfig sdram_cfg = { FMC_SDClock_Period_3 | FMC_Read_Burst_Enable | FMC_ReadPipe_Delay_1, - .sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + .sdtr1 = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) @@ -168,7 +168,7 @@ int main(void) { chSysInit(); fsmcSdramInit(); - fsmcSdramStart(&SDRAMD1, &sdram_cfg); + fsmcSdramStart(&SDRAMD, &sdram_cfg); extram_benchmark(); #if USE_INFINITE_MEMTEST |