diff options
| -rw-r--r-- | os/hal/ports/TIVA/LLD/UART/driver.mk | 4 | ||||
| -rw-r--r-- | os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c | 826 | ||||
| -rw-r--r-- | os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h | 471 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/.cproject | 68 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/.project | 101 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/Makefile | 218 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/chconf.h | 510 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch | 10 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/debug/TM4C123x-UART (OpenOCD, Flash and Run).launch | 52 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/halconf.h | 296 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/main.c | 146 | ||||
| -rw-r--r-- | testhal/TIVA/TM4C123x/UART/mcuconf.h | 196 |
12 files changed, 2898 insertions, 0 deletions
diff --git a/os/hal/ports/TIVA/LLD/UART/driver.mk b/os/hal/ports/TIVA/LLD/UART/driver.mk index e23dc82..e42f34a 100644 --- a/os/hal/ports/TIVA/LLD/UART/driver.mk +++ b/os/hal/ports/TIVA/LLD/UART/driver.mk @@ -2,8 +2,12 @@ ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c endif +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c +endif else PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c endif PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c new file mode 100644 index 0000000..374ea6d --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c @@ -0,0 +1,826 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.c + * @brief Tiva low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief UART0 UART driver identifier.*/ +#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief UART1 UART driver identifier.*/ +#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief UART2 UART driver identifier.*/ +#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/** @brief UART3 UART driver identifier.*/ +#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__) +UARTDriver UARTD4; +#endif + +/** @brief UART4 UART driver identifier.*/ +#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__) +UARTDriver UARTD5; +#endif + +/** @brief UART5 UART driver identifier.*/ +#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__) +UARTDriver UARTD6; +#endif + +/** @brief UART6 UART driver identifier.*/ +#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__) +UARTDriver UARTD7; +#endif + +/** @brief UART7 UART driver identifier.*/ +#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__) +UARTDriver UARTD8; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] err UART LSR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint32_t err) +{ + uartflags_t sts = 0; + + if (err & UART_MIS_FEMIS) + sts |= UART_FRAMING_ERROR; + if (err & UART_MIS_PEMIS) + sts |= UART_PARITY_ERROR; + if (err & UART_MIS_BEMIS) + sts |= UART_BREAK_DETECTED; + if (err & UART_MIS_OEMIS) + sts |= UART_OVERRUN_ERROR; + + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_enter_rx_idle_loop(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + dmaChannelDisable(uartp->dmarxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmarxnr].dstendp = (volatile void *)&uartp->rxbuf; + primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(1) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmarxnr); + dmaChannelPrimary(uartp->dmarxnr); + dmaChannelPriorityDefault(uartp->dmarxnr); + dmaChannelEnableRequest(uartp->dmarxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmarxnr); +} + +/** + * @brief UART de-initialization. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_stop(UARTDriver *uartp) +{ + /* Stops RX and TX DMA channels.*/ + dmaChannelDisable(uartp->dmarxnr); + dmaChannelDisable(uartp->dmatxnr); + + /* Stops USART operations.*/ + HWREG(uartp->uart + UART_O_CTL) &= ~UART_CTL_UARTEN; +} + +/** + * @brief UART initialization. + * + * @param[in] uartp pointer to a @p UARTDriver object + */ +static void uart_init(UARTDriver *uartp) +{ + uint32_t u = uartp->uart; + const UARTConfig *config = uartp->config; + uint32_t brd; + uint32_t speed = config->speed; + uint32_t clock_source; + + if (uartp->config->ctl & UART_CTL_HSE) { + /* High speed mode is enabled, half the baud rate to compensate + * for high speed mode.*/ + speed = (speed + 1) / 2; + } + + if ((config->cc & UART_CC_CS_M) == UART_CC_CS_SYSCLK) { + /* UART is clocked using the SYSCLK.*/ + clock_source = TIVA_SYSCLK * 8; + } + else { + /* UART is clocked using the PIOSC.*/ + clock_source = 16000000 * 8; + } + + /* Calculate the baud rate divisor */ + brd = ((clock_source / speed) + 1) / 2; + + /* Disable UART.*/ + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; + + /* Set baud rate.*/ + HWREG(u + UART_O_IBRD) = brd / 64; + HWREG(u + UART_O_FBRD) = brd % 64; + + /* Line control/*/ + HWREG(u + UART_O_LCRH) = config->lcrh; + + /* Select clock source.*/ + HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M; + + /* FIFO configuration.*/ + HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M); + + /* Enable interrupts.*/ + HWREG(u + UART_O_IM) = UART_IM_TXIM | UART_IM_OEIM | UART_IM_BEIM | UART_IM_PEIM | UART_IM_FEIM; + + /* Enable DMA for the UART */ + HWREG(u + UART_O_DMACTL) = UART_DMACTL_TXDMAE | UART_DMACTL_RXDMAE | UART_DMACTL_DMAERR; + + /* Note that some bits are enforced.*/ + HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN | UART_CTL_EOT; + + /* Starting the receiver idle loop.*/ + uart_enter_rx_idle_loop(uartp); +} + +/** + * @brief UART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_serve_interrupt(UARTDriver *uartp) +{ + uint32_t dmachis = HWREG(UDMA_CHIS); + uint32_t mis = HWREG(uartp->uart + UART_O_MIS); + + if (mis & UART_MIS_TXMIS) { + /* End of transfer */ + _uart_tx2_isr_code(uartp); + } + + if (mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_PEMIS | UART_MIS_FEMIS)) { + /* Error occurred */ + _uart_rx_error_isr_code(uartp, translate_errors(mis)); + } + + if (dmachis & (1 << uartp->dmarxnr)) { + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + _uart_rx_idle_code(uartp); + uart_enter_rx_idle_loop(uartp); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + _uart_rx_complete_isr_code(uartp); + } + } + + if (dmachis & (1 << uartp->dmatxnr)) { + /* A callback is generated, if enabled, after a completed transfer.*/ + _uart_tx1_isr_code(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__) +#if !defined(TIVA_UART0_HANDLER) +#error "TIVA_UART0_HANDLER not defined" +#endif +/** + * @brief UART0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__) +#if !defined(TIVA_UART1_HANDLER) +#error "TIVA_UART1_HANDLER not defined" +#endif +/** + * @brief UART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__) +#if !defined(TIVA_UART2_HANDLER) +#error "TIVA_UART2_HANDLER not defined" +#endif +/** + * @brief UART2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__) +#if !defined(TIVA_UART3_HANDLER) +#error "TIVA_UART3_HANDLER not defined" +#endif +/** + * @brief UART3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__) +#if !defined(TIVA_UART4_HANDLER) +#error "TIVA_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__) +#if !defined(TIVA_UART5_HANDLER) +#error "TIVA_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__) +#if !defined(TIVA_UART6_HANDLER) +#error "TIVA_UART6_HANDLER not defined" +#endif +/** + * @brief UART6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__) +#if !defined(TIVA_UART7_HANDLER) +#error "TIVA_UART7_HANDLER not defined" +#endif +/** + * @brief UART7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) +{ +#if TIVA_UART_USE_UART0 + uartObjectInit(&UARTD1); + UARTD1.uart = UART0_BASE; + UARTD1.dmarxnr = TIVA_UART_UART0_RX_UDMA_CHANNEL; + UARTD1.dmatxnr = TIVA_UART_UART0_TX_UDMA_CHANNEL; + UARTD1.rxchnmap = TIVA_UART_UART0_RX_UDMA_MAPPING; + UARTD1.txchnmap = TIVA_UART_UART0_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART1 + uartObjectInit(&UARTD2); + UARTD2.uart = UART1_BASE; + UARTD2.dmarxnr = TIVA_UART_UART1_RX_UDMA_CHANNEL; + UARTD2.dmatxnr = TIVA_UART_UART1_TX_UDMA_CHANNEL; + UARTD2.rxchnmap = TIVA_UART_UART1_RX_UDMA_MAPPING; + UARTD2.txchnmap = TIVA_UART_UART1_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART2 + uartObjectInit(&UARTD3); + UARTD2.uart = UART2_BASE; + UARTD2.dmarxnr = TIVA_UART_UART2_RX_UDMA_CHANNEL; + UARTD2.dmatxnr = TIVA_UART_UART2_TX_UDMA_CHANNEL; + UARTD2.rxchnmap = TIVA_UART_UART2_RX_UDMA_MAPPING; + UARTD2.txchnmap = TIVA_UART_UART2_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART3 + uartObjectInit(&UARTD4); + UARTD4.uart = UART3_BASE; + UARTD4.dmarxnr = TIVA_UART_UART3_RX_UDMA_CHANNEL; + UARTD4.dmatxnr = TIVA_UART_UART3_TX_UDMA_CHANNEL; + UARTD4.rxchnmap = TIVA_UART_UART3_RX_UDMA_MAPPING; + UARTD4.txchnmap = TIVA_UART_UART3_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART4 + uartObjectInit(&UARTD5); + UARTD5.uart = UART4_BASE; + UARTD5.dmarxnr = TIVA_UART_UART4_RX_UDMA_CHANNEL; + UARTD5.dmatxnr = TIVA_UART_UART4_TX_UDMA_CHANNEL; + UARTD5.rxchnmap = TIVA_UART_UART4_RX_UDMA_MAPPING; + UARTD5.txchnmap = TIVA_UART_UART4_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART5 + uartObjectInit(&UARTD6); + UARTD6.uart = UART5_BASE; + UARTD6.dmarxnr = TIVA_UART_UART5_RX_UDMA_CHANNEL; + UARTD6.dmatxnr = TIVA_UART_UART5_TX_UDMA_CHANNEL; + UARTD6.rxchnmap = TIVA_UART_UART5_RX_UDMA_MAPPING; + UARTD6.txchnmap = TIVA_UART_UART5_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART6 + uartObjectInit(&UARTD7); + UARTD7.uart = UART6_BASE; + UARTD7.dmarxnr = TIVA_UART_UART6_RX_UDMA_CHANNEL; + UARTD7.dmatxnr = TIVA_UART_UART6_TX_UDMA_CHANNEL; + UARTD7.rxchnmap = TIVA_UART_UART6_RX_UDMA_MAPPING; + UARTD7.txchnmap = TIVA_UART_UART6_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART7 + uartObjectInit(&UARTD8); + UARTD8.uart = UART7_BASE; + UARTD8.dmarxnr = TIVA_UART_UART7_RX_UDMA_CHANNEL; + UARTD8.dmatxnr = TIVA_UART_UART7_TX_UDMA_CHANNEL; + UARTD8.rxchnmap = TIVA_UART_UART7_RX_UDMA_MAPPING; + UARTD8.txchnmap = TIVA_UART_UART7_TX_UDMA_MAPPING; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if TIVA_UART_USE_UART0 + if (&UARTD1 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 0))) + ; + + nvicEnableVector(TIVA_UART0_NUMBER, TIVA_UART_UART0_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART1 + if (&UARTD2 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 1))) + ; + + nvicEnableVector(TIVA_UART1_NUMBER, TIVA_UART_UART1_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART2 + if (&UARTD3 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 2))) + ; + + nvicEnableVector(TIVA_UART2_NUMBER, TIVA_UART_UART2_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART3 + if (&UARTD4 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 3))) + ; + + nvicEnableVector(TIVA_UART3_NUMBER, TIVA_UART_UART3_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART4 + if (&UARTD5 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 4))) + ; + + nvicEnableVector(TIVA_UART4_NUMBER, TIVA_UART_UART4_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART5 + if (&UARTD6 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 5))) + ; + + nvicEnableVector(TIVA_UART5_NUMBER, TIVA_UART_UART5_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART6 + if (&UARTD7 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 6); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 6))) + ; + + nvicEnableVector(TIVA_UART6_NUMBER, TIVA_UART_UART6_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART7 + if (&UARTD8 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 7); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 7))) + ; + + nvicEnableVector(TIVA_UART7_NUMBER, TIVA_UART_UART7_PRIORITY); + } +#endif + + uartp->rxbuf = 0; + + HWREG(UDMA_CHMAP0 + (uartp->dmarxnr / 8) * 4) |= (uartp->rxchnmap << (uartp->dmarxnr % 8)); + HWREG(UDMA_CHMAP0 + (uartp->dmatxnr / 8) * 4) |= (uartp->txchnmap << (uartp->dmatxnr % 8)); + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + uart_init(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + uart_stop(uartp); + udmaChannelRelease(uartp->dmarxnr); + udmaChannelRelease(uartp->dmatxnr); + +#if TIVA_UART_USE_UART0 + if (&UARTD1 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); + return; + } +#endif +#if TIVA_UART_USE_UART1 + if (&UARTD2 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); + return; + } +#endif +#if TIVA_UART_USE_UART2 + if (&UARTD3 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); + return; + } +#endif +#if TIVA_UART_USE_UART3 + if (&UARTD4 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); + return; + } +#endif +#if TIVA_UART_USE_UART4 + if (&UARTD5 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); + return; + } +#endif +#if TIVA_UART_USE_UART5 + if (&UARTD6 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); + return; + } +#endif +#if TIVA_UART_USE_UART6 + if (&UARTD7 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); + return; + } +#endif +#if TIVA_UART_USE_UART7 + if (&UARTD8 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + /* TODO: This assert should be moved to the dma helper driver */ + osalDbgAssert((uint32_t)txbuf >= SRAM_BASE, "txbuf should be in SRAM region."); + + dmaChannelDisable(uartp->dmatxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmatxnr].srcendp = (volatile void *)txbuf+n-1; + primary[uartp->dmatxnr].dstendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmatxnr); + dmaChannelPrimary(uartp->dmatxnr); + dmaChannelPriorityDefault(uartp->dmatxnr); + dmaChannelEnableRequest(uartp->dmatxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmatxnr); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + uint16_t left; + + dmaChannelDisable(uartp->dmatxnr); + + left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4; + + return left; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + /* TODO: This assert should be moved to the dma helper driver */ + osalDbgAssert((uint32_t)rxbuf >= SRAM_BASE, "rxbuf should be in SRAM region."); + + dmaChannelDisable(uartp->dmarxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmarxnr].dstendp = (volatile void *)rxbuf+n-1; + primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmarxnr); + dmaChannelPrimary(uartp->dmarxnr); + dmaChannelPriorityDefault(uartp->dmarxnr); + dmaChannelEnableRequest(uartp->dmarxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmarxnr); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + uint16_t left; + + dmaChannelDisable(uartp->dmatxnr); + + left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4; + + uart_enter_rx_idle_loop(uartp); + + return left; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h new file mode 100644 index 0000000..1dc743b --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h @@ -0,0 +1,471 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.h + * @brief Tiva low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on UART0 enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART0) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART0 FALSE +#endif + +/** + * @brief UART driver on UART1 enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART1) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART1 FALSE +#endif + +/** + * @brief UART driver on UART2 enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART2) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART2 FALSE +#endif + +/** + * @brief UART driver on UART3 enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART3) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART3 FALSE +#endif + +/** + * @brief UART driver on UART4 enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART4) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART4 FALSE +#endif + +/** + * @brief UART driver on UART5 enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART5) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART5 FALSE +#endif + +/** + * @brief UART driver on UART6 enable switch. + * @details If set to @p TRUE the support for UART6 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART6) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART6 FALSE +#endif + +/** + * @brief UART driver on UART7 enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART7) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART7 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART0_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART1_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART2_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART3_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART4_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART5_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART6 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART6_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART7 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART7_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 && !TIVA_HAS_UART0 +#error "UART0 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART1 && !TIVA_HAS_UART1 +#error "UART1 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART2 && !TIVA_HAS_UART2 +#error "UART2 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART3 && !TIVA_HAS_UART3 +#error "UART3 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART4 && !TIVA_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART5 && !TIVA_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART6 && !TIVA_HAS_UART6 +#error "UART6 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART7 && !TIVA_HAS_UART7 +#error "UART7 not present in the selected device" +#endif + +#if !TIVA_UART_USE_UART0 && !TIVA_UART_USE_UART1 && !TIVA_UART_USE_UART2 && \ + !TIVA_UART_USE_UART3 && !TIVA_UART_USE_UART4 && !TIVA_UART_USE_UART5 && \ + !TIVA_UART_USE_UART6 && !TIVA_UART_USE_UART7 +#error "UART driver activated but no UART peripheral assigned" +#endif + +#if TIVA_UART_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if TIVA_UART_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if TIVA_UART_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +#if TIVA_UART_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + +#if TIVA_UART_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if TIVA_UART_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if TIVA_UART_USE_UART6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART6" +#endif + +#if TIVA_UART_USE_UART7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART7" +#endif + +#if !defined(TIVA_UDMA_REQUIRED) +#define TIVA_UDMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields. */ + /** + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. + */ + uint8_t ifls; + /** + * @brief Initialization value for the CC register. + */ + uint8_t cc; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the UART registers block. + */ + uint32_t uart; + /** + * @brief Receive DMA channel number. + */ + uint8_t dmarxnr; + /** + * @brief Transmit DMA channel number. + */ + uint8_t dmatxnr; + /** + * @brief Receive DMA channel map. + */ + uint8_t rxchnmap; + /** + * @brief Transmit DMA channel map. + */ + uint8_t txchnmap; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if TIVA_UART_USE_UART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if TIVA_UART_USE_UART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#if TIVA_UART_USE_UART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD4; +#endif + +#if TIVA_UART_USE_UART4 && !defined(__DOXYGEN__) +extern UARTDriver UARTD5; +#endif + +#if TIVA_UART_USE_UART5 && !defined(__DOXYGEN__) +extern UARTDriver UARTD6; +#endif + +#if TIVA_UART_USE_UART6 && !defined(__DOXYGEN__) +extern UARTDriver UARTD7; +#endif + +#if TIVA_UART_USE_UART7 && !defined(__DOXYGEN__) +extern UARTDriver UARTD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/UART/.cproject b/testhal/TIVA/TM4C123x/UART/.cproject new file mode 100644 index 0000000..19e6606 --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/.cproject @@ -0,0 +1,68 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="0.114656749"> + <storageModule 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<key>org.eclipse.cdt.make.core.buildCommand</key> + <value>make</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.cleanBuildTarget</key> + <value>clean</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.contents</key> + <value>org.eclipse.cdt.make.core.activeConfigSettings</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableAutoBuild</key> + <value>false</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableCleanBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.enableFullBuild</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.fullBuildTarget</key> + <value>all</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.stopOnError</key> + <value>true</value> + </dictionary> + <dictionary> + <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key> + <value>true</value> + </dictionary> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>board</name> + <type>2</type> + <locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD</locationURI> + </link> + <link> + <name>community_os</name> + <type>2</type> + <locationURI>PARENT-1-CHIBIOS/ChibiOS-Contrib/os</locationURI> + </link> + <link> + <name>os</name> + <type>2</type> + <locationURI>CHIBIOS/os</locationURI> + </link> + </linkedResources> + <variableList> + <variable> + <name>CHIBIOS3</name> + <value>file:/C:/ChibiStudio/chibios3</value> + </variable> + </variableList> +</projectDescription> diff --git a/testhal/TIVA/TM4C123x/UART/Makefile b/testhal/TIVA/TM4C123x/UART/Makefile new file mode 100644 index 0000000..b7360e4 --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/Makefile @@ -0,0 +1,218 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../../../../ChibiOS-RT +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/TM4C123x/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/TM4C123xH6.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/testhal/TIVA/TM4C123x/UART/chconf.h b/testhal/TIVA/TM4C123x/UART/chconf.h new file mode 100644 index 0000000..0d24275 --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/chconf.h @@ -0,0 +1,510 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_5_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** + * @brief Realtime Counter frequency. + * @details Frequency of the system counter used for realtime delays and + * measurements. + */ +#define CH_CFG_RTC_FREQUENCY 80000000 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/UART/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch b/testhal/TIVA/TM4C123x/UART/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch new file mode 100644 index 0000000..0af6b44 --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/debug/OpenOCD on ICDI (prompts for .cfg target configuration).launch @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.ui.externaltools.ProgramLaunchConfigurationType"> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.ui.externaltools.launchGroup"/> +</listAttribute> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LAUNCH_CONFIGURATION_BUILD_SCOPE" value="${none}"/> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="${eclipse_home}\..\tools\openocd\bin\openocd.exe"/> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-c "telnet_port 4444" -f "interface/ti-icdi.cfg" -f "${file_prompt}""/> +<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${eclipse_home}\..\tools\openocd\scripts\"/> +</launchConfiguration> diff --git a/testhal/TIVA/TM4C123x/UART/debug/TM4C123x-UART (OpenOCD, Flash and Run).launch b/testhal/TIVA/TM4C123x/UART/debug/TM4C123x-UART (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..6e2f16c --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/debug/TM4C123x-UART (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType"> +<stringAttribute key="bad_container_name" value="\TM4C123x-UART\debug"/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset halt monitor reset init"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/> +<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/> +<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> +<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList/>"/> +<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="TM4C123x-UART"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/TM4C123x-UART"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/> +</listAttribute> +</launchConfiguration> diff --git a/testhal/TIVA/TM4C123x/UART/halconf.h b/testhal/TIVA/TM4C123x/UART/halconf.h new file mode 100644 index 0000000..e4a5517 --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/halconf.h @@ -0,0 +1,296 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#define UART_USE_WAIT TRUE + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/TIVA/TM4C123x/UART/main.c b/testhal/TIVA/TM4C123x/UART/main.c new file mode 100644 index 0000000..8abae57 --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/main.c @@ -0,0 +1,146 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +static virtual_timer_t vt1, vt2; + +static void restart(void *p) { + + (void)p; + + chSysLockFromISR(); + uartStartSendI(&UARTD1, 14, "Hello World!\r\n"); + chSysUnlockFromISR(); +} + +static void ledoff(void *p) { + + (void)p; + palClearLine(LINE_LED_RED); +} + +/* + * This callback is invoked when a transmission buffer has been completely + * read by the driver. + */ +static void txend1(UARTDriver *uartp) { + + (void)uartp; + palSetLine(LINE_LED_RED); +} + +/* + * This callback is invoked when a transmission has physically completed. + */ +static void txend2(UARTDriver *uartp) { + + (void)uartp; + palClearLine(LINE_LED_RED); + chSysLockFromISR(); + chVTResetI(&vt1); + chVTSetI(&vt1, MS2ST(5000), restart, NULL); + chSysUnlockFromISR(); +} + +/* + * This callback is invoked on a receive error, the errors mask is passed + * as parameter. + */ +static void rxerr(UARTDriver *uartp, uartflags_t e) { + + (void)uartp; + (void)e; +} + +/* + * This callback is invoked when a character is received but the application + * was not ready to receive it, the character is passed as parameter. + */ +static void rxchar(UARTDriver *uartp, uint16_t c) { + + (void)uartp; + (void)c; + /* Flashing the LED each time a character is received.*/ + palSetLine(LINE_LED_RED); + chSysLockFromISR(); + chVTResetI(&vt2); + chVTSetI(&vt2, MS2ST(200), ledoff, NULL); + chSysUnlockFromISR(); +} + +/* + * This callback is invoked when a receive buffer has been completely written. + */ +static void rxend(UARTDriver *uartp) { + + (void)uartp; +} + +/* + * UART driver configuration structure. + */ +static UARTConfig uart_cfg_1 = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + 38400, + 0, + UART_LCRH_FEN | UART_LCRH_WLEN_8, + UART_IFLS_TX4_8 | UART_IFLS_RX4_8, + UART_CC_CS_SYSCLK +}; + +/* + * Application entry point. + */ +int main(void) +{ + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + palSetLineMode(LINE_UART0_RX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1)); + palSetLineMode(LINE_UART0_TX, PAL_MODE_INPUT | PAL_MODE_ALTERNATE(1)); + + palSetLineMode(LINE_LED_RED, PAL_MODE_OUTPUT_PUSHPULL); + + /* + * Activates the uart driver 1. + */ + uartStart(&UARTD1, &uart_cfg_1); + + /* + * Starts the transmission, it will be handled entirely in background. + */ + uartStartSend(&UARTD1, 13, "Starting...\r\n"); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (true) { + chThdSleepMilliseconds(5000); + } +} diff --git a/testhal/TIVA/TM4C123x/UART/mcuconf.h b/testhal/TIVA/TM4C123x/UART/mcuconf.h new file mode 100644 index 0000000..c5f9bdf --- /dev/null +++ b/testhal/TIVA/TM4C123x/UART/mcuconf.h @@ -0,0 +1,196 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * TM4C123x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...Highest. + */ + +#define TM4C123x_MCUCONF + +/* + * HAL driver system settings. + */ +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO +#define TIVA_MOSC_ENABLE TRUE +#define TIVA_DIV400_VALUE 1 +#define TIVA_SYSDIV_VALUE 2 +#define TIVA_USESYSDIV_ENABLE FALSE +#define TIVA_SYSDIV2LSB_ENABLE FALSE +#define TIVA_BYPASS_VALUE 0 +#define TIVA_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) + +/* + * GPIO driver system settings. + */ +#define TIVA_GPIO_GPIOA_USE_AHB TRUE +#define TIVA_GPIO_GPIOB_USE_AHB TRUE +#define TIVA_GPIO_GPIOC_USE_AHB TRUE +#define TIVA_GPIO_GPIOD_USE_AHB TRUE +#define TIVA_GPIO_GPIOE_USE_AHB TRUE +#define TIVA_GPIO_GPIOF_USE_AHB TRUE + +/* + * GPT driver system settings. + */ +#define TIVA_GPT_USE_GPT0 FALSE +#define TIVA_GPT_USE_GPT1 FALSE +#define TIVA_GPT_USE_GPT2 FALSE +#define TIVA_GPT_USE_GPT3 FALSE +#define TIVA_GPT_USE_GPT4 FALSE +#define TIVA_GPT_USE_GPT5 FALSE +#define TIVA_GPT_USE_WGPT0 FALSE +#define TIVA_GPT_USE_WGPT1 FALSE +#define TIVA_GPT_USE_WGPT2 FALSE +#define TIVA_GPT_USE_WGPT3 FALSE +#define TIVA_GPT_USE_WGPT4 FALSE +#define TIVA_GPT_USE_WGPT5 FALSE + +#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7 +#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT0A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT1A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT2A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT3A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT4A_IRQ_PRIORITY 7 +#define TIVA_GPT_WGPT5A_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define TIVA_I2C_USE_I2C0 FALSE +#define TIVA_I2C_USE_I2C1 FALSE +#define TIVA_I2C_USE_I2C2 FALSE +#define TIVA_I2C_USE_I2C3 FALSE +#define TIVA_I2C_USE_I2C4 FALSE +#define TIVA_I2C_USE_I2C5 FALSE +#define TIVA_I2C_USE_I2C6 FALSE +#define TIVA_I2C_USE_I2C7 FALSE +#define TIVA_I2C_I2C0_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C1_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C2_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C3_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C4_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C5_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C6_IRQ_PRIORITY 4 +#define TIVA_I2C_I2C7_IRQ_PRIORITY 4 + +/* + * PWM driver system settings. + */ +#define TIVA_PWM_USE_PWM0 FALSE +#define TIVA_PWM_USE_PWM1 FALSE +#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_0_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_1_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_2_IRQ_PRIORITY 4 +#define TIVA_PWM_PWM1_3_IRQ_PRIORITY 4 + +/* + * SERIAL driver system settings. + */ +#define TIVA_SERIAL_USE_UART0 FALSE +#define TIVA_SERIAL_USE_UART1 FALSE +#define TIVA_SERIAL_USE_UART2 FALSE +#define TIVA_SERIAL_USE_UART3 FALSE +#define TIVA_SERIAL_USE_UART4 FALSE +#define TIVA_SERIAL_USE_UART5 FALSE +#define TIVA_SERIAL_USE_UART6 FALSE +#define TIVA_SERIAL_USE_UART7 FALSE +#define TIVA_SERIAL_UART0_PRIORITY 5 +#define TIVA_SERIAL_UART1_PRIORITY 5 +#define TIVA_SERIAL_UART2_PRIORITY 5 +#define TIVA_SERIAL_UART3_PRIORITY 5 +#define TIVA_SERIAL_UART4_PRIORITY 5 +#define TIVA_SERIAL_UART5_PRIORITY 5 +#define TIVA_SERIAL_UART6_PRIORITY 5 +#define TIVA_SERIAL_UART7_PRIORITY 5 + +/* + * UART driver system settings. + */ +#define TIVA_UART_USE_UART0 TRUE +#define TIVA_UART_USE_UART1 FALSE +#define TIVA_UART_USE_UART2 FALSE +#define TIVA_UART_USE_UART3 FALSE +#define TIVA_UART_USE_UART4 FALSE +#define TIVA_UART_USE_UART5 FALSE +#define TIVA_UART_USE_UART6 FALSE +#define TIVA_UART_USE_UART7 FALSE +#define TIVA_UART_UART0_PRIORITY 5 +#define TIVA_UART_UART1_PRIORITY 5 +#define TIVA_UART_UART2_PRIORITY 5 +#define TIVA_UART_UART3_PRIORITY 5 +#define TIVA_UART_UART4_PRIORITY 5 +#define TIVA_UART_UART5_PRIORITY 5 +#define TIVA_UART_UART6_PRIORITY 5 +#define TIVA_UART_UART7_PRIORITY 5 +#define TIVA_UART_UART0_RX_UDMA_CHANNEL 8 +#define TIVA_UART_UART1_RX_UDMA_CHANNEL 22 +#define TIVA_UART_UART2_RX_UDMA_CHANNEL 0 +#define TIVA_UART_UART3_RX_UDMA_CHANNEL 16 +#define TIVA_UART_UART4_RX_UDMA_CHANNEL 18 +#define TIVA_UART_UART5_RX_UDMA_CHANNEL 6 +#define TIVA_UART_UART6_RX_UDMA_CHANNEL 10 +#define TIVA_UART_UART7_RX_UDMA_CHANNEL 20 +#define TIVA_UART_UART0_TX_UDMA_CHANNEL 9 +#define TIVA_UART_UART1_TX_UDMA_CHANNEL 23 +#define TIVA_UART_UART2_TX_UDMA_CHANNEL 1 +#define TIVA_UART_UART3_TX_UDMA_CHANNEL 17 +#define TIVA_UART_UART4_TX_UDMA_CHANNEL 19 +#define TIVA_UART_UART5_TX_UDMA_CHANNEL 7 +#define TIVA_UART_UART6_TX_UDMA_CHANNEL 11 +#define TIVA_UART_UART7_TX_UDMA_CHANNEL 21 +#define TIVA_UART_UART0_RX_UDMA_MAPPING 0 +#define TIVA_UART_UART1_RX_UDMA_MAPPING 0 +#define TIVA_UART_UART2_RX_UDMA_MAPPING 1 +#define TIVA_UART_UART3_RX_UDMA_MAPPING 2 +#define TIVA_UART_UART4_RX_UDMA_MAPPING 2 +#define TIVA_UART_UART5_RX_UDMA_MAPPING 2 +#define TIVA_UART_UART6_RX_UDMA_MAPPING 2 +#define TIVA_UART_UART7_RX_UDMA_MAPPING 2 +#define TIVA_UART_UART0_TX_UDMA_MAPPING 0 +#define TIVA_UART_UART1_TX_UDMA_MAPPING 0 +#define TIVA_UART_UART2_TX_UDMA_MAPPING 1 +#define TIVA_UART_UART3_TX_UDMA_MAPPING 2 +#define TIVA_UART_UART4_TX_UDMA_MAPPING 2 +#define TIVA_UART_UART5_TX_UDMA_MAPPING 2 +#define TIVA_UART_UART6_TX_UDMA_MAPPING 2 +#define TIVA_UART_UART7_TX_UDMA_MAPPING 2 + +/* + * ST driver system settings. + */ +#define TIVA_ST_IRQ_PRIORITY 2 +#define TIVA_ST_USE_WIDE_TIMER TRUE +#define TIVA_ST_TIMER_NUMBER 5 +#define TIVA_ST_TIMER_LETTER A |