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Diffstat (limited to 'os/hal/ports/STM32/LLD/FSMCv1/fsmc.h')
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc.h31
1 files changed, 17 insertions, 14 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
index 21c58bd..4ca6e58 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
@@ -56,10 +56,7 @@
#define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
#endif
#if !defined(FSMC_Bank5_R_BASE)
- #define FSMC_Bank5_R_BASE (FMC_R_BASE + 0x0140)
- #endif
- #if !defined(FSMC_Bank_R_BASE)
- #define FSMC_Bank6_R_BASE (FMC_R_BASE + 0x0144)
+ #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
#endif
#else
#if !defined(FSMC_Bank1_R_BASE)
@@ -165,11 +162,20 @@ typedef struct {
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx))
- typedef struct {
- __IO uint32_t SDCR; /**< SDRAM control register */
- uint32_t RESERVED0; /**< Reserved */
- __IO uint32_t SDTR; /**< SDRAM timing register */
- } FSMC_SDRAM_TypeDef;
+
+typedef struct {
+ __IO uint32_t SDCR; /**< SDRAM control register */
+ uint32_t RESERVED; /**< Reserved */
+ __IO uint32_t SDTR; /**< SDRAM timing register */
+} FSMC_SDRAM_BANK_TypeDef;
+
+typedef struct {
+ FSMC_SDRAM_BANK_TypeDef banks[2]; /**< Banks mapping */
+ __IO uint32_t SDCMR; /**< SDRAM comand mode register */
+ __IO uint32_t SDRTR; /**< SDRAM refresh timer register */
+ __IO uint32_t SDSR; /**< SDRAM status register */
+} FSMC_SDRAM_TypeDef;
+
#endif
/**
@@ -296,11 +302,8 @@ struct FSMCDriver {
#endif
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx))
- #if STM32_SDRAM_USE_FSMC_SDRAM1
- FSMC_SDRAM_TypeDef *sdram1;
- #endif
- #if STM32_SDRAM_USE_FSMC_SDRAM2
- FSMC_SDRAM_TypeDef *sdram2;
+ #if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM1)
+ FSMC_SDRAM_TypeDef *sdram;
#endif
#endif
};