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Diffstat (limited to 'os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c')
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c200
1 files changed, 91 insertions, 109 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
index b738185..6ac6966 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram.c
@@ -54,18 +54,9 @@
/* Driver exported variables. */
/*===========================================================================*/
/**
- * @brief SDRAM1 driver identifier.
+ * @brief SDRAM driver identifier.
*/
-#if STM32_SDRAM_USE_FSMC_SDRAM1 || defined(__DOXYGEN__)
-SDRAMDriver SDRAMD1;
-#endif
-
-/**
- * @brief SDRAM2 driver identifier.
- */
-#if STM32_SDRAM_USE_FSMC_SDRAM2 || defined(__DOXYGEN__)
-SDRAMDriver SDRAMD2;
-#endif
+SDRAMDriver SDRAMD;
/*===========================================================================*/
/* Driver local types. */
@@ -80,77 +71,90 @@ SDRAMDriver SDRAMD2;
/*===========================================================================*/
/**
+ * @brief Wait until the SDRAM controller is ready.
+ *
+ * @notapi
+ */
+static void _sdram_wait_ready(void) {
+ /* Wait until the SDRAM controller is ready */
+ while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY);
+}
+
+/**
* @brief Executes the SDRAM memory initialization sequence.
*
* @param[in] sdramp pointer to the @p SDRAMDriver object
*
* @notapi
*/
-static void fsmc_sdram_init_sequence(uint32_t command_target) {
- uint32_t tmpreg;
- /* Step 3 -----------------------------------------------------------------*/
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
- /* Configure a clock configuration enable command */
- FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_CLK_Enabled |
- command_target |
- ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
- (0 << 9); // FMC_ModeRegisterDefinition = 0
- /* Step 4 -----------------------------------------------------------------*/
- /* Insert 10 ms delay */
+static void _sdram_init_sequence(void) {
+
+ uint32_t tmp = 0;
+ uint32_t command_target = 0;
+
+#if STM32_SDRAM_USE_FSMC_SDRAM1
+ command_target |= FMC_SDCMR_CTB1;
+#endif
+#if STM32_SDRAM_USE_FSMC_SDRAM2
+ command_target |= FMC_SDCMR_CTB2;
+#endif
+
+ /* Step 3: Configure a clock configuration enable command.*/
+ _sdram_wait_ready();
+ SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_CLK_Enabled |
+ command_target |
+ ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
+ (0 << 9); // FMC_ModeRegisterDefinition = 0
+
+ /* Step 4: Insert 10 ms delay.*/
chSysPolledDelayX(MS2ST(10));
- /* Step 5 -----------------------------------------------------------------*/
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
- /* Configure a PALL (precharge all) command */
- FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_PALL |
- command_target |
- ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
- (0 << 9); // FMC_ModeRegisterDefinition = 0
- /* Step 6 -----------------------------------------------------------------*/
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
- /* Configure a Auto-Refresh command: Send the first command */
- FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
- command_target |
- ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4
- (0 << 9); // FMC_ModeRegisterDefinition = 0
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
- /* Configure a Auto-Refresh command: Send the second command*/
- FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
- command_target |
- ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4
- (0 << 9); // FMC_ModeRegisterDefinition = 0
- /* Step 7 -----------------------------------------------------------------*/
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
- /* Program the external memory mode register */
- tmpreg = FMC_SDCMR_MRD_BURST_LENGTH_2 |
- FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
- FMC_SDCMR_MRD_CAS_LATENCY_3 |
- FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
- FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE;
- /* Send the command */
- FMC_Bank5_6->SDCMR = (uint32_t) FMC_Command_Mode_LoadMode |
- command_target |
- ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
- (tmpreg << 9);
- /* Step 8 -----------------------------------------------------------------*/
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
+
+ /* Step 5: Configure a PALL (precharge all) command.*/
+ _sdram_wait_ready();
+ SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_PALL |
+ command_target |
+ ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
+ (0 << 9); // FMC_ModeRegisterDefinition = 0
+
+ /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
+ _sdram_wait_ready();
+ SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
+ command_target |
+ ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4
+ (0 << 9); // FMC_ModeRegisterDefinition = 0
+
+ /* Step 6.2: Send the second command.*/
+ SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_AutoRefresh |
+ command_target |
+ ((4 -1) << 5) | // FMC_AutoRefreshNumber = 4
+ (0 << 9); // FMC_ModeRegisterDefinition = 0
+
+ /* Step 7: Program the external memory mode register.*/
+ _sdram_wait_ready();
+ tmp = FMC_SDCMR_MRD_BURST_LENGTH_2 |
+ FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
+ FMC_SDCMR_MRD_CAS_LATENCY_3 |
+ FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
+ FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE;
+ SDRAMD.sdram->SDCMR = (uint32_t) FMC_Command_Mode_LoadMode |
+ command_target |
+ ((1 -1) << 5) | // FMC_AutoRefreshNumber = 1
+ (tmp << 9);
+
+ /* Step 8: Set clock.*/
+ _sdram_wait_ready();
// 64ms/4096=15.625us
#if (STM32_SYSCLK == 180000000)
//15.625us*90MHz=1406-20=1386
- FMC_Bank5_6->SDRTR=1386<<1;
+ SDRAMD.sdram->SDRTR=1386<<1;
#elif (STM32_SYSCLK == 168000000)
//15.625us*84MHz=1312-20=1292
- FMC_Bank5_6->SDRTR=1292<<1;
+ SDRAMD.sdram->SDRTR=1292<<1;
#else
#error No refresh timings for this clock
#endif
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
+
+ _sdram_wait_ready();
}
/*===========================================================================*/
@@ -168,15 +172,8 @@ void fsmcSdramInit(void) {
fsmc_init();
-#if STM32_SDRAM_USE_FSMC_SDRAM1
- SDRAMD1.sdram = FSMCD1.sdram1;
- SDRAMD1.state = SDRAM_STOP;
-#endif /* STM32_SDRAM_USE_FSMC_SDRAM1 */
-
-#if STM32_SDRAM_USE_FSMC_SDRAM2
- SDRAMD2.sdram = FSMCD1.sdram2;
- SDRAMD2.state = SDRAM_STOP;
-#endif /* STM32_SDRAM_USE_FSMC_SDRAM2 */
+ SDRAMD.sdram = FSMCD1.sdram;
+ SDRAMD.state = SDRAM_STOP;
}
/**
@@ -191,24 +188,19 @@ void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) {
fsmc_start(&FSMCD1);
osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY),
- "invalid state");
+ "SDRAM. Invalid state.");
if (sdramp->state == SDRAM_STOP) {
- // Executes the SDRAM memory initialization sequence.
- if (sdramp->sdram == (FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE) {
- sdramp->sdram->SDCR = cfgp->sdcr;
- sdramp->sdram->SDTR = cfgp->sdtr;
- fsmc_sdram_init_sequence(FMC_Command_Target_bank1);
- }
- else { /* SDCR2 "don't care" bits configuration */
- ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE)->SDCR =
- cfgp->sdcr & SDCR2_DONTCARE_BITS;
- sdramp->sdram->SDCR = cfgp->sdcr;
- ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_R_BASE)->SDTR =
- cfgp->sdtr & SDTR2_DONTCARE_BITS;
- sdramp->sdram->SDTR = cfgp->sdtr;
- fsmc_sdram_init_sequence(FMC_Command_Target_bank2);
- }
+#if STM32_SDRAM_USE_FSMC_SDRAM1
+ sdramp->sdram->banks[0].SDCR = cfgp->sdcr1;
+ sdramp->sdram->banks[0].SDTR = cfgp->sdtr1;
+#endif
+#if STM32_SDRAM_USE_FSMC_SDRAM2
+ sdramp->sdram->banks[1].SDCR = cfgp->sdcr2;
+ sdramp->sdram->banks[1].SDTR = cfgp->sdtr2;
+#endif
+ _sdram_init_sequence();
+
sdramp->state = SDRAM_READY;
}
}
@@ -228,16 +220,6 @@ void fsmcSdramStop(SDRAMDriver *sdramp) {
}
/**
- * @brief Wait until the SDRAM controller is ready.
- *
- * @notapi
- */
-void fsmcSdram_WaitReady(void) {
- /* Wait until the SDRAM controller is ready */
- while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY);
-}
-
-/**
* @brief Enables or disables write protection to the specified SDRAM Bank.
* @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
@@ -245,13 +227,13 @@ void fsmcSdram_WaitReady(void) {
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state) {
-
- if (state)
- sdramp->sdram->SDCR |= FMC_Write_Protection_Enable;
- else
- sdramp->sdram->SDCR &= SDCR_WriteProtection_RESET;
-}
+//void fsmcSdram_WriteProtectionConfig(SDRAMDriver *sdramp, int state) {
+//
+// if (state)
+// sdramp->sdram->SDCR |= FMC_Write_Protection_Enable;
+// else
+// sdramp->sdram->SDCR &= SDCR_WriteProtection_RESET;
+//}
#endif /* STM32_USE_FSMC_SDRAM */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 17:56:08 +0000