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-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c24
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h6
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c30
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h119
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c17
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h5
6 files changed, 159 insertions, 42 deletions
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
index c04278e..ed4c5b8 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
@@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) {
if (&EICUD1 == eicup) {
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_EICU_USE_TIM2
if (&EICUD2 == eicup) {
nvicDisableVector(STM32_TIM2_NUMBER);
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_EICU_USE_TIM3
if (&EICUD3 == eicup) {
nvicDisableVector(STM32_TIM3_NUMBER);
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_EICU_USE_TIM4
if (&EICUD4 == eicup) {
nvicDisableVector(STM32_TIM4_NUMBER);
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_EICU_USE_TIM5
if (&EICUD5 == eicup) {
nvicDisableVector(STM32_TIM5_NUMBER);
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
#if STM32_EICU_USE_TIM8
if (&EICUD8 == eicup) {
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
#if STM32_EICU_USE_TIM9
if (&EICUD9 == eicup) {
nvicDisableVector(STM32_TIM9_NUMBER);
- rccDisableTIM9(FALSE);
+ rccDisableTIM9();
}
#endif
#if STM32_EICU_USE_TIM12
if (&EICUD12 == eicup) {
nvicDisableVector(STM32_TIM12_NUMBER);
- rccDisableTIM12(FALSE);
+ rccDisableTIM12();
}
#endif
}
#if STM32_EICU_USE_TIM10
if (&EICUD10 == eicup) {
nvicDisableVector(STM32_TIM10_NUMBER);
- rccDisableTIM10(FALSE);
+ rccDisableTIM10();
}
#endif
#if STM32_EICU_USE_TIM11
if (&EICUD11 == eicup) {
nvicDisableVector(STM32_TIM11_NUMBER);
- rccDisableTIM11(FALSE);
+ rccDisableTIM11();
}
#endif
#if STM32_EICU_USE_TIM13
if (&EICUD13 == eicup) {
nvicDisableVector(STM32_TIM13_NUMBER);
- rccDisableTIM13(FALSE);
+ rccDisableTIM13();
}
#endif
#if STM32_EICU_USE_TIM14
if (&EICUD14 == eicup) {
nvicDisableVector(STM32_TIM14_NUMBER);
- rccDisableTIM14(FALSE);
+ rccDisableTIM14();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h
index 927eb6f..e72098e 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.h
@@ -22,8 +22,8 @@
32-bit timers and timers with single capture/compare channels.
*/
-#ifndef __EICU_LLD_H
-#define __EICU_LLD_H
+#ifndef HAL_EICU_LLD_H
+#define HAL_EICU_LLD_H
#include "stm32_tim.h"
@@ -551,4 +551,4 @@ extern "C" {
#endif /* HAL_USE_EICU */
-#endif /* __EICU_LLD_H */
+#endif /* HAL_EICU_LLD_H */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index ea051f7..e07b946 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -150,6 +150,8 @@ void qei_lld_init(void) {
* @notapi
*/
void qei_lld_start(QEIDriver *qeip) {
+ osalDbgAssert((qeip->config->min == 0) || (qeip->config->max == 0),
+ "only min/max set to 0 is supported");
if (qeip->state == QEI_STOP) {
/* Clock activation and timer reset.*/
@@ -192,24 +194,24 @@ void qei_lld_start(QEIDriver *qeip) {
#endif
}
/* Timer configuration.*/
- qeip->tim->CR1 = 0; /* Initially stopped. */
+ qeip->tim->CR1 = 0; /* Initially stopped. */
qeip->tim->CR2 = 0;
qeip->tim->PSC = 0;
qeip->tim->DIER = 0;
- qeip->tim->ARR = 0xFFFF;
+ qeip->tim->ARR = 0xFFFF;
/* Set Capture Compare 1 and Capture Compare 2 as input. */
qeip->tim->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
if (qeip->config->mode == QEI_MODE_QUADRATURE) {
if (qeip->config->resolution == QEI_BOTH_EDGES)
- qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0;
else
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
} else {
/* Direction/Clock mode.
* Direction input on TI1, Clock input on TI2. */
- qeip->tim->SMCR = TIM_SMCR_SMS_0;
+ qeip->tim->SMCR = TIM_SMCR_SMS_0;
}
if (qeip->config->dirinv == QEI_DIRINV_TRUE)
@@ -228,38 +230,38 @@ void qei_lld_start(QEIDriver *qeip) {
void qei_lld_stop(QEIDriver *qeip) {
if (qeip->state == QEI_READY) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
/* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
}
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
}
@@ -273,7 +275,7 @@ void qei_lld_stop(QEIDriver *qeip) {
*/
void qei_lld_enable(QEIDriver *qeip) {
- qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
+ qeip->tim->CR1 = TIM_CR1_CEN; /* Timer enabled. */
}
/**
@@ -285,7 +287,7 @@ void qei_lld_enable(QEIDriver *qeip) {
*/
void qei_lld_disable(QEIDriver *qeip) {
- qeip->tim->CR1 = 0; /* Timer disabled. */
+ qeip->tim->CR1 = 0; /* Timer disabled. */
}
#endif /* HAL_USE_QEI */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
index d0cb683..73468f5 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.h
@@ -33,6 +33,16 @@
/* Driver constants. */
/*===========================================================================*/
+/**
+ * @brief Mininum usable value for defining counter underflow
+ */
+#define QEI_COUNT_MIN (0)
+
+/**
+ * @brief Maximum usable value for defining counter overflow
+ */
+#define QEI_COUNT_MAX (65535)
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -172,6 +182,56 @@
#error "QEI driver activated but no TIM peripheral assigned"
#endif
+/* Checks on allocation of TIMx units.*/
+#if STM32_QEI_USE_TIM1
+#if defined(STM32_TIM1_IS_USED)
+#error "QEID1 requires TIM1 but the timer is already used"
+#else
+#define STM32_TIM1_IS_USED
+#endif
+#endif
+
+#if STM32_QEI_USE_TIM2
+#if defined(STM32_TIM2_IS_USED)
+#error "QEID2 requires TIM2 but the timer is already used"
+#else
+#define STM32_TIM2_IS_USED
+#endif
+#endif
+
+#if STM32_QEI_USE_TIM3
+#if defined(STM32_TIM3_IS_USED)
+#error "QEID3 requires TIM3 but the timer is already used"
+#else
+#define STM32_TIM3_IS_USED
+#endif
+#endif
+
+#if STM32_QEI_USE_TIM4
+#if defined(STM32_TIM4_IS_USED)
+#error "QEID4 requires TIM4 but the timer is already used"
+#else
+#define STM32_TIM4_IS_USED
+#endif
+#endif
+
+#if STM32_QEI_USE_TIM5
+#if defined(STM32_TIM5_IS_USED)
+#error "QEID5 requires TIM5 but the timer is already used"
+#else
+#define STM32_TIM5_IS_USED
+#endif
+#endif
+
+#if STM32_QEI_USE_TIM8
+#if defined(STM32_TIM8_IS_USED)
+#error "QEID8 requires TIM8 but the timer is already used"
+#else
+#define STM32_TIM8_IS_USED
+#endif
+#endif
+
+/* IRQ priority checks.*/
#if STM32_QEI_USE_TIM1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_QEI_TIM1_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to TIM1"
@@ -202,6 +262,14 @@
#error "Invalid IRQ priority assigned to TIM8"
#endif
+#if QEI_USE_OVERFLOW_DISCARD
+#error "QEI_USE_OVERFLOW_DISCARD not supported by this driver"
+#endif
+
+#if QEI_USE_OVERFLOW_MINMAX
+#error "QEI_USE_OVERFLOW_MINMAX not supported by this driver"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -233,7 +301,7 @@ typedef enum {
/**
* @brief QEI counter type.
*/
-typedef uint16_t qeicnt_t;
+typedef int16_t qeicnt_t;
/**
* @brief QEI delta type.
@@ -257,6 +325,45 @@ typedef struct {
* @brief Direction inversion.
*/
qeidirinv_t dirinv;
+ /**
+ * @brief Handling of counter overflow/underflow
+ *
+ * @details When overflow occurs, the counter value is updated
+ * according to:
+ * - QEI_OVERFLOW_DISCARD:
+ * discard the update value, counter doesn't change
+ */
+ qeioverflow_t overflow;
+ /**
+ * @brief Min count value.
+ *
+ * @note If min == max, then QEI_COUNT_MIN is used.
+ *
+ * @note Only min set to 0 / QEI_COUNT_MIN is supported.
+ */
+ qeicnt_t min;
+ /**
+ * @brief Max count value.
+ *
+ * @note If min == max, then QEI_COUNT_MAX is used.
+ *
+ * @note Only max set to 0 / QEI_COUNT_MAX is supported.
+ */
+ qeicnt_t max;
+ /**
+ * @brief Notify of value change
+ *
+ * @note Called from ISR context.
+ */
+ qeicallback_t notify_cb;
+ /**
+ * @brief Notify of overflow
+ *
+ * @note Overflow notification is performed after
+ * value changed notification.
+ * @note Called from ISR context.
+ */
+ void (*overflow_cb)(QEIDriver *qeip, qeidelta_t delta);
/* End of the mandatory fields.*/
} QEIConfig;
@@ -300,6 +407,16 @@ struct QEIDriver {
*/
#define qei_lld_get_count(qeip) ((qeip)->tim->CNT)
+/**
+ * @brief Set the counter value.
+ *
+ * @param[in] qeip pointer to the @p QEIDriver object
+ * @param[in] qeip counter value
+ *
+ * @notapi
+ */
+#define qei_lld_set_count(qeip, value)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
index 8ab6176..d95c6a3 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
@@ -24,14 +24,13 @@
/**
- * @file STM32/timcap_lld.c
+ * @file STM32/hal_timcap_lld.c
* @brief STM32 TIMCAP subsystem low level driver header.
*
* @addtogroup TIMCAP
* @{
*/
-#include "ch.h"
#include "hal.h"
#if HAL_USE_TIMCAP || defined(__DOXYGEN__)
@@ -714,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) {
if (&TIMCAPD1 == timcapp) {
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_TIMCAP_USE_TIM2
if (&TIMCAPD2 == timcapp) {
nvicDisableVector(STM32_TIM2_NUMBER);
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_TIMCAP_USE_TIM3
if (&TIMCAPD3 == timcapp) {
nvicDisableVector(STM32_TIM3_NUMBER);
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_TIMCAP_USE_TIM4
if (&TIMCAPD4 == timcapp) {
nvicDisableVector(STM32_TIM4_NUMBER);
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_TIMCAP_USE_TIM5
if (&TIMCAPD5 == timcapp) {
nvicDisableVector(STM32_TIM5_NUMBER);
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
#if STM32_TIMCAP_USE_TIM8
if (&TIMCAPD8 == timcapp) {
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
#if STM32_TIMCAP_USE_TIM9
if (&TIMCAPD9 == timcapp) {
nvicDisableVector(STM32_TIM9_NUMBER);
- rccDisableTIM9(FALSE);
+ rccDisableTIM9();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h
index d39c438..621313a 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.h
@@ -22,10 +22,9 @@
* @{
*/
-#ifndef _TIMCAP_LLD_H_
-#define _TIMCAP_LLD_H_
+#ifndef HAL_TIMCAP_LLD_H_
+#define HAL_TIMCAP_LLD_H_
-#include "ch.h"
#include "hal.h"
#include "stm32_tim.h"
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 20:40:46 +0000