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-rwxr-xr-xos/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c24
-rw-r--r--os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h6
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c7
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h5
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c6
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h6
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c5
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c24
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c12
-rw-r--r--os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c14
-rw-r--r--os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c8
11 files changed, 75 insertions, 42 deletions
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
index a2cf026..180a383 100755
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
@@ -121,9 +121,14 @@ static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) {
/* Stop everything.*/
dmaStreamDisable(crcp->dma);
- /* Portable CRC ISR code defined in the high level driver, note, it is
- a macro.*/
- _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val);
+ if (crcp->rem_data_size) {
+ /* Start DMA follow up transfer for next data chunk */
+ crc_lld_start_calc(crcp, crcp->rem_data_size,
+ (const void *)crcp->dma->channel->CPAR+0xffff);
+ } else {
+ /* Portable CRC ISR code defined in the high level driver, note, it is a macro.*/
+ _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val);
+ }
}
#endif
@@ -155,7 +160,7 @@ void crc_lld_start(CRCDriver *crcp) {
if (crcp->config == NULL)
crcp->config = &default_config;
- rccEnableCRC(FALSE);
+ rccEnableCRC();
#if STM32_CRC_PROGRAMMABLE == TRUE
crcp->crc->INIT = crcp->config->initial_val;
@@ -234,7 +239,7 @@ void crc_lld_stop(CRCDriver *crcp) {
#else
(void)crcp;
#endif
- rccDisableCRC(FALSE);
+ rccDisableCRC();
}
/**
@@ -308,12 +313,17 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
#if CRC_USE_DMA == TRUE
void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) {
+ /* The STM32 DMA can only handle max 65535 bytes per transfer
+ * because it's data count register has only 16 bit. */
+ size_t sz = (n > 0xffff) ? 0xffff : n;
+ crcp->rem_data_size = n-sz;
+
dmaStreamSetPeripheral(crcp->dma, buf);
dmaStreamSetMemory0(crcp->dma, &crcp->crc->DR);
#if STM32_CRC_PROGRAMMABLE == TRUE
- dmaStreamSetTransactionSize(crcp->dma, n);
+ dmaStreamSetTransactionSize(crcp->dma, sz);
#else
- dmaStreamSetTransactionSize(crcp->dma, (n / 4));
+ dmaStreamSetTransactionSize(crcp->dma, (sz / 4));
#endif
dmaStreamSetMode(crcp->dma, crcp->dmamode);
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
index 213d346..e879103 100644
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
@@ -203,6 +203,12 @@ struct CRCDriver {
*/
thread_reference_t thread;
/**
+ * @brief Remaining data size.
+ * @note The DMA can handle only 65535 bytes per transfer because
+ * it's data count register is only 16 bits wide.
+ */
+ size_t rem_data_size;
+ /**
* @brief CRC DMA stream
*/
const stm32_dma_stream_t *dma;
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
index b4c2938..71c6ada 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
@@ -97,7 +97,10 @@ void fsmc_init(void) {
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
#if STM32_USE_FSMC_SDRAM
FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
#endif
@@ -156,7 +159,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
#if HAL_USE_NAND
nvicDisableVector(STM32_FSMC_NUMBER);
#endif
- rccDisableFSMC(FALSE);
+ rccDisableFSMC();
}
#endif /* STM32_FSMC_USE_FSMC1 */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
index 51b9428..80c5d26 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
@@ -36,7 +36,10 @@
*/
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
#if !defined(FSMC_Bank1_R_BASE)
#define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
index ac83477..6d727c8 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
@@ -28,7 +28,11 @@
#include "hal.h"
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx))
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
index b419168..c9f9de0 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
@@ -29,7 +29,11 @@
#define HAL_FMC_SDRAM_H_
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx))
+ defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
#include "hal_fsmc.h"
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
index fbd6f56..da13ca5 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
@@ -148,7 +148,10 @@ void fsmcSramStop(SRAMDriver *sramp) {
uint32_t mask = FSMC_BCR_MBKEN;
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F7))
+ defined(STM32F745xx) || defined(STM32F746xx) || \
+ defined(STM32F756xx) || defined(STM32F767xx) || \
+ defined(STM32F769xx) || defined(STM32F777xx) || \
+ defined(STM32F779xx))
mask |= FSMC_BCR_CCLKEN;
#endif
sramp->sram->BCR &= ~mask;
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
index c04278e..ed4c5b8 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
@@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) {
if (&EICUD1 == eicup) {
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_EICU_USE_TIM2
if (&EICUD2 == eicup) {
nvicDisableVector(STM32_TIM2_NUMBER);
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_EICU_USE_TIM3
if (&EICUD3 == eicup) {
nvicDisableVector(STM32_TIM3_NUMBER);
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_EICU_USE_TIM4
if (&EICUD4 == eicup) {
nvicDisableVector(STM32_TIM4_NUMBER);
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_EICU_USE_TIM5
if (&EICUD5 == eicup) {
nvicDisableVector(STM32_TIM5_NUMBER);
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
#if STM32_EICU_USE_TIM8
if (&EICUD8 == eicup) {
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
#if STM32_EICU_USE_TIM9
if (&EICUD9 == eicup) {
nvicDisableVector(STM32_TIM9_NUMBER);
- rccDisableTIM9(FALSE);
+ rccDisableTIM9();
}
#endif
#if STM32_EICU_USE_TIM12
if (&EICUD12 == eicup) {
nvicDisableVector(STM32_TIM12_NUMBER);
- rccDisableTIM12(FALSE);
+ rccDisableTIM12();
}
#endif
}
#if STM32_EICU_USE_TIM10
if (&EICUD10 == eicup) {
nvicDisableVector(STM32_TIM10_NUMBER);
- rccDisableTIM10(FALSE);
+ rccDisableTIM10();
}
#endif
#if STM32_EICU_USE_TIM11
if (&EICUD11 == eicup) {
nvicDisableVector(STM32_TIM11_NUMBER);
- rccDisableTIM11(FALSE);
+ rccDisableTIM11();
}
#endif
#if STM32_EICU_USE_TIM13
if (&EICUD13 == eicup) {
nvicDisableVector(STM32_TIM13_NUMBER);
- rccDisableTIM13(FALSE);
+ rccDisableTIM13();
}
#endif
#if STM32_EICU_USE_TIM14
if (&EICUD14 == eicup) {
nvicDisableVector(STM32_TIM14_NUMBER);
- rccDisableTIM14(FALSE);
+ rccDisableTIM14();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index 6138481..e07b946 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -235,33 +235,33 @@ void qei_lld_stop(QEIDriver *qeip) {
/* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
}
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
index 37a48fd..d95c6a3 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
@@ -713,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) {
if (&TIMCAPD1 == timcapp) {
nvicDisableVector(STM32_TIM1_UP_NUMBER);
nvicDisableVector(STM32_TIM1_CC_NUMBER);
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_TIMCAP_USE_TIM2
if (&TIMCAPD2 == timcapp) {
nvicDisableVector(STM32_TIM2_NUMBER);
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_TIMCAP_USE_TIM3
if (&TIMCAPD3 == timcapp) {
nvicDisableVector(STM32_TIM3_NUMBER);
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_TIMCAP_USE_TIM4
if (&TIMCAPD4 == timcapp) {
nvicDisableVector(STM32_TIM4_NUMBER);
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_TIMCAP_USE_TIM5
if (&TIMCAPD5 == timcapp) {
nvicDisableVector(STM32_TIM5_NUMBER);
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
#if STM32_TIMCAP_USE_TIM8
if (&TIMCAPD8 == timcapp) {
nvicDisableVector(STM32_TIM8_UP_NUMBER);
nvicDisableVector(STM32_TIM8_CC_NUMBER);
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
#if STM32_TIMCAP_USE_TIM9
if (&TIMCAPD9 == timcapp) {
nvicDisableVector(STM32_TIM9_NUMBER);
- rccDisableTIM9(FALSE);
+ rccDisableTIM9();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
index 0403eae..226f1bb 100644
--- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
+++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
@@ -1673,9 +1673,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
* despite reporting a successful por enable. */
uerr("Detected enabled port; resetting OTG core");
otg->GAHBCFG = 0;
- osalThreadSleepS(MS2ST(20));
+ osalThreadSleepS(OSAL_MS2I(20));
_usbh_start(usbh); /* this effectively resets the core */
- osalThreadSleepS(MS2ST(100)); /* during this delay, the core generates connect ISR */
+ osalThreadSleepS(OSAL_MS2I(100)); /* during this delay, the core generates connect ISR */
uinfo("OTG reset ended");
if (otg->HPRT & HPRT_PCSTS) {
/* if the device is still connected, don't report a C_CONNECTION flag, which would cause
@@ -1688,9 +1688,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG);
while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0);
otg->HPRT = hprt | HPRT_PRST;
- osalThreadSleepS(MS2ST(15));
+ osalThreadSleepS(OSAL_MS2I(15));
otg->HPRT = hprt;
- osalThreadSleepS(MS2ST(10));
+ osalThreadSleepS(OSAL_MS2I(10));
usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET;
osalSysUnlock();
} break;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 18:12:37 +0000