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-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc.c188
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc.h311
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c159
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h173
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c515
-rw-r--r--os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h335
-rw-r--r--os/hal/ports/STM32/STM32F4xx/platform.mk7
7 files changed, 1688 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c
new file mode 100644
index 0000000..4c1a197
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c
@@ -0,0 +1,188 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file fsmc.c
+ * @brief FSMC Driver subsystem low level driver source template.
+ *
+ * @addtogroup FSMC
+ * @{
+ */
+#include "hal.h"
+#include "fsmc.h"
+
+#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief FSMC1 driver identifier.
+ */
+#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__)
+FSMCDriver FSMCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level FSMC driver initialization.
+ *
+ * @notapi
+ */
+void fsmc_init(void) {
+
+ if (FSMCD1.state == FSMC_UNINIT) {
+ FSMCD1.state = FSMC_STOP;
+
+#if STM32_SRAM_USE_FSMC_SRAM1
+ FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE);
+#endif
+
+#if STM32_SRAM_USE_FSMC_SRAM2
+ FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8);
+#endif
+
+#if STM32_SRAM_USE_FSMC_SRAM3
+ FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2);
+#endif
+
+#if STM32_SRAM_USE_FSMC_SRAM4
+ FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3);
+#endif
+
+#if STM32_NAND_USE_FSMC_NAND1
+ FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
+#endif
+
+#if STM32_NAND_USE_FSMC_NAND2
+ FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
+#endif
+
+#if STM32_USE_FSMC_PCCARD
+ FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE;
+#endif
+ }
+}
+
+/**
+ * @brief Configures and activates the FSMC peripheral.
+ *
+ * @param[in] fsmcp pointer to the @p FSMCDriver object
+ *
+ * @notapi
+ */
+void fsmc_start(FSMCDriver *fsmcp) {
+
+ osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY),
+ "invalid state");
+
+ if (fsmcp->state == FSMC_STOP) {
+ /* Enables the peripheral.*/
+#if STM32_FSMC_USE_FSMC1
+ if (&FSMCD1 == fsmcp) {
+ rccResetFSMC();
+ rccEnableFSMC(FALSE);
+#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
+ nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY);
+#endif
+ }
+#endif /* STM32_FSMC_USE_FSMC1 */
+
+ fsmcp->state = FSMC_READY;
+ }
+}
+
+/**
+ * @brief Deactivates the FSMC peripheral.
+ *
+ * @param[in] emcp pointer to the @p FSMCDriver object
+ *
+ * @notapi
+ */
+void fsmc_stop(FSMCDriver *fsmcp) {
+
+ if (fsmcp->state == FSMC_READY) {
+ /* Resets the peripheral.*/
+ rccResetFSMC();
+
+ /* Disables the peripheral.*/
+#if STM32_FSMC_USE_FSMC1
+ if (&FSMCD1 == fsmcp) {
+#if (!STM32_NAND_USE_EXT_INT && HAL_USE_NAND)
+ nvicDisableVector(STM32_FSMC_NUMBER);
+#endif
+ rccDisableFSMC(FALSE);
+ }
+#endif /* STM32_FSMC_USE_FSMC1 */
+
+ fsmcp->state = FSMC_STOP;
+ }
+}
+
+#if !STM32_NAND_USE_EXT_INT
+/**
+ * @brief FSMC shared interrupt handler.
+ *
+ * @notapi
+ */
+CH_IRQ_HANDLER(STM32_FSMC_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+#if STM32_NAND_USE_FSMC_NAND1
+ if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK){
+ NANDD1.isr_handler(&NANDD1);
+ }
+#endif
+#if STM32_NAND_USE_FSMC_NAND2
+ if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK){
+ NANDD2.isr_handler(&NANDD2);
+ }
+#endif
+ CH_IRQ_EPILOGUE();
+}
+#endif /* !STM32_NAND_USE_EXT_INT */
+
+#endif /* HAL_USE_FSMC || STM32_USE_FSMC_SRAM */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
new file mode 100644
index 0000000..2b579a2
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h
@@ -0,0 +1,311 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file fsmc.h
+ * @brief FSMC Driver subsystem low level driver header.
+ *
+ * @addtogroup FSMC
+ * @{
+ */
+
+#ifndef _FSMC_H_
+#define _FSMC_H_
+
+#if HAL_USE_NAND || STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * (Re)define if needed base address constants supplied in ST's CMSIS
+ */
+#if (defined(STM32F427xx) || defined(STM32F437xx) || \
+ defined(STM32F429xx) || defined(STM32F439xx))
+ #if !defined(FSMC_Bank1_R_BASE)
+ #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+ #endif
+ #if !defined(FSMC_Bank1E_R_BASE)
+ #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+ #endif
+ #if !defined(FSMC_Bank2_R_BASE)
+ #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
+ #endif
+ #if !defined(FSMC_Bank3_R_BASE)
+ #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+ #endif
+ #if !defined(FSMC_Bank4_R_BASE)
+ #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+ #endif
+ #if !defined(FSMC_Bank5_R_BASE)
+ #define FSMC_Bank5_R_BASE (FMC_R_BASE + 0x0140)
+ #endif
+ #if !defined(FSMC_Bank_R_BASE)
+ #define FSMC_Bank6_R_BASE (FMC_R_BASE + 0x0144)
+ #endif
+#else
+ #if !defined(FSMC_Bank1_R_BASE)
+ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
+ #endif
+ #if !defined(FSMC_Bank1E_R_BASE)
+ #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
+ #endif
+ #if !defined(FSMC_Bank2_R_BASE)
+ #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
+ #endif
+ #if !defined(FSMC_Bank3_R_BASE)
+ #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
+ #endif
+ #if !defined(FSMC_Bank4_R_BASE)
+ #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
+ #endif
+#endif
+
+/*
+ * Base bank mappings
+ */
+#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000)
+#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000)
+#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
+#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
+
+/*
+ * Subbunks of bank1
+ */
+#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
+#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
+#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
+#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
+#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
+
+/*
+ * Bank 2 (NAND)
+ */
+#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0)
+#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000)
+
+#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0)
+#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000)
+#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000)
+
+#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0)
+#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000)
+#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000)
+
+/*
+ * Bank 3 (NAND)
+ */
+#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0)
+#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000)
+
+#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0)
+#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000)
+#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000)
+
+#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0)
+#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000)
+#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000)
+
+/*
+ * Bank 4 (PC card)
+ */
+#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0)
+#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000)
+#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000)
+
+/*
+ * More convenient typedefs than CMSIS has
+ */
+typedef struct {
+ __IO uint32_t PCR; /**< NAND Flash control */
+ __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */
+ __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */
+ __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */
+ uint32_t RESERVED0; /**< Reserved, 0x70 */
+ __IO uint32_t ECCR; /**< NAND Flash ECC result registers */
+} FSMC_NAND_TypeDef;
+
+typedef struct {
+ __IO uint32_t PCR; /**< PC Card control */
+ __IO uint32_t SR; /**< PC Card FIFO status and interrupt */
+ __IO uint32_t PMEM; /**< PC Card Common memory space timing */
+ __IO uint32_t PATT; /**< PC Card Attribute memory space timing */
+ __IO uint32_t PIO; /**< PC Card I/O space timing */
+} FSMC_PCCard_TypeDef;
+
+typedef struct {
+ __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
+ __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
+ uint32_t RESERVED[63]; /**< Reserved */
+ __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
+} FSMC_SRAM_NOR_TypeDef;
+
+/**
+ * @brief PCR register
+ */
+#define FSMC_PCR_PWAITEN ((uint32_t)0x00000002)
+#define FSMC_PCR_PBKEN ((uint32_t)0x00000004)
+#define FSMC_PCR_PTYP ((uint32_t)0x00000008)
+#define FSMC_PCR_ECCEN ((uint32_t)0x00000040)
+#define FSMC_PCR_PTYP_PCCARD 0
+#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP
+
+/**
+ * @brief SR register
+ */
+#define FSMC_SR_IRS ((uint8_t)0x01)
+#define FSMC_SR_ILS ((uint8_t)0x02)
+#define FSMC_SR_IFS ((uint8_t)0x04)
+#define FSMC_SR_IREN ((uint8_t)0x08)
+#define FSMC_SR_ILEN ((uint8_t)0x10)
+#define FSMC_SR_IFEN ((uint8_t)0x20)
+#define FSMC_SR_FEMPT ((uint8_t)0x40)
+#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
+
+/**
+ * @brief BCR register
+ */
+#define FSMC_BCR_MBKEN ((uint32_t)0x00000001)
+#define FSMC_BCR_MUXEN ((uint32_t)0x00000002)
+#define FSMC_BCR_MWID_0 ((uint32_t)0x00000010)
+#define FSMC_BCR_FACCEN ((uint32_t)0x00000040)
+#define FSMC_BCR_BURSTEN ((uint32_t)0x00000100)
+#define FSMC_BCR_WAITPOL ((uint32_t)0x00000200)
+#define FSMC_BCR_WRAPMOD ((uint32_t)0x00000400)
+#define FSMC_BCR_WAITCFG ((uint32_t)0x00000800)
+#define FSMC_BCR_WREN ((uint32_t)0x00001000)
+#define FSMC_BCR_WAITEN ((uint32_t)0x00002000)
+#define FSMC_BCR_EXTMOD ((uint32_t)0x00004000)
+#define FSMC_BCR_ASYNCWAIT ((uint32_t)0x00008000)
+#define FSMC_BCR_CBURSTRW ((uint32_t)0x00080000)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief FSMC driver enable switch.
+ * @details If set to @p TRUE the support for FSMC is included.
+ */
+#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__)
+#define STM32_FSMC_USE_FSMC1 FALSE
+#endif
+
+/**
+ * @brief Internal FSMC interrupt enable switch
+ * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC.
+ * You have to use EXTI module instead to workaround this issue.
+ */
+#if !defined(STM32_NAND_USE_EXT_INT) || defined(__DOXYGEN__)
+#define STM32_NAND_USE_EXT_INT FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+#if !STM32_FSMC_USE_FSMC1
+#error "FSMC driver activated but no FSMC peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an FSMC driver.
+ */
+typedef struct FSMCDriver FSMCDriver;
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ FSMC_UNINIT = 0, /**< Not initialized. */
+ FSMC_STOP = 1, /**< Stopped. */
+ FSMC_READY = 2, /**< Ready. */
+} fsmcstate_t;
+
+/**
+ * @brief Structure representing an FSMC driver.
+ */
+struct FSMCDriver {
+ /**
+ * @brief Driver state.
+ */
+ fsmcstate_t state;
+ /* End of the mandatory fields.*/
+
+#if STM32_SRAM_USE_FSMC_SRAM1
+ FSMC_SRAM_NOR_TypeDef *sram1;
+#endif
+#if STM32_SRAM_USE_FSMC_SRAM2
+ FSMC_SRAM_NOR_TypeDef *sram2;
+#endif
+#if STM32_SRAM_USE_FSMC_SRAM3
+ FSMC_SRAM_NOR_TypeDef *sram3;
+#endif
+#if STM32_SRAM_USE_FSMC_SRAM4
+ FSMC_SRAM_NOR_TypeDef *sram4;
+#endif
+#if STM32_NAND_USE_FSMC_NAND1
+ FSMC_NAND_TypeDef *nand1;
+#endif
+#if STM32_NAND_USE_FSMC_NAND2
+ FSMC_NAND_TypeDef *nand2;
+#endif
+#if STM32_USE_FSMC_PCCARD
+ FSMC_PCCard_TypeDef *pccard;
+#endif
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__)
+extern FSMCDriver FSMCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void fsmc_init(void);
+ void fsmc_start(FSMCDriver *fsmcp);
+ void fsmc_stop(FSMCDriver *fsmcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_NAND || STM32_USE_FSMC_SRAM */
+
+#endif /* _FSMC_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
new file mode 100644
index 0000000..44f7ff2
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
@@ -0,0 +1,159 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file fsmc_sram.c
+ * @brief SRAM Driver subsystem low level driver source.
+ *
+ * @addtogroup SRAM
+ * @{
+ */
+#include "hal.h"
+#include "fsmc_sram.h"
+
+#if STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+/**
+ * @brief SRAM1 driver identifier.
+ */
+#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__)
+SRAMDriver SRAMD1;
+#endif
+
+/**
+ * @brief SRAM2 driver identifier.
+ */
+#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__)
+SRAMDriver SRAMD2;
+#endif
+
+/**
+ * @brief SRAM3 driver identifier.
+ */
+#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__)
+SRAMDriver SRAMD3;
+#endif
+
+/**
+ * @brief SRAM4 driver identifier.
+ */
+#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__)
+SRAMDriver SRAMD4;
+#endif
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SRAM driver initialization.
+ *
+ * @notapi
+ */
+void fsmcSramInit(void) {
+
+ fsmc_init();
+
+#if STM32_SRAM_USE_FSMC_SRAM1
+ SRAMD1.sram = FSMCD1.sram1;
+ SRAMD1.state = SRAM_STOP;
+#endif /* STM32_SRAM_USE_FSMC_SRAM1 */
+
+#if STM32_SRAM_USE_FSMC_SRAM2
+ SRAMD2.sram = FSMCD1.sram2;
+ SRAMD2.state = SRAM_STOP;
+#endif /* STM32_SRAM_USE_FSMC_SRAM2 */
+
+#if STM32_SRAM_USE_FSMC_SRAM3
+ SRAMD3.sram = FSMCD1.sram3;
+ SRAMD3.state = SRAM_STOP;
+#endif /* STM32_SRAM_USE_FSMC_SRAM3 */
+
+#if STM32_SRAM_USE_FSMC_SRAM4
+ SRAMD4.sram = FSMCD1.sram4;
+ SRAMD4.state = SRAM_STOP;
+#endif /* STM32_SRAM_USE_FSMC_SRAM4 */
+}
+
+/**
+ * @brief Configures and activates the SRAM peripheral.
+ *
+ * @param[in] sramp pointer to the @p SRAMDriver object
+ * @param[in] cfgp pointer to the @p SRAMConfig object
+ *
+ * @notapi
+ */
+void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) {
+
+ if (FSMCD1.state == FSMC_STOP)
+ fsmc_start(&FSMCD1);
+
+ osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY),
+ "invalid state");
+
+ if (sramp->state == SRAM_STOP) {
+ sramp->sram->BCR = FSMC_BCR_WREN | FSMC_BCR_MBKEN | FSMC_BCR_MWID_0;
+ sramp->sram->BTR = cfgp->btr;
+ sramp->state = SRAM_READY;
+ }
+}
+
+/**
+ * @brief Deactivates the SRAM peripheral.
+ *
+ * @param[in] sramp pointer to the @p SRAMDriver object
+ *
+ * @notapi
+ */
+void fsmcSramStop(SRAMDriver *sramp) {
+
+ if (sramp->state == SRAM_READY) {
+ sramp->sram->BCR &= ~FSMC_BCR_MBKEN;
+ sramp->state = SRAM_STOP;
+ }
+}
+
+#endif /* STM32_USE_FSMC_SRAM */
+
+/** @} */
+
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h
new file mode 100644
index 0000000..0113a04
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.h
@@ -0,0 +1,173 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file fsmc_sram.h
+ * @brief SRAM Driver subsystem low level driver header.
+ *
+ * @addtogroup SRAM
+ * @{
+ */
+
+#ifndef _FSMC_SRAM_H_
+#define _FSMC_SRAM_H_
+
+#include "fsmc.h"
+
+#if STM32_USE_FSMC_SRAM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM1 is included.
+ */
+#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
+#endif
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM2 is included.
+ */
+#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
+#endif
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM3 is included.
+ */
+#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
+#endif
+
+/**
+ * @brief SRAM driver enable switch.
+ * @details If set to @p TRUE the support for SRAM4 is included.
+ */
+#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__)
+#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \
+ !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4
+#error "SRAM driver activated but no SRAM peripheral assigned"
+#endif
+
+#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \
+ STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC
+#error "FSMC not present in the selected device"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ SRAM_UNINIT = 0, /**< Not initialized. */
+ SRAM_STOP = 1, /**< Stopped. */
+ SRAM_READY = 2, /**< Ready. */
+} sramstate_t;
+
+/**
+ * @brief Type of a structure representing an NAND driver.
+ */
+typedef struct SRAMDriver SRAMDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ uint32_t btr;
+} SRAMConfig;
+
+/**
+ * @brief Structure representing an NAND driver.
+ */
+struct SRAMDriver {
+ /**
+ * @brief Driver state.
+ */
+ sramstate_t state;
+ /**
+ * @brief Pointer to the FSMC SRAM registers block.
+ */
+ FSMC_SRAM_NOR_TypeDef *sram;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD1;
+#endif
+
+#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD2;
+#endif
+
+#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD3;
+#endif
+
+#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__)
+extern SRAMDriver SRAMD4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void fsmcSramInit(void);
+ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp);
+ void fsmcSramStop(SRAMDriver *sramp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_USE_FSMC_SRAM */
+
+#endif /* _FSMC_SRAM_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
new file mode 100644
index 0000000..3739e88
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
@@ -0,0 +1,515 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file nand_lld.c
+ * @brief NAND Driver subsystem low level driver source.
+ *
+ * @addtogroup NAND
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_NAND || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+#define NAND_DMA_CHANNEL \
+ STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \
+ STM32_FSMC_DMA_CHN)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief NAND1 driver identifier.
+ */
+#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__)
+NANDDriver NANDD1;
+#endif
+
+/**
+ * @brief NAND2 driver identifier.
+ */
+#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__)
+NANDDriver NANDD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Wakes up the waiting thread.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[in] msg wakeup message
+ *
+ * @notapi
+ */
+static void wakeup_isr(NANDDriver *nandp){
+
+ osalDbgCheck(nandp->thread != NULL);
+ osalThreadResumeI(&nandp->thread, MSG_OK);
+}
+
+/**
+ * @brief Put calling thread in suspend and switch driver state
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ */
+static void nand_lld_suspend_thread(NANDDriver *nandp) {
+
+ osalThreadSuspendS(&nandp->thread);
+}
+
+/**
+ * @brief Caclulate ECCPS register value
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ */
+static uint32_t calc_eccps(NANDDriver *nandp){
+
+ uint32_t i = 0;
+ uint32_t eccps = nandp->config->page_data_size;
+
+ eccps = eccps >> 9;
+ while (eccps > 0){
+ i++;
+ eccps >>= 1;
+ }
+
+ return i << 17;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief Enable interrupts from NAND
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ *
+ * @notapi
+ */
+static void nand_ready_isr_enable(NANDDriver *nandp) {
+#if STM32_NAND_USE_EXT_INT
+ nandp->config->ext_nand_isr_enable();
+#else
+ nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS |
+ FSMC_SR_ILEN | FSMC_SR_IFEN);
+ nandp->nand->SR |= FSMC_SR_IREN;
+#endif
+}
+
+/**
+ * @brief Disable interrupts from NAND
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ *
+ * @notapi
+ */
+static void nand_ready_isr_disable(NANDDriver *nandp) {
+#if STM32_NAND_USE_EXT_INT
+ nandp->config->ext_nand_isr_disable();
+#else
+ nandp->nand->SR &= ~FSMC_SR_IREN;
+#endif
+}
+
+/**
+ * @brief Ready interrupt handler
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ *
+ * @notapi
+ */
+static void nand_isr_handler (NANDDriver *nandp){
+
+ osalSysLockFromISR();
+
+#if !STM32_NAND_USE_EXT_INT
+ osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */
+ nandp->nand->SR &= ~FSMC_SR_IRS;
+#endif
+
+ switch (nandp->state){
+ case NAND_READ:
+ nandp->state = NAND_DMA_RX;
+ dmaStartMemCopy(nandp->dma, nandp->dmamode,
+ nandp->map_data, nandp->rxdata, nandp->datalen);
+ /* thread will be waked up from DMA ISR */
+ break;
+
+ case NAND_ERASE:
+ /* NAND reports about erase finish */
+ nandp->state = NAND_READY;
+ wakeup_isr(nandp);
+ break;
+
+ case NAND_PROGRAM:
+ /* NAND reports about page programming finish */
+ nandp->state = NAND_READY;
+ wakeup_isr(nandp);
+ break;
+
+ default:
+ osalSysHalt("Unhandled case");
+ break;
+ }
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief DMA RX end IRQ handler.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[in] flags pre-shifted content of the ISR register
+ *
+ * @notapi
+ */
+static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) {
+ /* DMA errors handling.*/
+#if defined(STM32_NAND_DMA_ERROR_HOOK)
+ if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+ STM32_NAND_DMA_ERROR_HOOK(nandp);
+ }
+#else
+ (void)flags;
+#endif
+
+ osalSysLockFromISR();
+
+ dmaStreamDisable(nandp->dma);
+
+ switch (nandp->state){
+ case NAND_DMA_TX:
+ nandp->state = NAND_PROGRAM;
+ nandp->map_cmd[0] = NAND_CMD_PAGEPROG;
+ /* thread will be woken from ready_isr() */
+ break;
+
+ case NAND_DMA_RX:
+ nandp->state = NAND_READY;
+ nandp->rxdata = NULL;
+ nandp->datalen = 0;
+ wakeup_isr(nandp);
+ break;
+
+ default:
+ osalSysHalt("Unhandled case");
+ break;
+ }
+
+ osalSysUnlockFromISR();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level NAND driver initialization.
+ *
+ * @notapi
+ */
+void nand_lld_init(void) {
+
+ fsmc_init();
+
+#if STM32_NAND_USE_FSMC_NAND1
+ /* Driver initialization.*/
+ nandObjectInit(&NANDD1);
+ NANDD1.rxdata = NULL;
+ NANDD1.datalen = 0;
+ NANDD1.thread = NULL;
+ NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
+ NANDD1.nand = FSMCD1.nand1;
+ NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA;
+ NANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD;
+ NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR;
+#endif /* STM32_NAND_USE_FSMC_NAND1 */
+
+#if STM32_NAND_USE_FSMC_NAND2
+ /* Driver initialization.*/
+ nandObjectInit(&NANDD2);
+ NANDD2.rxdata = NULL;
+ NANDD2.datalen = 0;
+ NANDD2.thread = NULL;
+ NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
+ NANDD2.nand = FSMCD1.nand2;
+ NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA;
+ NANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD;
+ NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR;
+#endif /* STM32_NAND_USE_FSMC_NAND2 */
+}
+
+/**
+ * @brief Configures and activates the NAND peripheral.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ *
+ * @notapi
+ */
+void nand_lld_start(NANDDriver *nandp) {
+
+ bool b;
+
+ if (FSMCD1.state == FSMC_STOP)
+ fsmc_start(&FSMCD1);
+
+ if (nandp->state == NAND_STOP) {
+ b = dmaStreamAllocate(nandp->dma,
+ STM32_EMC_FSMC1_IRQ_PRIORITY,
+ (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq,
+ (void *)nandp);
+ osalDbgAssert(!b, "stream already allocated");
+ nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) |
+ STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) |
+ STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
+ STM32_DMA_CR_TCIE;
+ /* dmaStreamSetFIFO(nandp->dma,
+ STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */
+ nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN;
+ nandp->nand->PMEM = nandp->config->pmem;
+ nandp->nand->PATT = nandp->config->pmem;
+ nandp->isr_handler = nand_isr_handler;
+ nand_ready_isr_enable(nandp);
+ }
+}
+
+/**
+ * @brief Deactivates the NAND peripheral.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ *
+ * @notapi
+ */
+void nand_lld_stop(NANDDriver *nandp) {
+
+ if (nandp->state == NAND_READY) {
+ dmaStreamRelease(nandp->dma);
+ nandp->nand->PCR &= ~FSMC_PCR_PBKEN;
+ nand_ready_isr_disable(nandp);
+ nandp->isr_handler = NULL;
+ }
+}
+
+/**
+ * @brief Read data from NAND.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[out] data pointer to data buffer
+ * @param[in] datalen size of data buffer
+ * @param[in] addr pointer to address buffer
+ * @param[in] addrlen length of address
+ * @param[out] ecc pointer to store computed ECC. Ignored when NULL.
+ *
+ * @notapi
+ */
+void nand_lld_read_data(NANDDriver *nandp, uint8_t *data,
+ size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){
+
+ nandp->state = NAND_READ;
+ nandp->rxdata = data;
+ nandp->datalen = datalen;
+
+ nand_lld_write_cmd (nandp, NAND_CMD_READ0);
+ nand_lld_write_addr(nandp, addr, addrlen);
+ osalSysLock();
+ nand_lld_write_cmd (nandp, NAND_CMD_READ0_CONFIRM);
+
+ /* Here NAND asserts busy signal and starts transferring from memory
+ array to page buffer. After the end of transmission ready_isr functions
+ starts DMA transfer from page buffer to MCU's RAM.*/
+ osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0,
+ "State machine broken. ECCEN must be previously disabled.");
+
+ if (NULL != ecc){
+ nandp->nand->PCR |= FSMC_PCR_ECCEN;
+ }
+
+ nand_lld_suspend_thread(nandp);
+ osalSysUnlock();
+
+ /* thread was woken up from DMA ISR */
+ if (NULL != ecc){
+ while (! (nandp->nand->SR & FSMC_SR_FEMPT))
+ ;
+ *ecc = nandp->nand->ECCR;
+ nandp->nand->PCR &= ~FSMC_PCR_ECCEN;
+ }
+}
+
+/**
+ * @brief Write data to NAND.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[in] data buffer with data to be written
+ * @param[in] datalen size of data buffer
+ * @param[in] addr pointer to address buffer
+ * @param[in] addrlen length of address
+ * @param[out] ecc pointer to store computed ECC. Ignored when NULL.
+ *
+ * @return The operation status reported by NAND IC (0x70 command).
+ *
+ * @notapi
+ */
+uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
+ size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){
+
+ nandp->state = NAND_WRITE;
+
+ nand_lld_write_cmd (nandp, NAND_CMD_WRITE);
+ osalSysLock();
+ nand_lld_write_addr(nandp, addr, addrlen);
+
+ /* Now start DMA transfer to NAND buffer and put thread in sleep state.
+ Tread will we woken up from ready ISR. */
+ nandp->state = NAND_DMA_TX;
+ osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0,
+ "State machine broken. ECCEN must be previously disabled.");
+
+ if (NULL != ecc){
+ nandp->nand->PCR |= FSMC_PCR_ECCEN;
+ }
+
+ dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, datalen);
+
+ nand_lld_suspend_thread(nandp);
+ osalSysUnlock();
+
+ if (NULL != ecc){
+ while (! (nandp->nand->SR & FSMC_SR_FEMPT))
+ ;
+ *ecc = nandp->nand->ECCR;
+ nandp->nand->PCR &= ~FSMC_PCR_ECCEN;
+ }
+
+ return nand_lld_read_status(nandp);
+}
+
+/**
+ * @brief Erase block.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[in] addr pointer to address buffer
+ * @param[in] addrlen length of address
+ *
+ * @return The operation status reported by NAND IC (0x70 command).
+ *
+ * @notapi
+ */
+uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen){
+
+ nandp->state = NAND_ERASE;
+
+ nand_lld_write_cmd (nandp, NAND_CMD_ERASE);
+ nand_lld_write_addr(nandp, addr, addrlen);
+ osalSysLock();
+ nand_lld_write_cmd (nandp, NAND_CMD_ERASE_CONFIRM);
+ nand_lld_suspend_thread(nandp);
+ osalSysUnlock();
+
+ return nand_lld_read_status(nandp);
+}
+
+/**
+ * @brief Read data from NAND using polling approach.
+ *
+ * @detatils Use this function to read data when no waiting expected. For
+ * Example read status word after 0x70 command
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[out] data pointer to output buffer
+ * @param[in] len length of data to be read
+ *
+ * @notapi
+ */
+void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len){
+ size_t i = 0;
+
+ for (i=0; i<len; i++)
+ data[i] = nandp->map_data[i];
+}
+
+/**
+ * @brief Send addres to NAND.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[in] len length of address array
+ * @param[in] addr pointer to address array
+ *
+ * @notapi
+ */
+void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len){
+ size_t i = 0;
+
+ for (i=0; i<len; i++)
+ nandp->map_addr[i] = addr[i];
+}
+
+/**
+ * @brief Send command to NAND.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ * @param[in] cmd command value
+ *
+ * @notapi
+ */
+void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd){
+ nandp->map_cmd[0] = cmd;
+}
+
+/**
+ * @brief Read status byte from NAND.
+ *
+ * @param[in] nandp pointer to the @p NANDDriver object
+ *
+ * @return Status byte.
+ *
+ * @notapi
+ */
+uint8_t nand_lld_read_status(NANDDriver *nandp) {
+
+ uint8_t status[1] = {0x01}; /* presume worse */
+
+ nand_lld_write_cmd(nandp, NAND_CMD_STATUS);
+ nand_lld_polled_read_data(nandp, status, 1);
+
+ return status[0];
+}
+
+#endif /* HAL_USE_NAND */
+
+/** @} */
+
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
new file mode 100644
index 0000000..618255f
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
@@ -0,0 +1,335 @@
+/*
+ ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+/*
+ Concepts and parts of this file have been contributed by Uladzimir Pylinsky
+ aka barthess.
+ */
+
+/**
+ * @file nand_lld.h
+ * @brief NAND Driver subsystem low level driver header.
+ *
+ * @addtogroup NAND
+ * @{
+ */
+
+#ifndef _NAND_LLD_H_
+#define _NAND_LLD_H_
+
+#include "fsmc.h"
+
+#if HAL_USE_NAND || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+#define NAND_MIN_PAGE_SIZE 256
+#define NAND_MAX_PAGE_SIZE 8192
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief FSMC1 interrupt priority level setting.
+ */
+#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EMC_FSMC1_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief NAND driver enable switch.
+ * @details If set to @p TRUE the support for NAND1 is included.
+ */
+#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__)
+#define STM32_NAND_USE_NAND1 FALSE
+#endif
+
+/**
+ * @brief NAND driver enable switch.
+ * @details If set to @p TRUE the support for NAND2 is included.
+ */
+#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__)
+#define STM32_NAND_USE_NAND2 FALSE
+#endif
+
+/**
+ * @brief NAND DMA error hook.
+ * @note The default action for DMA errors is a system halt because DMA
+ * error can only happen because programming errors.
+ */
+#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
+#endif
+
+/**
+ * @brief NAND interrupt enable switch.
+ * @details If set to @p TRUE the support for internal FSMC interrupt included.
+ */
+#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__)
+#define STM32_NAND_USE_INT FALSE
+#endif
+
+/**
+* @brief NAND1 DMA priority (0..3|lowest..highest).
+*/
+#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_NAND_NAND1_DMA_PRIORITY 0
+#endif
+
+/**
+* @brief NAND2 DMA priority (0..3|lowest..highest).
+*/
+#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_NAND_NAND2_DMA_PRIORITY 0
+#endif
+
+/**
+ * @brief DMA stream used for NAND operations.
+ * @note This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2
+#error "NAND driver activated but no NAND peripheral assigned"
+#endif
+
+#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
+#error "FSMC not present in the selected device"
+#endif
+
+#if STM32_NAND_USE_EXT_INT && !HAL_USE_EXT
+#error "External interrupt controller must be enabled to use this feature"
+#endif
+
+#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && \
+ !STM32_DMA_IS_VALID_ID(STM32_NAND_DMA_STREAM, \
+ STM32_FSMC_DMA_MSK)
+#error "invalid DMA stream associated to NAND"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief NAND driver condition flags type.
+ */
+typedef uint32_t nandflags_t;
+
+/**
+ * @brief Type of a structure representing an NAND driver.
+ */
+typedef struct NANDDriver NANDDriver;
+
+/**
+ * @brief Type of interrupt handler function
+ */
+typedef void (*nandisrhandler_t)(NANDDriver *nandp);
+
+#if STM32_NAND_USE_EXT_INT
+/**
+ * @brief Type of function switching external interrupts on and off.
+ */
+typedef void (*nandisrswitch_t)(void);
+#endif /* STM32_NAND_USE_EXT_INT */
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Pointer to lower level driver.
+ */
+ FSMCDriver *fsmcp;
+ /**
+ * @brief Number of erase blocks in NAND device.
+ */
+ uint32_t blocks;
+ /**
+ * @brief Number of data bytes in page.
+ */
+ uint32_t page_data_size;
+ /**
+ * @brief Number of spare bytes in page.
+ */
+ uint32_t page_spare_size;
+ /**
+ * @brief Number of pages in block.
+ */
+ uint32_t pages_per_block;
+#if NAND_USE_BAD_MAP
+ /**
+ * @brief Pointer to bad block map.
+ * @details One bit per block. Memory for map must be allocated by user.
+ */
+ uint32_t *bb_map;
+#endif /* NAND_USE_BAD_MAP */
+ /**
+ * @brief Number of write cycles for row addressing.
+ */
+ uint8_t rowcycles;
+ /**
+ * @brief Number of write cycles for column addressing.
+ */
+ uint8_t colcycles;
+
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Number of wait cycles. This value will be used both for
+ * PMEM and PATTR registers
+ *
+ * @note For proper calculation procedure please look at AN2784 document
+ * from STMicroelectronics.
+ */
+ uint32_t pmem;
+#if STM32_NAND_USE_EXT_INT
+ /**
+ * @brief Function enabling interrupts from EXTI
+ */
+ nandisrswitch_t ext_nand_isr_enable;
+ /**
+ * @brief Function disabling interrupts from EXTI
+ */
+ nandisrswitch_t ext_nand_isr_disable;
+#endif /* STM32_NAND_USE_EXT_INT */
+} NANDConfig;
+
+/**
+ * @brief Structure representing an NAND driver.
+ */
+struct NANDDriver {
+ /**
+ * @brief Driver state.
+ */
+ nandstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const NANDConfig *config;
+ /**
+ * @brief Array to store bad block map.
+ */
+#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#elif CH_CFG_USE_SEMAPHORES
+ semaphore_t semaphore;
+#endif
+#endif /* NAND_USE_MUTUAL_EXCLUSION */
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Function enabling interrupts from FSMC
+ */
+ nandisrhandler_t isr_handler;
+ /**
+ * @brief Pointer to current transaction buffer
+ */
+ uint8_t *rxdata;
+ /**
+ * @brief Current transaction length
+ */
+ size_t datalen;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+ /**
+ * @brief DMA channel.
+ */
+ const stm32_dma_stream_t *dma;
+ /**
+ * @brief Thread waiting for I/O completion.
+ */
+ thread_t *thread;
+ /**
+ * @brief Pointer to the FSMC NAND registers block.
+ */
+ FSMC_NAND_TypeDef *nand;
+ /**
+ * @brief Memory mapping for data.
+ */
+ uint8_t *map_data;
+ /**
+ * @brief Memory mapping for commands.
+ */
+ uint8_t *map_cmd;
+ /**
+ * @brief Memory mapping for addresses.
+ */
+ uint8_t *map_addr;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__)
+extern NANDDriver NANDD1;
+#endif
+
+#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__)
+extern NANDDriver NANDD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void nand_lld_init(void);
+ void nand_lld_start(NANDDriver *nandp);
+ void nand_lld_stop(NANDDriver *nandp);
+ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
+ size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
+ void nand_lld_read_data(NANDDriver *nandp, uint8_t *data,
+ size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
+ void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len);
+ uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
+ void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len);
+ void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd);
+ uint8_t nand_lld_read_status(NANDDriver *nandp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_NAND */
+
+#endif /* _NAND_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk
new file mode 100644
index 0000000..0fa3ce0
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F4xx/platform.mk
@@ -0,0 +1,7 @@
+include ${CHIBIOS}/os/hal/ports/STM32/STM32F4xx/platform.mk
+
+PLATFORMSRC += ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
+ ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c \
+ ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram.c
+
+PLATFORMINC += ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1