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-rw-r--r--os/hal/ports/TIVA/TM4C129x/tm4c129x.h400
1 files changed, 323 insertions, 77 deletions
diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
index 18072a4..462a14f 100644
--- a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
+++ b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h
@@ -534,109 +534,251 @@ typedef struct
*/
typedef struct
{
- __I uint32_t PDS; /**< Power Domain Status */
- __IO uint32_t MPC; /**< Memory Power Control */
-} SYSCTL_PDSMPC_t;
-
-typedef struct
-{
- uint32_t WD; /**< Watchdog Timer */
- uint32_t TIMER; /**< General-Purpose Timer */
- uint32_t GPIO; /**< General-Purpose Input/Output */
- uint32_t DMA; /**< Micro Direct Memory Access */
- uint32_t EPI; /**< EPI */
- uint32_t HIB; /**< Hibernation */
- uint32_t UART; /**< Universal Asynchronous
- Receiver/Transmitter */
- uint32_t SSI; /**< Synchronous Serial Interface */
- uint32_t I2C; /**< Inter-Integrated Circuit */
- uint32_t _RESERVED0[1]; /**< Reserved */
- uint32_t USB; /**< Universal Serial Bus */
- uint32_t _RESERVED1[1]; /**< Reserved */
- uint32_t EPHY; /**< Ethernet PHY*/
- uint32_t CAN; /**< Controller Area Network */
- uint32_t ADC; /**< Analog-to-Digital Converter */
- uint32_t ACMP; /**< Analog Comparator */
- uint32_t PWM; /**< Pulse Width Modulator */
- uint32_t QEI; /**< Quadrature Encoder Interface */
- uint32_t LPC; /**< Low Pin Count Interface */
- uint32_t _RESERVED2[1]; /**< Reserved */
- uint32_t PECI; /**< Platform Environment Control Interface */
- uint32_t FAN; /**< Fan Control */
- uint32_t EEPROM; /**< EEPROM */
- uint32_t WTIMER; /**< Wide General-Purpose Timer */
- uint32_t _RESERVED3[4]; /**< Reserved */
- uint32_t RTS; /**< Remote Temperature Sensor */
- uint32_t CCM; /**< CRC Module */
- uint32_t _RESERVED4[6]; /**< Reserved */
- uint32_t LCD; /**< LCD */
- uint32_t _RESERVED5[1]; /**< Reserved */
- uint32_t OWIRE; /**< 1-Wire */
- uint32_t EMAC; /**< Ethernet MAC */
- uint32_t PRB; /**< Power Regulator Bus */
- uint32_t HIM; /**< Human Interface Master */
- uint32_t _RESERVED6[24]; /**< Reserved */
-} SYSCTL_PERIPH_t;
-
-typedef struct
-{
- __I uint32_t DID[2]; /**< Device Identification 0 and 1 */
- __I uint32_t _RESERVED0[12]; /**< Reserved */
- __IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */
- __I uint32_t _RESERVED1[5]; /**< Reserved */
+ __I uint32_t DID0; /**< Device Identification 0 */
+ __I uint32_t DID1; /**< Device Identification 1 */
+ __I uint32_t RESERVED0[12]; /**< Reserved */
+ __IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */
+ __I uint32_t RESERVED1[5]; /**< Reserved */
__I uint32_t RIS; /**< Raw Interrupt Status */
__IO uint32_t IMC; /**< Interrupt Mask Control */
__IO uint32_t MISC; /**< Interrupt Status and Clear */
__IO uint32_t RESC; /**< Reset Cause */
__IO uint32_t PWRTC; /**< Power-Temperature Cause */
__IO uint32_t NMIC; /**< NMI Cause Register */
- __I uint32_t _RESERVED2[5]; /**< Reserved */
+ __I uint32_t RESERVED2[5]; /**< Reserved */
__IO uint32_t MOSCCTL; /**< Main Oscillator Control */
- __I uint32_t _RESERVED3[12]; /**< Reserved */
+ __I uint32_t RESERVED3[12]; /**< Reserved */
__IO uint32_t RSCLKCFG; /**< Run and Sleep Mode Configuration Register */
- __I uint32_t _RESERVED4[3];
+ __I uint32_t RESERVEDx[3];
__IO uint32_t MEMTIM0; /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */
- __I uint32_t _RESERVED5[29]; /**< Reserved */
+ __I uint32_t RESERVED4[29]; /**< Reserved */
__IO uint32_t ALTCLKCFG; /**< Alternate Clock Configuration */
- __I uint32_t _RESERVED6[2]; /**< Reserved */
+ __I uint32_t RESERVED5[2]; /**< Reserved */
__IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */
__IO uint32_t DIVSCLK; /**< Divisor and Source Clock Configuration */
__I uint32_t SYSPROP; /**< System Properties */
__IO uint32_t PIOSCCAL; /**< PIOSC Calibration */
__I uint32_t PIOSCSTAT; /**< PIOSC Statistics */
- __I uint32_t _RESERVED7[2]; /**< Reserved */
- __IO uint32_t PLLFREQ[2]; /**< PLL Frequency 0 and 1 */
+ __I uint32_t RESERVED6[2]; /**< Reserved */
+ __IO uint32_t PLLFREQ0; /**< PLL Frequency 0 */
+ __IO uint32_t PLLFREQ1; /**< PLL Frequency 1 */
__I uint32_t PLLSTAT; /**< PLL Frequency Status */
- __I uint32_t _RESERVED8[7]; /**< Reserved */
+ __I uint32_t RESERVED7[7]; /**< Reserved */
__IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */
__IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */
- __I uint32_t _RESERVED9[4]; /**< Reserved */
+ __I uint32_t RESERVED8[4]; /**< Reserved */
__I uint32_t NVMSTAT; /**< Non-Volatile Memory Information */
- __I uint32_t _RESERVED10[4]; /**< Reserved */
+ __I uint32_t RESERVED9[4]; /**< Reserved */
__IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */
__I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */
__IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */
__I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */
- __I uint32_t _RESERVED11[2]; /**< Reserved */
+ __I uint32_t RESERVED10[2]; /**< Reserved */
__I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */
- __I uint32_t _RESERVED12[2]; /**< Reserved */
+ __I uint32_t RESERVED11[2]; /**< Reserved */
__IO uint32_t RESBEHAVCTL; /**< Reset Behavior Control Register */
- __I uint32_t _RESERVED13[6]; /**< Reserved */
+ __I uint32_t RESERVED12[6]; /**< Reserved */
__IO uint32_t HSSR; /**< Hardware System Service Request */
- __I uint32_t _RESERVED14[34];/**< Reserved */
- SYSCTL_PDSMPC_t USB; /**< USB PDS/MPC */
- SYSCTL_PDSMPC_t EMAC; /**< EMAC PDS/MPC */
- SYSCTL_PDSMPC_t LCD; /**< LCD PDS/MPC */
- SYSCTL_PDSMPC_t CAN[2]; /**< CAN 0 and 1 PDS/MPC */
- __I uint32_t _RESERVED15[22];/**< Reserved */
- __I SYSCTL_PERIPH_t PP; /**< Peripheral Present */
- __I uint32_t _RESERVED16[60];/**< Reserved */
- __IO SYSCTL_PERIPH_t SR; /**< Software Reset */
- __IO SYSCTL_PERIPH_t RCGC; /**< Run Mode Clock Gating Control */
- __IO SYSCTL_PERIPH_t SCGC; /**< Sleep Mode Clock Gating Control */
- __IO SYSCTL_PERIPH_t DCGC; /**< Deep-Sleep Mode Clock Gating Control */
- __IO SYSCTL_PERIPH_t PC; /**< Power Control */
- __IO SYSCTL_PERIPH_t PR; /**< Peripheral Ready */
+ __I uint32_t RESERVED[34]; /**< Reserved */
+ __I uint32_t USBPDS; /**< USB Power Domain Status */
+ __IO uint32_t USBMPC; /**< USB Memory Power Control */
+ __I uint32_t EMACPDS; /**< Ethernet MAC Power Domain Status */
+ __IO uint32_t EMACMPC; /**< Ethernet MAC Memory Power Control */
+ __I uint32_t RESERVED13[2]; /**< Reserved */
+ __I uint32_t CAN0PDS; /**< CAN 0 Power Domain Status */
+ __IO uint32_t CAN0MPC; /**< CAN 0 Memory Power Control */
+ __I uint32_t CAN1PDS; /**< CAN 1 Power Domain Status */
+ __IO uint32_t CAN1MPC; /**< CAN 1 Memory Power Control */
+ __I uint32_t RESERVED14[22]; /**< Reserved */
+ __I uint32_t PPWD; /**< WDT Peripheral Present */
+ __I uint32_t PPTIMER; /**< GPT Peripheral Present */
+ __I uint32_t PPGPIO; /**< GPIO Peripheral Present */
+ __I uint32_t PPDMA; /**< UDMA Peripheral Present */
+ __I uint32_t PPEPI; /**< EPI Peripheral Present */
+ __I uint32_t PPHIB; /**< HIB Peripheral Present */
+ __I uint32_t PPUART; /**< UART Peripheral Present */
+ __I uint32_t PPSSI; /**< SSI Peripheral Present */
+ __I uint32_t PPI2C; /**< I2C Peripheral Present */
+ __I uint32_t RESERVED15[1]; /**< Reserved */
+ __I uint32_t PPUSB; /**< USB Peripheral Present */
+ __I uint32_t RESERVED16[1]; /**< Reserved */
+ __I uint32_t PPEPHY; /**< Ethernet PHY Peripheral Present */
+ __I uint32_t PPCAN; /**< CAN Peripheral Present */
+ __I uint32_t PPADC; /**< ADC Peripheral Present */
+ __I uint32_t PPACMP; /**< ACMP Peripheral Present */
+ __I uint32_t PPPWM; /**< PWM Peripheral Present */
+ __I uint32_t PPQEI; /**< QEI Peripheral Present */
+ __I uint32_t PPLPC; /**< Low Pin Count Interface Peripheral Present */
+ __I uint32_t RESERVED17[1]; /**< Reserved */
+ __I uint32_t PPPECI; /**< Platform Environment Control Interface Peripheral Present */
+ __I uint32_t PPFAN; /**< Fan Control Peripheral Present */
+ __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */
+ __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */
+ __I uint32_t RESERVED18[4]; /**< Reserved */
+ __I uint32_t PPRTS; /**< Remote Temperature Sensor Peripheral Present */
+ __I uint32_t PPCCM; /**< CRC Module Peripheral Present */
+ __I uint32_t RESERVED19[6]; /**< Reserved */
+ __I uint32_t PPLCD; /**< LCD Peripheral Present */
+ __I uint32_t RESERVED20[1]; /**< Reserved */
+ __I uint32_t PPOWIRE; /**< 1-Wire Peripheral Present */
+ __I uint32_t PPEMAC; /**< Ethernet MAC Peripheral Present */
+ __I uint32_t PPPRB; /**< Power Regulator Bus Peripheral Present */
+ __I uint32_t PPHIM; /**< Human Interface Master Peripheral Present */
+ __I uint32_t RESERVED21[86]; /**< Reserved */
+ __IO uint32_t SRWD; /**< WDT Software Reset */
+ __IO uint32_t SRTIMER; /**< GPT Software Reset */
+ __IO uint32_t SRGPIO; /**< GPIO Software Reset */
+ __IO uint32_t SRDMA; /**< UDMA Software Reset */
+ __IO uint32_t SREPI; /**< EPI Software Reset */
+ __IO uint32_t SRHIB; /**< HIB Software Reset */
+ __IO uint32_t SRUART; /**< UART Software Reset */
+ __IO uint32_t SRSSI; /**< SSI Software Reset */
+ __IO uint32_t SRI2C; /**< I2C Software Reset */
+ __I uint32_t RESERVED22[1]; /**< Reserved */
+ __IO uint32_t SRUSB; /**< USB Software Reset */
+ __I uint32_t RESERVED23[1]; /**< Reserved */
+ __IO uint32_t SREPHY; /**< Ethernet PHY Software Reset */
+ __IO uint32_t SRCAN; /**< CAN Software Reset */
+ __IO uint32_t SRADC; /**< ADC Software Reset */
+ __IO uint32_t SRACMP; /**< ACMP Software Reset */
+ __IO uint32_t SRPWM; /**< PWM Software Reset */
+ __IO uint32_t SRQEI; /**< QEI Software Reset */
+ __I uint32_t RESERVED24[4]; /**< Reserved */
+ __IO uint32_t SREEPROM; /**< EEPROM Software Reset */
+ __I uint32_t RESERVED25[6]; /**< Reserved */
+ __IO uint32_t SRCCM; /**< CRC Module Software Reset */
+ __I uint32_t RESERVED26[9]; /**< Reserved */
+ __IO uint32_t SREMAC; /**< Ethernet MAC Software Reset */
+ __I uint32_t RESERVED27[24]; /**< Reserved */
+ __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */
+ __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */
+ __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */
+ __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */
+ __IO uint32_t RCGCEPI; /**< EPI Run Mode Clock Gating Control */
+ __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */
+ __IO uint32_t RCGCUART; /**< UART Run Mode Control */
+ __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */
+ __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */
+ __I uint32_t RESERVED28[1]; /**< Reserved */
+ __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */
+ __I uint32_t RESERVED29[1]; /**< Reserved */
+ __IO uint32_t RCGCEPHY; /**< Ethernet PHY Run Mode Clock Gating Control */
+ __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */
+ __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */
+ __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */
+ __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */
+ __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */
+ __I uint32_t RESERVED30[4]; /**< Reserved */
+ __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */
+ __I uint32_t RESERVED31[6]; /**< Reserved */
+ __IO uint32_t RCGCCCM; /**< CRC Module Run Mode Clock Gating Control */
+ __I uint32_t RESERVED32[9]; /**< Reserved */
+ __IO uint32_t RCGCEMAC; /**< Ethernet MAC Run Mode Clock Gating Control */
+ __I uint32_t RESERVED33[24]; /**< Reserved */
+ __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCEPI; /**< EPI Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED34[1]; /**< Reserved */
+ __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED35[1]; /**< Reserved */
+ __IO uint32_t SCGCEPHY; /**< Ethernet PHY Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED36[4]; /**< Reserved */
+ __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED37[6]; /**< Reserved */
+ __IO uint32_t SCGCCCM; /**< CRC Module Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED38[9]; /**< Reserved */
+ __IO uint32_t SCGCEMAC; /**< Ethernet MAC Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED39[24]; /**< Reserved */
+ __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCEPI; /**< EPI Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/
+ __I uint32_t RESERVED40[1]; /**< Reserved */
+ __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/
+ __I uint32_t RESERVED41[1]; /**< Reserved */
+ __IO uint32_t DCGCEPHY; /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/
+ __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/
+ __I uint32_t RESERVED42[4]; /**< Reserved */
+ __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating
+ Control */
+ __I uint32_t RESERVED43[6]; /**< Reserved */
+ __IO uint32_t DCGCCCM; /**< CRC Module Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED44[9]; /**< Reserved */
+ __IO uint32_t DCGCEMAC; /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED45[24]; /**< Reserved */
+ __IO uint32_t PCWD; /**< Watchdog Timer Power Control */
+ __IO uint32_t PCTIMER; /**< 16/32-Bit General-Purpose Timer Power Control */
+ __IO uint32_t PCGPIO; /**< General-Purpose Input/Output Power Control */
+ __IO uint32_t PCDMA; /**< Micro Direct Memory Access Power Control */
+ __IO uint32_t PCEPI; /**< External Peripheral Interface Power Control */
+ __IO uint32_t PCHIB; /**< Hibernation Power Control */
+ __IO uint32_t PCUART; /**< Universal Asynchronous Receiver/Transmitter Power Control */
+ __IO uint32_t PCSSI; /**< Synchronous Serial Interface Power Control */
+ __IO uint32_t PCI2C; /**< Inter-Integrated Circuit Power Control */
+ __I uint32_t RESERVED46[1]; /**< Reserved */
+ __IO uint32_t PCUSB; /**< Universal Serial Bus Power Control */
+ __I uint32_t RESERVED47[1]; /**< Reserved */
+ __IO uint32_t PCEPHY; /**< Ethernet PHY Power Control */
+ __IO uint32_t PCCAN; /**< Controller Area Network Power Control */
+ __IO uint32_t PCADC; /**< Analog-to-Digital Converter Power Control */
+ __IO uint32_t PCACMP; /**< Analog Comparator Power Control */
+ __IO uint32_t PCPWM; /**< Pulse Width Modulator Power Control */
+ __IO uint32_t PCQEI; /**< Quadrature Encoder Interface Power Control */
+ __I uint32_t RESERVED48[4]; /**< Reserved */
+ __IO uint32_t PCEEPROM; /**< EEPROM Power Control */
+ __I uint32_t RESERVED49[6]; /**< Reserved */
+ __IO uint32_t PCCCM; /**< CRC Module Power Control */
+ __I uint32_t RESERVED50[9]; /**< Reserved */
+ __IO uint32_t PCEMAC; /**< Ethernet MAC Power Control */
+ __I uint32_t RESERVED51[24]; /**< Reserved */
+ __IO uint32_t PRWD; /**< WDT Peripheral Ready */
+ __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */
+ __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */
+ __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */
+ __IO uint32_t PREPI; /**< EPI Peripheral Ready */
+ __IO uint32_t PRHIB; /**< HIB Peripheral Ready */
+ __IO uint32_t PRUART; /**< UART Peripheral Ready */
+ __IO uint32_t PRSSI; /**< SSI Peripheral Ready */
+ __IO uint32_t PRI2C; /**< I2C Peripheral Ready */
+ __I uint32_t RESERVED52[1]; /**< Reserved */
+ __IO uint32_t PRUSB; /**< USB Peripheral Ready */
+ __I uint32_t RESERVED53[1]; /**< Reserved */
+ __IO uint32_t PREPHY; /**< Ethernet PHY Peripheral Ready */
+ __IO uint32_t PRCAN; /**< CAN Peripheral Ready */
+ __IO uint32_t PRADC; /**< ADC Peripheral Ready */
+ __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */
+ __IO uint32_t PRPWM; /**< PWM Peripheral Ready */
+ __IO uint32_t PRQEI; /**< QEI Peripheral Ready */
+ __I uint32_t RESERVED54[4]; /**< Reserved */
+ __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */
+ __I uint32_t RESERVED55[6]; /**< Reserved */
+ __IO uint32_t PRCCM; /**< CRC Module Peripheral Ready */
+ __I uint32_t RESERVED56[9]; /**< Reserved */
+ __IO uint32_t PREMAC; /**< Ethernet MAC Peripheral Ready */
} SYSCTL_TypeDef;
/**
@@ -723,6 +865,106 @@ typedef struct
} WATCHDOG_TypeDef;
/**
+ * @brief Ethernet peripheral
+ */
+typedef struct {
+ __IO uint32_t CFG; /**< Configuration */
+ __IO uint32_t FRAMEFLTR; /**< Frame Filter */
+ __IO uint32_t HASHTBLH; /**< Hash Table High */
+ __IO uint32_t HASHTBLL; /**< Hash Table Low */
+ __IO uint32_t MIIADDR; /**< MII Address */
+ __IO uint32_t MIIDATA; /**< MII Data Register */
+ __IO uint32_t FLOWCTL; /**< Flow Control */
+ __IO uint32_t VLANTG; /**< VLAN Tag */
+ __I uint32_t RESERVED0[1]; /**< Reserved */
+ __IO uint32_t STATUS; /**< Status */
+ __IO uint32_t RWUFF; /**< Remote Wake-Up Frame Filter */
+ __IO uint32_t PMTCTLSTAT; /**< PMT Control and Status Register */
+ __I uint32_t RESERVED1[2]; /**< Reserved */
+ __IO uint32_t RIS; /**< Raw Interrupt Status */
+ __IO uint32_t IM; /**< Interrupt Mask */
+ __IO uint32_t ADDR0H; /**< Address 0 High */
+ __IO uint32_t ADDR0L; /**< Address 0 Low Register */
+ __IO uint32_t ADDR1H; /**< Address 1 High */
+ __IO uint32_t ADDR1L; /**< Address 1 Low */
+ __IO uint32_t ADDR2H; /**< Address 2 High */
+ __IO uint32_t ADDR2L; /**< Address 2 Low */
+ __IO uint32_t ADDR3H; /**< Address 3 High */
+ __IO uint32_t ADDR3L; /**< Address 3 Low */
+ __I uint32_t RESERVED2[31]; /**< Reserved */
+ __IO uint32_t WDOGTO; /**< Watchdog Timeout */
+ __I uint32_t RESERVED3[8]; /**< Reserved */
+ __IO uint32_t MMCCTRL; /**< MMC Control */
+ __IO uint32_t MMCRXRIS; /**< MMC Receive Raw Interrupt Status */
+ __IO uint32_t MMCTXRIS; /**< MMC Transmit Raw Interrupt Status */
+ __IO uint32_t MMCRXIM; /**< MMC Receive Interrupt Mask */
+ __IO uint32_t MMCTXIM; /**< MMC Transmit Interrupt Mask */
+ __I uint32_t RESERVED4[1]; /**< Reserved */
+ __IO uint32_t TXCNTGB; /**< Transmit Frame Count for Good and Bad
+ Frames */
+ __I uint32_t RESERVED5[12]; /**< Reserved */
+ __IO uint32_t TXCNTSCOL; /**< Transmit Frame Count for Frames
+ Transmitted after Single Collision */
+ __IO uint32_t TXCNTMCOL; /**< Transmit Frame Count for Frames
+ Transmitted after Multiple Collisions */
+ __I uint32_t RESERVED6[4]; /**< Reserved */
+ __IO uint32_t TXOCTCNTG; /**< Transmit Octet Count Good */
+ __I uint32_t RESERVED7[6]; /**< Reserved */
+ __IO uint32_t RXCNTGB; /**< Receive Frame Count for Good and Bad
+ Frames */
+ __I uint32_t RESERVED8[4]; /**< Reserved */
+ __IO uint32_t RXCNTCRCERR; /**< Receive Frame Count for CRC Error Frames*/
+ __IO uint32_t RXCNTALGNERR; /**< Receive Frame Count for Alignment Error
+ Frames */
+ __I uint32_t RESERVED9[10]; /**< Reserved */
+ __IO uint32_t RXCNTGUNI; /**< Receive Frame Count for Good Unicast
+ Frames */
+ __I uint32_t RESERVED10[239];/**< Reserved */
+ __IO uint32_t VLNINCREP; /**< VLAN Tag Inclusion or Replacement */
+ __IO uint32_t VLANHASH; /**< VLAN Hash Table */
+ __I uint32_t RESERVED11[93]; /**< Reserved */
+ __IO uint32_t TIMSTCTRL; /**< Timestamp Control */
+ __IO uint32_t SUBSECINC; /**< Sub-Second Increment */
+ __IO uint32_t TIMSEC; /**< System Time - Seconds */
+ __IO uint32_t TIMNANO; /**< System Time - Nanoseconds */
+ __IO uint32_t TIMSECU; /**< System Time - Seconds Update */
+ __IO uint32_t TIMNANOU; /**< System Time - Nanoseconds Update */
+ __IO uint32_t TIMADD; /**< Timestamp Addend */
+ __IO uint32_t TARGSEC; /**< Target Time Seconds */
+ __IO uint32_t TARGNANO; /**< Target Time Nanoseconds */
+ __IO uint32_t HWORDSEC; /**< System Time-Higher Word Seconds */
+ __IO uint32_t TIMSTAT; /**< Timestamp Status */
+ __IO uint32_t PPSCTRL; /**< PPS Control */
+ __I uint32_t RESERVED12[12]; /**< Reserved */
+ __IO uint32_t PPS0INTVL; /**< PPS0 Interval */
+ __IO uint32_t PPS0WIDTH; /**< PPS0 Width */
+ __I uint32_t RESERVED13[294];/**< Reserved */
+ __IO uint32_t DMABUSMOD; /**< DMA Bus Mode */
+ __O uint32_t TXPOLLD; /**< Transmit Poll Demand */
+ __O uint32_t RXPOLLD; /**< Receive Poll Demand */
+ __IO uint32_t RXDLADDR; /**< Receive Descriptor List Address */
+ __IO uint32_t TXDLADDR; /**< Transmit Descriptor List Address */
+ __IO uint32_t DMARIS; /**< DMA Interrupt Status */
+ __IO uint32_t DMAOPMODE; /**< DMA Operation Mode */
+ __IO uint32_t DMAIM; /**< DMA Interrupt Mask Register */
+ __IO uint32_t MFBOC; /**< Missed Frame and Buffer Overflow Counter*/
+ __IO uint32_t RXINTWDT; /**< Receive Interrupt Watchdog Timer */
+ __I uint32_t RESERVED14[8]; /**< Reserved */
+ __IO uint32_t HOSTXDESC; /**< Current Host Transmit Descriptor */
+ __IO uint32_t HOSRXDESC; /**< Current Host Receive Descriptor */
+ __IO uint32_t HOSTXBA; /**< Current Host Transmit Buffer Address */
+ __IO uint32_t HOSRXBA; /**< Current Host Receive Buffer Address */
+ __I uint32_t RESERVED15[218];/**< Reserved */
+ __IO uint32_t PP; /**< Peripheral Property Register */
+ __IO uint32_t PC; /**< Peripheral Configuration Register */
+ __IO uint32_t CC; /**< Clock Configuration Register */
+ __I uint32_t RESERVED16[1]; /**< Reserved */
+ __I uint32_t PHYRIS; /**< PHY Raw Interrupt Status */
+ __IO uint32_t PHYIM; /**< PHY Interrupt Mask */
+ __IO uint32_t PHYMISC; /**< PHY Masked Interrupt Status and Clear */
+} ETH_TypeDef;
+
+/**
* @}
*/
@@ -796,6 +1038,8 @@ typedef struct
#define QEI0_BASE 0x4002C000
#define QEI1_BASE 0x4002D000
+#define ETH_BASE 0x400EC000
+
/**
* @}
*/
@@ -868,6 +1112,8 @@ typedef struct
#define QEI0 ((QEI_TypeDef *) QEI0_BASE)
#define QEI1 ((QEI_TypeDef *) QEI1_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+
/**
* @}
*/