diff options
Diffstat (limited to 'os')
-rw-r--r-- | os/hal/ports/TIVA/LLD/mac_lld.c | 823 | ||||
-rw-r--r-- | os/hal/ports/TIVA/LLD/mac_lld.h | 434 | ||||
-rw-r--r-- | os/hal/ports/TIVA/TM4C129x/platform.mk | 3 |
3 files changed, 1259 insertions, 1 deletions
diff --git a/os/hal/ports/TIVA/LLD/mac_lld.c b/os/hal/ports/TIVA/LLD/mac_lld.c new file mode 100644 index 0000000..226695e --- /dev/null +++ b/os/hal/ports/TIVA/LLD/mac_lld.c @@ -0,0 +1,823 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/mac_lld.c + * @brief MAC Driver subsystem low level driver source. + * + * @addtogroup MAC + * @{ + */ + +#include <string.h> + +#include "hal.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +#include "mii.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) + +/* MII divider optimal value.*/ +#if (TIVA_SYSCLK >= 100000000) +#define MACMIIADDR_CR (0x01 << 2) +#elif (TIVA_SYSCLK >= 60000000) +#define MACMIIADDR_CR (0x00 << 2) +#elif (TIVA_SYSCLK >= 35000000) +#define MACMIIADDR_CR (0x03 << 2) +#elif (TIVA_SYSCLK >= 20000000) +#define MACMIIADDR_CR (0x02 << 2) +#else +#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)" +#endif + +#define EMAC_MIIADDR_MIIW 0x00000002 /* MII Write */ +#define EMAC_MIIADDR_MIIB 0x00000001 /* MII Busy */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, + 0x37, 0x01, 0x10}; + +static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS]; +static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS]; + +static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; +static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Writes a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * @param[in] value new register value + * + * @notapi + */ +static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) +{ + ETH->MIIDATA = value; + ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; + + while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + ; +} + +/** + * @brief Writes an extended PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * @param[in] value new register value + * + * @notapi + */ +static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) +{ + mii_write(macp, TIVA_REGCTL, 0x001F); + mii_write(macp, TIVA_ADDAR, reg); + + mii_write(macp, TIVA_REGCTL, 0x401F); + mii_write(macp, TIVA_ADDAR, value); +} + +/** + * @brief Reads a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * + * @return The PHY register content. + * + * @notapi + */ +static uint32_t mii_read(MACDriver *macp, uint32_t reg) +{ + ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; + + while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + ; + + return ETH->MIIDATA; +} + +/** + * @brief Reads an extended PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * + * @return The extended PHY register content. + * + * @notapi + */ +static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg) +{ + mii_write(macp, TIVA_REGCTL, 0x001F); + mii_write(macp, TIVA_ADDAR, reg); + + mii_write(macp, TIVA_REGCTL, 0x401F); + return mii_read(macp, TIVA_ADDAR); +} + +#if !defined(BOARD_PHY_ADDRESS) +/** + * @brief PHY address detection. + * + * @param[in] macp pointer to the @p MACDriver object + */ +static void mii_find_phy(MACDriver *macp) +{ + uint32_t i; + +#if TIVA_MAC_PHY_TIMEOUT > 0 + rtcnt_t start = chSysGetRealtimeCounterX(); + rtcnt_t timeout = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT); + rtcnt_t time = start; + while (chSysIsCounterWithinX(time, start, timeout)) { +#endif + for (i = 0; i < 31; i++) { + macp->phyaddr = i << 11; + ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; + if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && + ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { + return; + } + } +#if TIVA_MAC_PHY_TIMEOUT > 0 + time = chSysGetRealtimeCounterX(); + } +#endif + /* Wrong or defective board.*/ + osalSysHalt("MAC failure"); +} +#endif + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void mac_lld_set_address(const uint8_t *p) +{ + /* MAC address configuration, only a single address comparator is used, + hash table not used.*/ + ETH->ADDR0H = ((uint32_t)p[5] << 8) | + ((uint32_t)p[4] << 0); + ETH->ADDR0L = ((uint32_t)p[3] << 24) | + ((uint32_t)p[2] << 16) | + ((uint32_t)p[1] << 8) | + ((uint32_t)p[0] << 0); + ETH->ADDR1H = 0x0000FFFF; + ETH->ADDR1L = 0xFFFFFFFF; + ETH->ADDR2H = 0x0000FFFF; + ETH->ADDR2L = 0xFFFFFFFF; + ETH->ADDR3H = 0x0000FFFF; + ETH->ADDR3L = 0xFFFFFFFF; + ETH->HASHTBLH = 0; + ETH->HASHTBLL = 0; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +CH_IRQ_HANDLER(TIVA_MAC_HANDLER) +{ + uint32_t dmaris; + + CH_IRQ_PROLOGUE(); + + dmaris = ETH->DMARIS; + ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ + + if (dmaris & (1 << 6)) { + /* Data Received.*/ + osalSysLockFromISR(); + osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET); +#if MAC_USE_EVENTS + osalEventBroadcastFlagsI(ÐD1.rdevent, 0); +#endif + osalSysUnlockFromISR(); + } + + if (dmaris & (1 << 0)) { + /* Data Transmitted.*/ + osalSysLockFromISR(); + osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET); + osalSysUnlockFromISR(); + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) +{ + uint8_t i; + + macObjectInit(ÐD1); + ETHD1.link_up = false; + + /* Descriptor tables are initialized in chained mode, note that the first + word is not initialized here but in mac_lld_start().*/ + for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { + rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE); + rd[i].rdes2 = (uint32_t)rb[i]; + rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS]; + } + for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { + td[i].tdes1 = 0; + td[i].tdes2 = (uint32_t)tb[i]; + td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS]; + } + + /* Enable MAC clock */ + SYSCTL->RCGCEMAC = 1; + while (SYSCTL->PREMAC != 0x01) + ; + + /* Set PHYHOLD bit */ + ETH->PC |= 1; + + /* Enable PHY clock */ + SYSCTL->RCGCEPHY = 1; + while (SYSCTL->PREPHY != 0x01) + ; + + /* Enable power to PHY */ + SYSCTL->PCEPHY |= 1; + while (SYSCTL->PREPHY != 0x01) + ; +#if BOARD_PHY_RMII + ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); +#else + ETH->PC = EMAC_PHY_CONFIG; +#endif + + /* + * Write OHY led configuration. + * 0: link ok + * 1: tx activity + * 2: link ok + * blink rate: 20Hz + */ + mii_write_extended(ÐD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0)); + mii_write(ÐD1, TIVA_LEDCR, (0 << 9)); + + /* Set done bit after writing EMACPC register */ + mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); + + while(ETH->DMABUSMOD & 1) + ; + + /* Reset MAC */ + ETH->DMABUSMOD |= 1; + while (ETH->DMABUSMOD & 1) + ; + + /* PHY address setup.*/ +#if defined(BOARD_PHY_ADDRESS) + ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; +#else + mii_find_phy(ÐD1); +#endif + +#if defined(BOARD_PHY_RESET) + /* PHY board-specific reset procedure.*/ + BOARD_PHY_RESET(); +#else + /* PHY soft reset procedure.*/ + mii_write(ÐD1, MII_BMCR, BMCR_RESET); +#if defined(BOARD_PHY_RESET_DELAY) + chSysPolledDelayX(BOARD_PHY_RESET_DELAY); +#endif + while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) + ; +#endif + +#if TIVA_MAC_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be started.*/ + mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); +#endif + + /* Disable MAC clock */ + SYSCTL->RCGCEMAC = 0; + + /* Disable PHY clock */ + SYSCTL->RCGCEPHY = 0; +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) +{ + uint8_t i; + + /* Resets the state of all descriptors.*/ + for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { + rd[i].rdes0 = TIVA_RDES0_OWN; + } + macp->rxptr = (tiva_eth_rx_descriptor_t *)rd; + + for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { + td[i].tdes0 = TIVA_TDES0_TCH; + td[i].locked = 0; + } + macp->txptr = (tiva_eth_tx_descriptor_t *)td; + + /* Enable MAC clock */ + SYSCTL->RCGCEMAC = 1; + while (SYSCTL->PREMAC != 0x01) + ; + + /* Enable PHY clock */ + SYSCTL->RCGCEPHY = 1; + while (!SYSCTL->PREPHY) + ; + + /* ISR vector enabled.*/ + nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY); + +#if TIVA_MAC_CHANGE_PHY_STATE + /* PHY in power up mode.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); +#endif + + /* MAC configuration.*/ + ETH->FRAMEFLTR = 0; + ETH->FLOWCTL = 0; + ETH->VLANTG = 0; + + /* MAC address setup.*/ + if (macp->config->mac_address == NULL) + mac_lld_set_address(default_mac_address); + else + mac_lld_set_address(macp->config->mac_address); + + /* Transmitter and receiver enabled. + Note that the complete setup of the MAC is performed when the link + status is detected.*/ +#if TIVA_MAC_IP_CHECKSUM_OFFLOAD + ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); +#else + ETH->CFG = (1 << 3) | (1 << 2); +#endif + + /* DMA configuration: + Descriptor chains pointers.*/ + ETH->RXDLADDR = (uint32_t)rd; + ETH->TXDLADDR = (uint32_t)td; + + /* Enabling required interrupt sources.*/ + ETH->DMARIS &= 0xFFFF; + ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); + + /* DMA general settings.*/ + ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); + + /* Transmit FIFO flush.*/ + ETH->DMAOPMODE = (1 << 20); + while (ETH->DMAOPMODE & (1 << 20)) + ; + + /* DMA final configuration and start.*/ + ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | + (1 << 13) | (1 << 1); +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) +{ + if (macp->state != MAC_STOP) { +#if TIVA_MAC_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be restarted.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); +#endif + + /* MAC and DMA stopped.*/ + ETH->CFG = 0; + ETH->DMAOPMODE = 0; + ETH->DMAIM = 0; + ETH->DMARIS &= 0xFFFF; + + /* MAC clocks stopped.*/ + SYSCTL->RCGCEMAC = 0; + + /* PHY clock stopped.*/ + SYSCTL->RCGCEPHY = 0; + + /* ISR vector disabled.*/ + nvicDisableVector(TIVA_MAC_NUMBER); + } +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) +{ + tiva_eth_tx_descriptor_t *tdes; + + if (!macp->link_up) + return MSG_TIMEOUT; + + osalSysLock(); + + /* Get Current TX descriptor.*/ + tdes = macp->txptr; + + /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by + another thread.*/ + if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) { + osalSysUnlock(); + return MSG_TIMEOUT; + } + + /* Marks the current descriptor as locked.*/ + tdes->locked = 1; + + /* Next TX descriptor to use.*/ + macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3; + + osalSysUnlock(); + + /* Set the buffer size and configuration.*/ + tdp->offset = 0; + tdp->size = TIVA_MAC_BUFFERS_SIZE; + tdp->physdesc = tdes; + + return MSG_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) +{ + osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), + "attempt to release descriptor already owned by DMA"); + + osalSysLock(); + + /* Unlocks the descriptor and returns it to the DMA engine.*/ + tdp->physdesc->tdes1 = tdp->offset; + tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) | + TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS | + TIVA_TDES0_TCH | TIVA_TDES0_OWN; + tdp->physdesc->locked = 0; + + /* If the DMA engine is stalled then a restart request is issued.*/ + if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { + ETH->DMARIS = (1 << 2); + ETH->TXPOLLD = 1; /* Any value is OK.*/ + } + + osalSysUnlock(); +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) +{ + tiva_eth_rx_descriptor_t *rdes; + + osalSysLock(); + + /* Get Current RX descriptor.*/ + rdes = macp->rxptr; + + /* Iterates through received frames until a valid one is found, invalid + frames are discarded.*/ + while (!(rdes->rdes0 & TIVA_RDES0_OWN)) { + if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES)) +#if TIVA_MAC_IP_CHECKSUM_OFFLOAD + && (rdes->rdes0 & TIVA_RDES0_FT) + && !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE)) +#endif + && (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) { + /* Found a valid one.*/ + rdp->offset = 0; + rdp->size = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4; + rdp->physdesc = rdes; + macp->rxptr = (tiva_eth_rx_descriptor_t *)rdes->rdes3; + + osalSysUnlock(); + return MSG_OK; + } + /* Invalid frame found, purging.*/ + rdes->rdes0 = TIVA_RDES0_OWN; + rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3; + } + + /* Next descriptor to check.*/ + macp->rxptr = rdes; + + osalSysUnlock(); + return MSG_TIMEOUT; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) +{ + osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), + "attempt to release descriptor already owned by DMA"); + + osalSysLock(); + + /* Give buffer back to the Ethernet DMA.*/ + rdp->physdesc->rdes0 = TIVA_RDES0_OWN; + + /* If the DMA engine is stalled then a restart request is issued.*/ + if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { + ETH->DMARIS = (1 << 7); + ETH->TXPOLLD = 1; /* Any value is OK.*/ + } + + osalSysUnlock(); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool mac_lld_poll_link_status(MACDriver *macp) +{ + uint32_t maccfg, bmsr, bmcr; + + maccfg = ETH->CFG; + + /* PHY CR and SR registers read.*/ + (void)mii_read(macp, MII_BMSR); + bmsr = mii_read(macp, MII_BMSR); + bmcr = mii_read(macp, MII_BMCR); + + /* Check on auto-negotiation mode.*/ + if (bmcr & BMCR_ANENABLE) { + uint32_t lpa; + + /* Auto-negotiation must be finished without faults and link established.*/ + if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != + (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) + return macp->link_up = false; + + /* Auto-negotiation enabled, checks the LPA register.*/ + lpa = mii_read(macp, MII_LPA); + + /* Check on link speed.*/ + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + maccfg |= (1 << 14); + else + maccfg &= ~(1 << 14); + + /* Check on link mode.*/ + if (lpa & (LPA_10FULL | LPA_100FULL)) + maccfg |= (1 << 11); + else + maccfg &= ~(1 << 11); + } + else { + /* Link must be established.*/ + if (!(bmsr & BMSR_LSTATUS)) + return macp->link_up = false; + + /* Check on link speed.*/ + if (bmcr & BMCR_SPEED100) + maccfg |= (1 << 14); + else + maccfg &= ~(1 << 14); + + /* Check on link mode.*/ + if (bmcr & BMCR_FULLDPLX) + maccfg |= (1 << 11); + else + maccfg &= ~(1 << 11); + } + + /* Changes the mode in the MAC.*/ + ETH->CFG = maccfg; + + /* Returns the link status.*/ + return macp->link_up = true; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) +{ + osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), + "attempt to write descriptor already owned by DMA"); + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + + if (size > 0) { + memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); + tdp->offset += size; + } + return size; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) +{ + osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), + "attempt to read descriptor already owned by DMA"); + + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + + if (size > 0) { + memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); + rdp->offset += size; + } + return size; +} + +#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the next transmit buffer in the descriptor + * chain. + * @note The API guarantees that enough buffers can be requested to fill + * a whole frame. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] size size of the requested buffer. Specify the frame size + * on the first call then scale the value down subtracting + * the amount of data already copied into the previous + * buffers. + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * Note that a returned size lower than the amount + * requested means that more buffers must be requested + * in order to fill the frame data entirely. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep) +{ + if (tdp->offset == 0) { + *sizep = tdp->size; + tdp->offset = size; + return (uint8_t *)tdp->physdesc->tdes2; + } + *sizep = 0; + return NULL; +} + +/** + * @brief Returns a pointer to the next receive buffer in the descriptor + * chain. + * @note The API guarantees that the descriptor chain contains a whole + * frame. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep) +{ + if (rdp->size > 0) { + *sizep = rdp->size; + rdp->offset = rdp->size; + rdp->size = 0; + return (uint8_t *)rdp->physdesc->rdes2; + } + *sizep = 0; + return NULL; +} +#endif /* MAC_USE_ZERO_COPY */ + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/mac_lld.h b/os/hal/ports/TIVA/LLD/mac_lld.h new file mode 100644 index 0000000..7c86dbd --- /dev/null +++ b/os/hal/ports/TIVA/LLD/mac_lld.h @@ -0,0 +1,434 @@ +/* + Copyright (C) 2014 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/mac_lld.h + * @brief MAC Driver subsystem low level driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef _MAC_LLD_H_ +#define _MAC_LLD_H_ + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY TRUE + +/** + * @name RDES0 constants + * @{ + */ +#define TIVA_RDES0_OWN 0x80000000 +#define TIVA_RDES0_AFM 0x40000000 + +#define TIVA_RDES0_FL_MASK 0x3FFF0000 +#define TIVA_RDES0_FL(n) ((n) << 16) + +#define TIVA_RDES0_ES 0x00008000 +#define TIVA_RDES0_DESERR 0x00004000 +#define TIVA_RDES0_SAF 0x00002000 +#define TIVA_RDES0_LE 0x00001000 +#define TIVA_RDES0_OE 0x00000800 +#define TIVA_RDES0_VLAN 0x00000400 +#define TIVA_RDES0_FS 0x00000200 +#define TIVA_RDES0_LS 0x00000100 +#define TIVA_RDES0_TAGF 0x00000080 +#define TIVA_RDES0_LC 0x00000040 +#define TIVA_RDES0_FT 0x00000020 +#define TIVA_RDES0_RWT 0x00000010 +#define TIVA_RDES0_RE 0x00000008 +#define TIVA_RDES0_DE 0x00000004 +#define TIVA_RDES0_CE 0x00000002 +#define TIVA_RDES0_ESA 0x00000001 +/** @} */ + +/** + * @name RDES1 constants + * @{ + */ +#define TIVA_RDES1_DIC 0x80000000 + +#define TIVA_RDES1_RBS2_MASK 0x1FFF0000 +#define TIVA_RDES1_RBS2(n) ((n) << 16) + +#define TIVA_RDES1_RER 0x00008000 +#define TIVA_RDES1_RCH 0x00004000 + +#define TIVA_RDES1_RBS1_MASK 0x00001FFF +#define TIVA_RDES1_RBS1(n) ((n) << 0) + +/** @} */ + +/** + * @name TDES0 constants + * @{ + */ +#define TIVA_TDES0_OWN 0x80000000 +#define TIVA_TDES0_IC 0x40000000 +#define TIVA_TDES0_LS 0x20000000 +#define TIVA_TDES0_FS 0x10000000 +#define TIVA_TDES0_DC 0x08000000 +#define TIVA_TDES0_DP 0x04000000 +#define TIVA_TDES0_TTSE 0x02000000 +#define TIVA_TDES0_CRCR 0x01000000 + +#define TIVA_TDES0_CIC_MASK 0x00C00000 +#define TIVA_TDES0_CIC(n) ((n) << 22) + +#define TIVA_TDES0_TER 0x00200000 +#define TIVA_TDES0_TCH 0x00100000 +#define TIVA_TDES0_VLIC 0x000C0000 +#define TIVA_TDES0_TTSS 0x00020000 +#define TIVA_TDES0_IHE 0x00010000 +#define TIVA_TDES0_ES 0x00008000 +#define TIVA_TDES0_JT 0x00004000 +#define TIVA_TDES0_FF 0x00002000 +#define TIVA_TDES0_IPE 0x00001000 +#define TIVA_TDES0_LC 0x00000800 +#define TIVA_TDES0_NC 0x00000400 +#define TIVA_TDES0_LCO 0x00000200 +#define TIVA_TDES0_EC 0x00000100 +#define TIVA_TDES0_VF 0x00000080 + +#define TIVA_TDES0_CC_MASK 0x00000078 +#define TIVA_TDES0_CC(n) ((n) << 3) + +#define TIVA_TDES0_ED 0x00000004 +#define TIVA_TDES0_UF 0x00000002 +#define TIVA_TDES0_DB 0x00000001 +/** @} */ + +/** + * @name TDES1 constants + * @{ + */ +#define TIVA_TDES1_SAIC_MASK 0xE0000000 +#define TIVA_TDES1_SAIC(n) ((n) << 29) + +#define TIVA_TDES1_TBS2_MASK 0x1FFF0000 +#define TIVA_TDES1_TBS2(n) ((n) << 16) + +#define TIVA_TDES1_TBS1_MASK 0x00001FFF +#define TIVA_TDES1_TBS1(n) ((n) << 0) +/** @} */ + + + + +/** + * @name Ethernet PHY registers + */ +#define TIVA_BMCR 0x00000000 /* MR0 - Basic Mode Control */ +#define TIVA_BMSR 0x00000001 /* MR1 - Basic Mode Status */ +#define TIVA_ID1 0x00000002 /* MR2 - Identifier Register 1 */ +#define TIVA_ID2 0x00000003 /* MR3 - Identifier Register 2 */ +#define TIVA_ANA 0x00000004 /* MR4 - Auto-Negotiation Advertisement */ +#define TIVA_ANLPA 0x00000005 /* MR5 - Auto-Negotiation Link Partner Ability */ +#define TIVA_ANER 0x00000006 /* MR6 - Auto-Negotiation Expansion */ +#define TIVA_ANNPTR 0x00000007 /* MR7 - Auto-Negotiation Next Page TX */ +#define TIVA_ANLNPTR 0x00000008 /* MR8 - Auto-Negotiation Link Partner Ability Next Page */ +#define TIVA_CFG1 0x00000009 /* MR9 - Configuration 1 */ +#define TIVA_CFG2 0x0000000A /* MR10 - Configuration 2 */ +#define TIVA_CFG3 0x0000000B /* MR11 - Configuration 3 */ +#define TIVA_REGCTL 0x0000000D /* MR13 - Register Control */ +#define TIVA_ADDAR 0x0000000E /* MR14 - Address or Data */ +#define TIVA_STS 0x00000010 /* MR16 - Status */ +#define TIVA_SCR 0x00000011 /* MR17 - Specific Control */ +#define TIVA_MISR1 0x00000012 /* MR18 - MII Interrupt Status 1 */ +#define TIVA_MISR2 0x00000013 /* MR19 - MII Interrupt Status 2 */ +#define TIVA_FCSCR 0x00000014 /* MR20 - False Carrier Sense Counter */ +#define TIVA_RXERCNT 0x00000015 /* MR21 - Receive Error Count */ +#define TIVA_BISTCR 0x00000016 /* MR22 - BIST Control */ +#define TIVA_LEDCR 0x00000018 /* MR24 - LED Control */ +#define TIVA_CTL 0x00000019 /* MR25 - Control */ +#define TIVA_10BTSC 0x0000001A /* MR26 - 10Base-T Status/Control - MR26 */ +#define TIVA_BICSR1 0x0000001B /* MR27 - BIST Control and Status 1 */ +#define TIVA_BICSR2 0x0000001C /* MR28 - BIST Control and Status 2 */ +#define TIVA_CDCR 0x0000001E /* MR30 - Cable Diagnostic Control */ +#define TIVA_RCR 0x0000001F /* MR31 - Reset Control */ +#define TIVA_LEDCFG 0x00000025 /* MR37 - LED Configuration */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Number of available transmit buffers. + */ +#if !defined(TIVA_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define TIVA_MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(TIVA_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define TIVA_MAC_RECEIVE_BUFFERS 4 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(TIVA_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define TIVA_MAC_BUFFERS_SIZE 1522 +#endif + +/** + * @brief PHY detection timeout. + * @details Timeout, in milliseconds, for PHY address detection, if a PHY + * is not detected within the timeout then the driver halts during + * initialization. This setting applies only if the PHY address is + * not explicitly set in the board header file using + * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a + * single search path is performed. + */ +#if !defined(TIVA_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) +#define TIVA_MAC_PHY_TIMEOUT 0 +#endif + +/** + * @brief Change the PHY power state inside the driver. + */ +#if !defined(TIVA_MAC_CHANGE_PHY_STATE) || defined(__DOXYGEN__) +#define TIVA_MAC_CHANGE_PHY_STATE TRUE +#endif + +/** + * @brief ETHD1 interrupt priority level setting. + */ +#if !defined(TIVA_MAC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_MAC_IRQ_PRIORITY 5 +#endif + +/** + * @brief IP checksum offload. + * @details The following modes are available: + * - 0 Function disabled. + * - 1 Only IP header checksum calculation and insertion are enabled. + * - 2 IP header checksum and payload checksum calculation and + * insertion are enabled, but pseudo-header checksum is not + * calculated in hardware. + * - 3 IP Header checksum and payload checksum calculation and + * insertion are enabled, and pseudo-header checksum is + * calculated in hardware. + * . + */ +#if !defined(TIVA_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) +#define TIVA_MAC_IP_CHECKSUM_OFFLOAD 0 +#endif +/** @} */ + +#ifndef EMAC_PHY_CONFIG +#define EMAC_PHY_CONFIG ((0 << 31) | \ + (1 << 23) | \ + (1 << 10) | \ + (1 << 3) | \ + (3 << 1) | \ + (1 << 0)) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (TIVA_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS +#error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an Tiva Ethernet receive descriptor. + */ +typedef struct +{ + volatile uint32_t rdes0; + volatile uint32_t rdes1; + volatile uint32_t rdes2; + volatile uint32_t rdes3; +} tiva_eth_rx_descriptor_t; + +/** + * @brief Type of an Tiva Ethernet transmit descriptor. + */ +typedef struct +{ + volatile uint32_t tdes0; + volatile uint32_t tdes1; + volatile uint32_t tdes2; + volatile uint32_t tdes3; + volatile uint32_t locked; +} tiva_eth_tx_descriptor_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct +{ + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver +{ + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + threads_queue_t tdqueue; + /** + * @brief Receive semaphore. + */ + threads_queue_t rdqueue; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + event_source_t rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool link_up; + /** + * @brief PHY address (pre shifted). + */ + uint32_t phyaddr; + /** + * @brief Receive next frame pointer. + */ + tiva_eth_rx_descriptor_t *rxptr; + /** + * @brief Transmit next frame pointer. + */ + tiva_eth_tx_descriptor_t *txptr; +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct +{ + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + tiva_eth_tx_descriptor_t *physdesc; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct +{ + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + tiva_eth_rx_descriptor_t *physdesc; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern MACDriver ETHD1; + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool mac_lld_poll_link_status(MACDriver *macp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); +#if MAC_USE_ZERO_COPY + uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); + const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif /* MAC_USE_ZERO_COPY */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* _MAC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index 83331e0..35de5ce 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -3,7 +3,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/st_lld.c \ ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/pal_lld.c \ - ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c + ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/serial_lld.c \ + ${CHIBIOS}/community/os/hal/ports/TIVA/LLD/mac_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ |