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* Merge branch 'master' into update_testsFabien Poussin2018-03-152-1/+22
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| * Merge pull request #148 from romainreignier/add_stm32L4Fabien Poussin2018-03-151-0/+21
| |\ | | | | | | platform: add support for STM32L4 family
| | * platform: add support for STM32L4 familyRomain Reignier2018-03-121-0/+21
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| * | Fixed most testhal examples for STM32, updated configs using script. Fixed ↵Fabien Poussin2018-03-143-6/+6
| |/ | | | | | | deprecated MS2ST calls.
| * Keep track of STM32 RCC APIRomain Reignier2018-03-113-25/+25
| | | | | | | | | | | | | | RCC API changed in 01/2018 so apply the changes. Note that ae7a4d40b84d8afc999691577210696f16e682f6 partially fixed the changes in QEI module but some were missing. So update the other modules too.
* | hal_usbh: update to new Time macrosRomain Reignier2018-03-121-4/+4
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* | hal_fsmc: update to new RCC APIRomain Reignier2018-03-121-1/+1
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* | hal: stm32: Keep track of latest STM32 RCC APIRomain Reignier2018-03-123-25/+25
|/ | | | | | | RCC API changed in 01/2018 so apply the changes. Note that ae7a4d40b84d8afc999691577210696f16e682f6 partially fixed the changes in QEI module but some were missing. So update the other modules too.
* Fixes for STM32F0 testhalFabien Poussin2018-03-082-14/+14
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* Added support for STM32F7Adrian2018-01-315-5/+20
| | | | Tested only for STM32F746, other chipsets have to be checked.
* Add STM32F769 to FSMCv1 sdram driverDave Flogeras2017-12-143-3/+5
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* USBH: STM32 LLD: break LS activity detect loop if port is disabledDiego Ismirlian2017-08-071-11/+18
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* USBH: STM32 LLD: various improvementsDiego Ismirlian2017-07-312-112/+134
| | | | | | | | | - general cleanup - implemented workaround to undocumented erratum (the OTG core may report successful enabling of port when connecting a low-speed device, but really it generates no traffic and remains in a "dumb" state) - improved handling of disconnection of devices (avoid submitting URBs if the port is disabled)
* USBH: remove unnecessary reschedules and add necessary onesDiego Ismirlian2017-07-161-7/+1
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* USBH: Correct bug in LLDDiego Ismirlian2017-07-161-1/+1
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* USBH: moved definition of driver to LLDDiego Ismirlian2017-07-091-0/+7
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* USBH: moved declaration of driver to LLDDiego Ismirlian2017-06-091-0/+9
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* USBH: STM32 lld, activate correction of unexpected lengthDiego Ismirlian2017-06-081-1/+1
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* Mass license dates updateDiego Ismirlian2017-06-052-4/+4
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* Remove redundant hal_stm32_otg.h fileDiego Ismirlian2017-06-051-934/+0
| | | | The correct version is already present in ChibiOS
* USB Host fixesDiego Ismirlian2017-06-052-20/+92
| | | | | | | | - Cleaned up alignment macros for GCC & IAR - Corrected EP halt and Clear halt behaviours - Initialization of class drivers by USB Host main driver - Minor cosmetic fixes - Updated USB_HOST testhal app
* Add checks to QEI if STM32 TIM is already usedAndres Vahter2017-06-051-4/+54
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* [DMA2D, LTDC] Removing ch.h dependencies. Fix #111.Romain Reignier2017-02-282-2/+0
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* [Comp] Adding interrupt functions, updating example.Fabien Poussin2017-02-092-2/+200
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* [Comp] Adding support for STM32F0.Fabien Poussin2017-02-071-1/+7
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* [Comp] Adding more definesFabien Poussin2017-02-071-0/+45
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* [Comp] Adding init, helper defines.Fabien Poussin2017-02-071-0/+94
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* [Comp] Cleaning example, removing dependencies and adding checks.Fabien Poussin2017-02-072-138/+134
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* [COMP] Fixing headers, missing includes.Fabien Poussin2017-02-071-5/+5
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* Adding COMP Driver.Fabien Poussin2017-02-063-0/+665
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* [Timcap/Eeprom] Removing ch.h dependencies.Fabien Poussin2017-02-062-2/+0
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* [STM32, NAND] Fixed #elif without expressionbarthess2017-01-241-2/+1
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* FSMC NAND improvements.barthess2017-01-173-65/+140
| | | | | 1) Implemented 16 bit bus width support 2) Added workaround errata in STM32
* Merge branch 'master' of github.com:ChibiOS/ChibiOS-Contribbarthess2017-01-064-19/+33
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| * Merge pull request #107 from pl4nkton/stm32_fixesFabien Poussin2017-01-044-19/+33
| |\ | | | | | | Stm32 fixes
| | * STM32: fix USB HOST HS when cpu is in sleep modeNicolas Reinecke2016-12-051-1/+2
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| | * change qei types to int16_tPeter2016-12-051-1/+1
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| | * usbh: add otg stepping 2 codeNicolas Reinecke2016-12-052-0/+12
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| | * usbh: cleanupNicolas Reinecke2016-12-053-17/+18
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* | | NAND. Added reset function.barthess2017-01-062-8/+21
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* / FSMC. Sync mode improvements.barthess2016-12-091-2/+8
|/ | | | | | | 1) Control registers writes reordered in init sequence to eliminate incorrect output clock frequnency in short period after CCLKEN bit set and B(W)TR registers set. 2) Added reset of CCLEN bit in stop procedure.
* whitespaceNicolas Reinecke2016-11-081-8/+8
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* add STM32F7 FMC write FIFO disable bitNicolas Reinecke2016-11-081-0/+3
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* STM32 CRC : Fix assertsKimmo Lindholm2016-11-051-6/+6
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* Updated include guardsbarthess2016-10-1719-47/+47
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* [STM32 NAND] Code cleanup.barthess2016-08-181-3/+4
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* [STM32 NAND] Deleted ugly hack with EXTI interrupt instead of NAND onebarthess2016-08-164-45/+5
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* [STM32 NAND] Deleted unused defines.barthess2016-08-161-9/+0
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* Added room for STM32F7xbarthess2016-07-143-6/+26
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* added qeiAdjustI. added new field and checking in STM32Stephane D'Alu2016-07-072-0/+69
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