| Commit message (Collapse) | Author | Age | Files | Lines |
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Various Tiva improvements
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Most code from the EXT driver could be reused.
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Registers are now accessed using the HWREG() macro.
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vectors.c was replaced by vectors.S
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Add support for the Kinetis SDHC peripheral
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Updated some comments and some trace statements.
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a failed data transfer; translate card status bits into HLD error
bits. Set BLKATTR_BLKCNT even when it's not being used, which seems to
avoid errors when alternating between multi-block and single-block
transfers. Some comments.
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and other members of the Kinetis family.
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Added support for additional UARTs (up to six on the K64F).
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Also moved some code that is duplicated per-UART into
local functions to reduce the amount of duplication.
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Fix Kinetis usb databank synchronization problems
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USB control transfers are structured as the following.
For incoming transfers
Setup (Data0 out)
Data (Data1/Data0 in) - starting with data 1
Status (Data1 out)
For outgoing transfers
Setup (Data0 out)
Data (Data1/Data0 out) - starting with data 1
Status (Data1 in)
The in buffers (device to host) are always correctly synchronized, since
they can always be reset to Data1 each setup packet without any
synchronization problems.
The problem occured for outgoing transfers (host to device). For
incoming transfers the data banks always alternates, and will
automatically stay in sync. Outgoing transfers also stays in sync when
there's an odd number of data packets. However when the number is even,
including zero, then the last packet received by the device will be
data0 and the next setup packet also has to be data0, so there's a
synchronization problem.
This itself is not a problem since data toggle synchronization(DTS) is
ignored for setup packets, however if the follwoing packet after that
is also an out packet, then the data bank will be wrong and the packet
dropped. In this case the USB spec don't allow sending a nack, so it
will only recover after a timeout, when the host tries to send a new
setup packet.
The old code tried to take care of this situation by reinitializing
both data banks when a setup packet is received. The problem is that the
next packet might already have been received or is in progress of being
received at this point, so the fixup comes to late. The new code does
the fixup when a status packet is about to be sent from the device to
avoid this problem.
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Tested only for STM32F746, other chipsets have to be checked.
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Add Tiva UART driver.
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Fix for K20x startup
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When host sends TEST UNIT READY command, set sense 'all ok' if block device reports
that medium is inserted, or set sense 'medium not present' if medium is not inserted.
Do not override sense by default with 'all ok', allow REQUEST SENSE command
to be responded with correct sense data which was set on last failure.
Check just DESC bit when responding to REQUEST SENSE command.
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Tiva add ADC driver
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- general cleanup
- implemented workaround to undocumented erratum (the OTG core may
report successful enabling of port when connecting a low-speed device,
but really it generates no traffic and remains in a "dumb" state)
- improved handling of disconnection of devices (avoid submitting URBs
if the port is disabled)
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- improved connection/disconnection handling
- corrected bug on aborting non-pending URB
- corrected bug on disconnecting multiple hubs
- improved debug messages
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