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| author | Rocco Marco Guglielmi <roccomarco.guglielmi@gmail.com> | 2017-09-16 23:42:19 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@gmail.com> | 2017-09-16 23:42:19 +0000 |
| commit | 30e99fdee65f9dd4a017a5ec859fc0cc3e64897a (patch) | |
| tree | c7d91f2f8003eaa4833a2d3adb90fba8438981fd | |
| parent | 9f9468efccbf5d6cef1da9778b1309d5768eff87 (diff) | |
| download | ChibiOS-30e99fdee65f9dd4a017a5ec859fc0cc3e64897a.tar.gz ChibiOS-30e99fdee65f9dd4a017a5ec859fc0cc3e64897a.tar.bz2 ChibiOS-30e99fdee65f9dd4a017a5ec859fc0cc3e64897a.zip | |
Style fixes
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10602 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h b/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h index 5d5e3b997..c00f6b8fd 100644 --- a/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h +++ b/os/common/startup/ARM/devices/SAMA5D2/sama5d2x.h @@ -180,7 +180,7 @@ #define PERID_SPI1_TX 8 #define PERID_SPI1_RX 9 #define PERID_PWM_TX 10 -#define PERID_PWM_RX 0xff +#define PERID_PWM_RX 0XFF #define PERID_FLEXCOM0_TX 11 #define PERID_FLEXCOM0_RX 12 #define PERID_FLEXCOM1_TX 13 @@ -195,14 +195,14 @@ #define PERID_SSC0_RX 22 #define PERID_SSC1_TX 23 #define PERID_SSC1_RX 24 -#define PERID_ADC_TX 0xff +#define PERID_ADC_TX 0XFF #define PERID_ADC_RX 25 #define PERID_AES_TX 26 #define PERID_AES_RX 27 #define PERID_TDES_TX 28 #define PERID_TDES_RX 29 #define PERID_SHA_TX 30 -#define PERID_SHA_RX 0xff +#define PERID_SHA_RX 0XFF #define PERID_I2SC0_TX 31 #define PERID_I2SC0_RX 32 #define PERID_I2SC1_TX 33 @@ -217,15 +217,15 @@ #define PERID_UART3_RX 42 #define PERID_UART4_TX 43 #define PERID_UART4_RX 44 -#define PERID_TC0_TX 0xff +#define PERID_TC0_TX 0XFF #define PERID_TC0_RX 45 -#define PERID_TC1_TX 0xff +#define PERID_TC1_TX 0XFF #define PERID_TC1_RX 46 #define PERID_CLASSD_TX 47 -#define PERID_CLASSD_RX 0xff +#define PERID_CLASSD_RX 0XFF #define PERID_QSPI1_TX 48 #define PERID_QSPI1_RX 49 -#define PERID_PDMIC_TX 0xff +#define PERID_PDMIC_TX 0XFF #define PERID_PDMIC_RX 50 #define ID_SAIC_FIQ_MSK (1 << (ID_SAIC_FIQ & 0x1F)) |