Various fixes to F413 mcuconf and registry. Removed dead options in OTGv1.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12036 110e8d01-0319-4d1e-a829-52ad28d1bb01

3 files changed, 76 insertions, 11 deletions

diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h
index 2243a48a2..828e6085e 100644
--- a/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h
+++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h
@@ -102,6 +102,28 @@
 #define STM32_ADC_IRQ_PRIORITY              6

 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6

 

+/*

+ * CAN driver system settings.

+ */

+#define STM32_CAN_USE_CAN1                  FALSE

+#define STM32_CAN_USE_CAN2                  FALSE

+#define STM32_CAN_USE_CAN3                  FALSE

+#define STM32_CAN_CAN1_IRQ_PRIORITY         11

+#define STM32_CAN_CAN2_IRQ_PRIORITY         11

+#define STM32_CAN_CAN3_IRQ_PRIORITY         11

+

+/*

+ * DAC driver system settings.

+ */

+#define STM32_DAC_DUAL_MODE                 FALSE

+#define STM32_DAC_USE_DAC1_CH1              FALSE

+#define STM32_DAC_USE_DAC1_CH2              FALSE

+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)

 

 /*

  * GPT driver system settings.

@@ -191,16 +213,35 @@
 #define STM32_PWM_TIM9_IRQ_PRIORITY         7

 

 /*

+ * SDC driver system settings.

+ */

+#define STM32_SDC_SDIO_DMA_PRIORITY         3

+#define STM32_SDC_SDIO_IRQ_PRIORITY         9

+#define STM32_SDC_WRITE_TIMEOUT_MS          1000

+#define STM32_SDC_READ_TIMEOUT_MS           1000

+#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10

+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE

+#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)

+

+/*

  * SERIAL driver system settings.

  */

 #define STM32_SERIAL_USE_USART1             FALSE

 #define STM32_SERIAL_USE_USART2             FALSE

 #define STM32_SERIAL_USE_USART3             TRUE

+#define STM32_SERIAL_USE_UART4              FALSE

+#define STM32_SERIAL_USE_UART5              FALSE

 #define STM32_SERIAL_USE_USART6             FALSE

+#define STM32_SERIAL_USE_UART7              FALSE

+#define STM32_SERIAL_USE_UART8              FALSE

 #define STM32_SERIAL_USART1_PRIORITY        12

 #define STM32_SERIAL_USART2_PRIORITY        12

 #define STM32_SERIAL_USART3_PRIORITY        12

+#define STM32_SERIAL_UART4_PRIORITY         12

+#define STM32_SERIAL_UART5_PRIORITY         12

 #define STM32_SERIAL_USART6_PRIORITY        12

+#define STM32_SERIAL_UART7_PRIORITY         12

+#define STM32_SERIAL_UART8_PRIORITY         12

 

 /*

  * SPI driver system settings.

@@ -244,23 +285,43 @@
 #define STM32_UART_USE_USART1               FALSE

 #define STM32_UART_USE_USART2               FALSE

 #define STM32_UART_USE_USART3               FALSE

+#define STM32_UART_USE_UART4                FALSE

+#define STM32_UART_USE_UART5                FALSE

 #define STM32_UART_USE_USART6               FALSE

+#define STM32_UART_USE_UART7                FALSE

+#define STM32_UART_USE_UART8                FALSE

 #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)

 #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

 #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

 #define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

 #define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)

 #define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)

 #define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)

 #define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

+#define STM32_UART_UART7_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 3)

+#define STM32_UART_UART7_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 1)

+#define STM32_UART_UART8_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 6)

+#define STM32_UART_UART8_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

 #define STM32_UART_USART3_IRQ_PRIORITY      12

+#define STM32_UART_UART4_IRQ_PRIORITY       12

+#define STM32_UART_UART5_IRQ_PRIORITY       12

 #define STM32_UART_USART6_IRQ_PRIORITY      12

+#define STM32_UART_UART7_IRQ_PRIORITY       12

+#define STM32_UART_UART8_IRQ_PRIORITY       12

 #define STM32_UART_USART1_DMA_PRIORITY      0

 #define STM32_UART_USART2_DMA_PRIORITY      0

 #define STM32_UART_USART3_DMA_PRIORITY      0

+#define STM32_UART_UART4_DMA_PRIORITY       0

+#define STM32_UART_UART5_DMA_PRIORITY       0

 #define STM32_UART_USART6_DMA_PRIORITY      0

+#define STM32_UART_UART7_DMA_PRIORITY       0

+#define STM32_UART_UART8_DMA_PRIORITY       0

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

 

 /*

@@ -269,9 +330,7 @@
 #define STM32_USB_USE_OTG1                  FALSE

 #define STM32_USB_OTG1_IRQ_PRIORITY         14

 #define STM32_USB_OTG1_RX_FIFO_SIZE         512

-#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO

-#define STM32_USB_OTG_THREAD_STACK_SIZE     128

-#define STM32_USB_OTGFIFO_FILL_BASEPRI      0

+#define STM32_USB_HOST_WAKEUP_DURATION      2

 

 /*

  * WDG driver system settings.

diff --git a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
index 7ec858ee7..addfd9858 100644
--- a/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
+++ b/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.h
@@ -145,8 +145,8 @@
 /**

  * @brief   Host wake-up procedure duration.

  */

-#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)

-#define USB_HOST_WAKEUP_DURATION            2

+#if !defined(STM32_USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)

+#define STM32_USB_HOST_WAKEUP_DURATION      2

 #endif

 

 /*===========================================================================*/

@@ -259,8 +259,8 @@
 #error "the USB OTG driver requires a 48MHz clock"

 #endif

 

-#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)

-#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"

+#if (STM32_USB_HOST_WAKEUP_DURATION < 2) || (STM32_USB_HOST_WAKEUP_DURATION > 15)

+#error "invalid STM32_USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"

 #endif

 

 /*===========================================================================*/

@@ -591,7 +591,7 @@ struct USBDriver {
 #define usb_lld_wakeup_host(usbp)                                           \

   do{                                                                       \

     (usbp)->otg->DCTL |= DCTL_RWUSIG;                                       \

-    osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION);                  \

+    osalThreadSleepMilliseconds(STM32_USB_HOST_WAKEUP_DURATION);            \

     (usbp)->otg->DCTL &= ~DCTL_RWUSIG;                                      \

   } while (false)

 

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index 4c1d9b5e7..fe7ce9bb9 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -1235,12 +1235,18 @@
 /* CAN attributes.*/

 #define STM32_HAS_CAN1                      TRUE

 #define STM32_HAS_CAN2                      TRUE

-#define STM32_HAS_CAN3                      FALSE

+#define STM32_HAS_CAN3                      TRUE

 #define STM32_CAN_MAX_FILTERS               28

 

 /* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  FALSE

-#define STM32_HAS_DAC1_CH2                  FALSE

+#define STM32_HAS_DAC1_CH1                  TRUE

+#define STM32_DAC1_CH1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_DAC1_CH1_DMA_CHN              0x00700000

+

+#define STM32_HAS_DAC1_CH2                  TRUE

+#define STM32_DAC1_CH2_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_DAC1_CH2_DMA_CHN              0x07000000

+

 #define STM32_HAS_DAC2_CH1                  FALSE

 #define STM32_HAS_DAC2_CH2                  FALSE