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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2007-12-09 09:16:33 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2007-12-09 09:16:33 +0000
commitb797fc9591a6ea6ae11495142218e82fed5a69b2 (patch)
tree935df71c668ab80a5fe2d8e6f1b0e53c19e1b841 /demos/ARM7-LPC214x-GCC/chcore.c
parent62458fc5d52e57dc7ce2493b9b78f2a03319fe7c (diff)
downloadChibiOS-b797fc9591a6ea6ae11495142218e82fed5a69b2.tar.gz
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@135 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'demos/ARM7-LPC214x-GCC/chcore.c')
-rw-r--r--demos/ARM7-LPC214x-GCC/chcore.c42
1 files changed, 34 insertions, 8 deletions
diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c
index 613841437..05305b24e 100644
--- a/demos/ARM7-LPC214x-GCC/chcore.c
+++ b/demos/ARM7-LPC214x-GCC/chcore.c
@@ -116,13 +116,11 @@ void hwinit(void) {
*/
InitVIC();
VICDefVectAddr = (IOREG32)IrqHandler;
- SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
- SetVICVector(UART0IrqHandler, 1, SOURCE_UART0);
- SetVICVector(UART1IrqHandler, 2, SOURCE_UART1);
/*
* System Timer initialization, 1ms intervals.
*/
+ SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
VICIntEnable = INTMASK(SOURCE_Timer0);
TC *timer = T0Base;
timer->TC_PR = VAL_TC0_PRESCALER;
@@ -134,7 +132,7 @@ void hwinit(void) {
/*
* Other subsystems.
*/
- InitSerial();
+ InitSerial(1, 2);
InitSSP();
InitMMC();
InitBuzzer();
@@ -174,17 +172,45 @@ void chSysPuts(char *msg) {
/*
* Non-vectored IRQs handling here.
*/
-void NonVectoredIrq(void) {
-
+__attribute__((naked, weak))
+void IrqHandler(void) {
+
+ asm(".code 32 \n\t" \
+ "stmfd sp!, {r0-r3, r12, lr} \n\t");
+#ifdef THUMB
+ asm("add r0, pc, #1 \n\t" \
+ "bx r0 \n\t" \
+ ".code 16 \n\t");
+ VICVectAddr = 0;
+ asm("ldr r0, =IrqCommon \n\t" \
+ "bx r0 \n\t");
+#else
VICVectAddr = 0;
+ asm("b IrqCommon \n\t");
+#endif
}
/*
* Timer 0 IRQ handling here.
*/
-void Timer0Irq(void) {
-
+__attribute__((naked, weak))
+void T0IrqHandler(void) {
+
+ asm(".code 32 \n\t" \
+ "stmfd sp!, {r0-r3, r12, lr} \n\t");
+#ifdef THUMB
+ asm("add r0, pc, #1 \n\t" \
+ "bx r0 \n\t" \
+ ".code 16 \n\t");
+ T0IR = 1; /* Clear interrupt on match MR0. */
+ chSysTimerHandlerI();
+ VICVectAddr = 0;
+ asm("ldr r0, =IrqCommon \n\t" \
+ "bx r0 \n\t");
+#else
T0IR = 1; /* Clear interrupt on match MR0. */
chSysTimerHandlerI();
VICVectAddr = 0;
+ asm("b IrqCommon \n\t");
+#endif
}