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authorareviu <areviu.info@gmail.com>2018-03-19 19:40:09 +0000
committerareviu <areviu.info@gmail.com>2018-03-19 19:40:09 +0000
commitd82f92151f7d0fbc6b34aad78e0e02da0a619057 (patch)
tree97211273ae990a3ab60852e023960039ae6ae109 /demos/STM32/RT-STM32F103-OLIMEX_STM32_P103/halconf.h
parentbadec871127cc434bdb83a54c2a4d7dde26b073f (diff)
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update hal crypto sha lld, added integration with wolfcrypt
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11824 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'demos/STM32/RT-STM32F103-OLIMEX_STM32_P103/halconf.h')
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generated by cgit v1.2.3 (git 2.25.1) at 2025-06-04 15:29:46 +0000
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library ieee;
use ieee.std_logic_1164.all;

entity ent1 is
    port (
        clk : in std_logic;
        o : out std_logic_vector (0 to 7)
    );
end ent1;

architecture a of ent1 is
    type reg_t is array(0 to 7) of std_logic_vector(0 to 7);

    signal reg : reg_t := (x"10", x"11", x"12", x"13",
                           x"14", x"15", x"16", x"17");
begin
    process(clk)
    begin
        if rising_edge(clk) then
            reg <= reg(1 to 7) & x"00";
        end if;
    end process;

    o <= reg (0);
end;