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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 13:07:25 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-22 13:07:25 +0000 |
| commit | e8cd09482172ce6ef2bc4e56f6258f3747ad06cc (patch) | |
| tree | 5f0706d566f42913028096505824ab541b8172e7 /os/hal/boards/ST_NUCLEO_F091RC/board.h | |
| parent | 51e94075b0fd08e41765ff379cdd011f181550da (diff) | |
| download | ChibiOS-e8cd09482172ce6ef2bc4e56f6258f3747ad06cc.tar.gz ChibiOS-e8cd09482172ce6ef2bc4e56f6258f3747ad06cc.tar.bz2 ChibiOS-e8cd09482172ce6ef2bc4e56f6258f3747ad06cc.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8378 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/boards/ST_NUCLEO_F091RC/board.h')
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_F091RC/board.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/os/hal/boards/ST_NUCLEO_F091RC/board.h b/os/hal/boards/ST_NUCLEO_F091RC/board.h index a0f4a8072..b76e3d3ec 100644 --- a/os/hal/boards/ST_NUCLEO_F091RC/board.h +++ b/os/hal/boards/ST_NUCLEO_F091RC/board.h @@ -61,8 +61,8 @@ #define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
-#define GPIOA_OTG_FS_DM 11U
-#define GPIOA_OTG_FS_DP 12U
+#define GPIOA_PIN11 11U
+#define GPIOA_PIN12 12U
#define GPIOA_SWDIO 13U
#define GPIOA_SWCLK 14U
#define GPIOA_PIN15 15U
@@ -178,8 +178,8 @@ *
* PA0 - PIN0 (input pullup).
* PA1 - PIN1 (input pullup).
- * PA2 - USART_TX (alternate 7).
- * PA3 - USART_RX (alternate 7).
+ * PA2 - USART_TX (alternate 1).
+ * PA3 - USART_RX (alternate 1).
* PA4 - PIN4 (input pullup).
* PA5 - LED_GREEN (output pushpull high).
* PA6 - PIN6 (input pullup).
@@ -187,8 +187,8 @@ * PA8 - PIN8 (input pullup).
* PA9 - PIN9 (input pullup).
* PA10 - PIN10 (input pullup).
- * PA11 - OTG_FS_DM (alternate 10).
- * PA12 - OTG_FS_DP (alternate 10).
+ * PA11 - PIN11 (input floating).
+ * PA12 - PIN12 (input floating).
* PA13 - SWDIO (alternate 0).
* PA14 - SWCLK (alternate 0).
* PA15 - PIN15 (input pullup).
@@ -204,8 +204,8 @@ PIN_MODE_INPUT(GPIOA_PIN8) | \
PIN_MODE_INPUT(GPIOA_PIN9) | \
PIN_MODE_INPUT(GPIOA_PIN10) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_INPUT(GPIOA_PIN11) | \
+ PIN_MODE_INPUT(GPIOA_PIN12) | \
PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
PIN_MODE_INPUT(GPIOA_PIN15))
@@ -220,8 +220,8 @@ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
@@ -236,8 +236,8 @@ PIN_OSPEED_40M(GPIOA_PIN8) | \
PIN_OSPEED_40M(GPIOA_PIN9) | \
PIN_OSPEED_40M(GPIOA_PIN10) | \
- PIN_OSPEED_40M(GPIOA_OTG_FS_DM) | \
- PIN_OSPEED_40M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_40M(GPIOA_PIN11) | \
+ PIN_OSPEED_40M(GPIOA_PIN12) | \
PIN_OSPEED_40M(GPIOA_SWDIO) | \
PIN_OSPEED_40M(GPIOA_SWCLK) | \
PIN_OSPEED_40M(GPIOA_PIN15))
@@ -252,8 +252,8 @@ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN12) | \
PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
PIN_PUPDR_PULLUP(GPIOA_PIN15))
@@ -268,15 +268,15 @@ PIN_ODR_HIGH(GPIOA_PIN8) | \
PIN_ODR_HIGH(GPIOA_PIN9) | \
PIN_ODR_HIGH(GPIOA_PIN10) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_PIN11) | \
+ PIN_ODR_HIGH(GPIOA_PIN12) | \
PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \
PIN_AFIO_AF(GPIOA_PIN1, 0) | \
- PIN_AFIO_AF(GPIOA_USART_TX, 7) | \
- PIN_AFIO_AF(GPIOA_USART_RX, 7) | \
+ PIN_AFIO_AF(GPIOA_USART_TX, 1) | \
+ PIN_AFIO_AF(GPIOA_USART_RX, 1) | \
PIN_AFIO_AF(GPIOA_PIN4, 0) | \
PIN_AFIO_AF(GPIOA_LED_GREEN, 0) | \
PIN_AFIO_AF(GPIOA_PIN6, 0) | \
@@ -284,8 +284,8 @@ #define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
PIN_AFIO_AF(GPIOA_PIN9, 0) | \
PIN_AFIO_AF(GPIOA_PIN10, 0) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN12, 0) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_PIN15, 0))
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