git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1426 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 122 insertions, 47 deletions

diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index 3c9092ad5..b1e4f7bc3 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -55,6 +55,10 @@ void stop_channels(PWMDriver *pwmp) {
 

   pwmp->pd_enabled_channels = 0;            /* All channels disabled.       */

   pwmp->pd_tim->CCER = 0;                   /* Outputs disabled.            */

+  pwmp->pd_tim->CCR1 = 0;                   /* Comparator 1 disabled.       */

+  pwmp->pd_tim->CCR2 = 0;                   /* Comparator 2 disabled.       */

+  pwmp->pd_tim->CCR3 = 0;                   /* Comparator 3 disabled.       */

+  pwmp->pd_tim->CCR4 = 0;                   /* Comparator 4 disabled.       */

   pwmp->pd_tim->CCMR1 = 0;                  /* Channels 1 and 2 frozen.     */

   pwmp->pd_tim->CCMR2 = 0;                  /* Channels 3 and 4 frozen.     */

 }

@@ -93,13 +97,14 @@ CH_IRQ_HANDLER(VectorAC) {
   sr = TIM1->SR;

   TIM1->SR &= ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);

   if ((sr & TIM_SR_CC1IF) != 0)

-    PWMD1.pd_channel_configs[0]->pcc_callback();

+    PWMD1.pd_config->pc_channels[0].pcc_callback();

   if ((sr & TIM_SR_CC2IF) != 0)

-    PWMD1.pd_channel_configs[1]->pcc_callback();

+    PWMD1.pd_config->pc_channels[1].pcc_callback();

   if ((sr & TIM_SR_CC3IF) != 0)

-    PWMD1.pd_channel_configs[2]->pcc_callback();

+    PWMD1.pd_config->pc_channels[2].pcc_callback();

   if ((sr & TIM_SR_CC4IF) != 0)

-    PWMD1.pd_channel_configs[3]->pcc_callback();

+    PWMD1.pd_config->pc_channels[3].pcc_callback();

+

   CH_IRQ_EPILOGUE();

 }

 #endif /* USE_STM32_PWM1 */

@@ -132,6 +137,7 @@ void pwm_lld_init(void) {
  * @param[in] pwmp pointer to a @p PWMDriver object

  */

 void pwm_lld_start(PWMDriver *pwmp) {

+  uint16_t ccer;

 

   if (pwmp->pd_state == PWM_STOP) {

     /* Clock activation.*/

@@ -147,18 +153,27 @@ void pwm_lld_start(PWMDriver *pwmp) {
   stop_channels(pwmp);

 

   /* Configuration or reconfiguration.*/

-  pwmp->pd_tim->CR1 = pwmp->pd_config->pc_cr1;

-  pwmp->pd_tim->CR2 = pwmp->pd_config->pc_cr2;

-  pwmp->pd_tim->PSC = pwmp->pd_config->pc_psc;

-  pwmp->pd_tim->ARR = pwmp->pd_config->pc_arr;

-  pwmp->pd_tim->CNT = 0;

-  pwmp->pd_tim->EGR = TIM_EGR_UG;           /* Update event.                */

-  pwmp->pd_tim->SR = 0;                     /* Clear pending IRQs.          */

-  if (pwmp->pd_config->pc_callback == NULL)

-    pwmp->pd_tim->DIER = 0;                 /* No IRQs.                     */

-  else

-    pwmp->pd_tim->DIER = TIM_DIER_UIE;      /* IRQ on update event.         */

-  pwmp->pd_tim->CR1 |= TIM_CR1_CEN;         /* Starts the timer.            */

+  pwmp->pd_tim->CR1  = 0;                   /* Timer stopped.               */

+  pwmp->pd_tim->SMCR = 0;                   /* Slave mode disabled.         */

+  pwmp->pd_tim->CR2  = pwmp->pd_config->pc_cr2;

+  pwmp->pd_tim->PSC  = pwmp->pd_config->pc_psc;

+  pwmp->pd_tim->CNT  = 0;

+  pwmp->pd_tim->ARR  = pwmp->pd_config->pc_arr;

+  ccer = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;

+  if (pwmp->pd_config->pc_channels[0].pcc_mode == PWM_ACTIVE_LOW)

+    ccer |= TIM_CCER_CC1P;

+  if (pwmp->pd_config->pc_channels[1].pcc_mode == PWM_ACTIVE_LOW)

+    ccer |= TIM_CCER_CC2P;

+  if (pwmp->pd_config->pc_channels[2].pcc_mode == PWM_ACTIVE_LOW)

+    ccer |= TIM_CCER_CC3P;

+  if (pwmp->pd_config->pc_channels[3].pcc_mode == PWM_ACTIVE_LOW)

+    ccer |= TIM_CCER_CC4P;

+  pwmp->pd_tim->CCER = ccer;

+  pwmp->pd_tim->EGR  = TIM_EGR_UG;          /* Update event.                */

+  pwmp->pd_tim->SR   = 0;                   /* Clear pending IRQs.          */

+  pwmp->pd_tim->DIER = pwmp->pd_config->pc_callback == NULL ? 0 : TIM_DIER_UIE;

+  pwmp->pd_tim->CR1  = TIM_CR1_ARPE | TIM_CR1_URS |

+                       TIM_CR1_CEN;         /* Timer configured and started.*/

 }

 

 /**

@@ -167,9 +182,12 @@ void pwm_lld_start(PWMDriver *pwmp) {
  * @param[in] pwmp pointer to a @p PWMDriver object

  */

 void pwm_lld_stop(PWMDriver *pwmp) {

-

   /* If in ready state then disables the PWM clock.*/

   if (pwmp->pd_state == PWM_READY) {

+    stop_channels(pwmp);

+    pwmp->pd_tim->CR1 = 0;

+    pwmp->pd_tim->DIER = 0;

+

 #if USE_STM32_PWM1

     if (&PWMD1 == pwmp) {

       NVICDisableVector(TIM1_UP_IRQn);

@@ -178,35 +196,6 @@ void pwm_lld_stop(PWMDriver *pwmp) {
     }

 #endif

   }

-

-  stop_channels(pwmp);

-  pwmp->pd_tim->CR1 = 0;

-  pwmp->pd_tim->DIER = 0;

-}

-

-/**

- * @brief Determines whatever the PWM channel is already enabled.

- *
- * @param[in] pwmp      pointer to a @p PWMDriver object

- * @param[in] channel   PWM channel identifier

- *

- * @return The PWM channel status.

- * @retval FALSE the channel is not enabled.

- * @retval TRUE the channel is enabled.
- */

-bool_t pwm_lld_is_enabled(PWMDriver *pwmp, pwmchannel_t channel) {

-

-  return (pwmp->pd_enabled_channels & (1 << channel)) != 0;

-}

-

-/**

- * @brief Setups a PWM channel.

- *

- * @param[in] pwmp      pointer to a @p PWMDriver object

- * @param[in] channel   PWM channel identifier

- */

-void pwm_lld_setup_channel(PWMDriver *pwmp, pwmchannel_t channel) {

-

 }

 

 /**

@@ -220,7 +209,67 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
                             pwmchannel_t channel,

                             pwmcnt_t width) {

 

-  pwmp->pd_enabled_channels |= (1 << channel);

+  /*

+   * Changes the pulse width.
+   */

+  switch (channel) {

+  case 0:

+    pwmp->pd_tim->CCR1 = width;

+    break;

+  case 1:

+    pwmp->pd_tim->CCR2 = width;

+    break;

+  case 2:

+    pwmp->pd_tim->CCR3 = width;

+    break;

+  case 3:

+    pwmp->pd_tim->CCR4 = width;

+    break;

+  }

+  if ((pwmp->pd_enabled_channels & (1 << channel)) == 0) {

+    /*

+     * The channel is not enabled yet.
+     */

+    pwmp->pd_enabled_channels |= (1 << channel);

+    /*

+     * Setup the comparator, the channel is configured as PWM mode 1 with

+     * preload enabled.

+     */

+    switch (channel) {

+    case 0:

+      pwmp->pd_tim->CCMR1 = (pwmp->pd_tim->CCMR1 & 0xFF00) |

+                            TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |

+                            TIM_CCMR1_OC1PE;

+      pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[0].pcc_callback == NULL

+                            ? 0 : TIM_DIER_CC1IE;

+      pwmp->pd_tim->SR = ~TIM_SR_CC1IF;

+      break;

+    case 1:

+      pwmp->pd_tim->CCMR1 = (pwmp->pd_tim->CCMR1 & 0x00FF) |

+                            TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 |

+                            TIM_CCMR1_OC2PE;

+      pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[1].pcc_callback == NULL

+                            ? 0 : TIM_DIER_CC2IE;

+      pwmp->pd_tim->SR = ~TIM_SR_CC2IF;

+      break;

+    case 2:

+      pwmp->pd_tim->CCMR2 = (pwmp->pd_tim->CCMR2 & 0xFF00) |

+                            TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |

+                            TIM_CCMR2_OC3PE;

+      pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[2].pcc_callback == NULL

+                            ? 0 : TIM_DIER_CC3IE;

+      pwmp->pd_tim->SR = ~TIM_SR_CC3IF;

+      break;

+    case 3:

+      pwmp->pd_tim->CCMR2 = (pwmp->pd_tim->CCMR2 & 0x00FF) |

+                            TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 |

+                            TIM_CCMR2_OC4PE;

+      pwmp->pd_tim->DIER |= pwmp->pd_config->pc_channels[3].pcc_callback == NULL

+                            ? 0 : TIM_DIER_CC4IE;

+      pwmp->pd_tim->SR = ~TIM_SR_CC4IF;

+      break;

+    }

+  }

 }

 

 /**

@@ -234,6 +283,32 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
 void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {

 

   pwmp->pd_enabled_channels &= ~(1 << channel);

+  switch (channel) {

+  case 0:

+    pwmp->pd_tim->CCR1 = 0;

+    pwmp->pd_tim->CCMR1 = pwmp->pd_tim->CCMR1 & 0xFF00;

+    pwmp->pd_tim->DIER &= ~TIM_DIER_CC1IE;

+    pwmp->pd_tim->SR = ~TIM_SR_CC1IF;

+    break;

+  case 1:

+    pwmp->pd_tim->CCR2 = 0;

+    pwmp->pd_tim->CCMR1 = pwmp->pd_tim->CCMR1 & 0x00FF;

+    pwmp->pd_tim->DIER &= ~TIM_DIER_CC2IE;

+    pwmp->pd_tim->SR = ~TIM_SR_CC2IF;

+    break;

+  case 2:

+    pwmp->pd_tim->CCR3 = 0;

+    pwmp->pd_tim->CCMR2 = pwmp->pd_tim->CCMR2 & 0xFF00;

+    pwmp->pd_tim->DIER &= ~TIM_DIER_CC3IE;

+    pwmp->pd_tim->SR = ~TIM_SR_CC3IF;

+    break;

+  case 3:

+    pwmp->pd_tim->CCR4 = 0;

+    pwmp->pd_tim->CCMR2 = pwmp->pd_tim->CCMR2 & 0x00FF;

+    pwmp->pd_tim->DIER &= ~TIM_DIER_CC4IE;

+    pwmp->pd_tim->SR = ~TIM_SR_CC4IF;

+    break;

+  }

 }

 

 #endif /* CH_HAL_USE_PWM */