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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-05-09 17:52:30 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-05-09 17:52:30 +0000
commitbf0c75c33e3c4ec0e19637d5da45e24f537295d9 (patch)
tree8b5f2798a01edeae0b4bc6188de3b0564ee7968b /os/hal/platforms/STM32/serial_lld.c
parent691538eb399e9a0ca1e8ed86699c58e3022d6fd5 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1911 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/serial_lld.c')
-rw-r--r--os/hal/platforms/STM32/serial_lld.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c
index fe9baea3d..4f7aee1e0 100644
--- a/os/hal/platforms/STM32/serial_lld.c
+++ b/os/hal/platforms/STM32/serial_lld.c
@@ -92,16 +92,16 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
* Baud rate setting.
*/
if (sdp->usart == USART1)
- u->BRR = APB2CLK / config->sc_speed;
+ u->BRR = STM32_PCLK2 / config->sc_speed;
else
- u->BRR = APB1CLK / config->sc_speed;
+ u->BRR = STM32_PCLK1 / config->sc_speed;
/*
* Note that some bits are enforced.
*/
u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
- USART_CR1_RXNEIE | USART_CR1_TE |
- USART_CR1_RE;
+ USART_CR1_RXNEIE | USART_CR1_TE |
+ USART_CR1_RE;
u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
u->CR3 = config->sc_cr3 | USART_CR3_EIE;
(void)u->SR; /* SR reset step 1.*/