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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-12-09 14:12:52 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-12-09 14:12:52 +0000 |
| commit | e8ce87c3272de1d7fadedd2b4cd6b41d0cb6acdf (patch) | |
| tree | 76bb1442d22a869b38a3bd7f635e7f291fe65951 /os/hal/platforms/STM32F1xx/stm32_rcc.h | |
| parent | db6fea6a28e94cf3beeb720e97c25014535e9f71 (diff) | |
| download | ChibiOS-e8ce87c3272de1d7fadedd2b4cd6b41d0cb6acdf.tar.gz ChibiOS-e8ce87c3272de1d7fadedd2b4cd6b41d0cb6acdf.tar.bz2 ChibiOS-e8ce87c3272de1d7fadedd2b4cd6b41d0cb6acdf.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6564 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/stm32_rcc.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index 61d68831a..8de6ec43c 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -746,6 +746,56 @@ #define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
* @brief Enables the TIM8 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
|