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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-12-09 11:29:07 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-12-09 11:29:07 +0000
commitdb6fea6a28e94cf3beeb720e97c25014535e9f71 (patch)
treeaa547d17a8fb2aad04928428ac28cd64401ca4fa /os/hal/platforms/STM32F1xx
parent41e76064d6b940f5adb5be8a73a450f450c3e9fd (diff)
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Fixed bugs #445 and #446.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6560 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx')
-rw-r--r--os/hal/platforms/STM32F1xx/adc_lld.c27
1 files changed, 13 insertions, 14 deletions
diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c
index 9e9bbfb7d..926fb9c5a 100644
--- a/os/hal/platforms/STM32F1xx/adc_lld.c
+++ b/os/hal/platforms/STM32F1xx/adc_lld.c
@@ -63,14 +63,14 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
}
else {
- if ((flags & STM32_DMA_ISR_HTIF) != 0) {
- /* Half transfer processing.*/
- _adc_isr_half_code(adcp);
- }
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_adc_isr_full_code(adcp);
}
+ else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _adc_isr_half_code(adcp);
+ }
}
}
@@ -181,23 +181,22 @@ void adc_lld_stop(ADCDriver *adcp) {
* @notapi
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t mode, n, cr2;
+ uint32_t mode, cr2;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
mode = adcp->dmamode;
- if (grpp->circular)
+ if (grpp->circular) {
mode |= STM32_DMA_CR_CIRC;
- if (adcp->depth > 1) {
- /* If the buffer depth is greater than one then the half transfer interrupt
- interrupt is enabled in order to allows streaming processing.*/
- mode |= STM32_DMA_CR_HTIE;
- n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth;
+ if (adcp->depth > 1) {
+ /* If circular buffer depth > 1, then the half transfer interrupt
+ is enabled in order to allow streaming processing.*/
+ mode |= STM32_DMA_CR_HTIE;
+ }
}
- else
- n = (uint32_t)grpp->num_channels;
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
- dmaStreamSetTransactionSize(adcp->dmastp, n);
+ dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+ (uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);