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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-04-06 18:41:34 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-04-06 18:41:34 +0000 |
| commit | 7cfab88550523fc375231131f3043d7fe82ebc29 (patch) | |
| tree | 2dcd057addd37640ff0402b5413c3de9ac6f68b1 /os/hal/platforms/STM32F30x/stm32_rcc.h | |
| parent | 85513252eea3357ce2efe177a10fc548d03669a2 (diff) | |
| download | ChibiOS-7cfab88550523fc375231131f3043d7fe82ebc29.tar.gz ChibiOS-7cfab88550523fc375231131f3043d7fe82ebc29.tar.bz2 ChibiOS-7cfab88550523fc375231131f3043d7fe82ebc29.zip | |
Added support for timers 6, 7, 9, 11, 12, 14 to the STM32 GPT driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5551 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F30x/stm32_rcc.h')
| -rw-r--r-- | os/hal/platforms/STM32F30x/stm32_rcc.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32F30x/stm32_rcc.h b/os/hal/platforms/STM32F30x/stm32_rcc.h index 13ea6bf99..9cc2edf52 100644 --- a/os/hal/platforms/STM32F30x/stm32_rcc.h +++ b/os/hal/platforms/STM32F30x/stm32_rcc.h @@ -578,6 +578,56 @@ #define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
* @brief Enables the TIM8 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
|