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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-27 11:31:57 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-27 11:31:57 +0000 |
| commit | d2c0aea892777c860fa29e18eda06bd6c0694f48 (patch) | |
| tree | 0d12400674b762f65ee63d9b7c58eaec0bca9bcc /os/hal/platforms/STM32F3xx/stm32_rcc.h | |
| parent | 1c4914bb0d7f7cf942cd5634d3f21e0c7a85a357 (diff) | |
| download | ChibiOS-d2c0aea892777c860fa29e18eda06bd6c0694f48.tar.gz ChibiOS-d2c0aea892777c860fa29e18eda06bd6c0694f48.tar.bz2 ChibiOS-d2c0aea892777c860fa29e18eda06bd6c0694f48.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4977 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F3xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/platforms/STM32F3xx/stm32_rcc.h | 37 |
1 files changed, 31 insertions, 6 deletions
diff --git a/os/hal/platforms/STM32F3xx/stm32_rcc.h b/os/hal/platforms/STM32F3xx/stm32_rcc.h index 7c4b30466..6c9078940 100644 --- a/os/hal/platforms/STM32F3xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F3xx/stm32_rcc.h @@ -169,29 +169,54 @@ * @{
*/
/**
- * @brief Enables the ADC1 peripheral clock.
+ * @brief Enables the ADC1/ADC2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
+#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
/**
- * @brief Disables the ADC1 peripheral clock.
+ * @brief Disables the ADC1/ADC2 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
/**
- * @brief Resets the ADC1 peripheral.
+ * @brief Resets the ADC1/ADC2 peripheral.
*
* @api
*/
-#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
+#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
+
+/**
+ * @brief Enables the ADC3/ADC4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
+
+/**
+ * @brief Disables the ADC3/ADC4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
+
+/**
+ * @brief Resets the ADC3/ADC4 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
/** @} */
/**
|