aboutsummaryrefslogtreecommitdiffstats
path: root/os/hal/platforms/STM32F4xx
diff options
context:
space:
mode:
authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-08-18 13:17:03 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-08-18 13:17:03 +0000
commitf50d9fb0480b9ce521e80af21ffbff79e0ca5b44 (patch)
treebc64438ca199758ca29135e6c747b6e8c21cba93 /os/hal/platforms/STM32F4xx
parentebc792e58d45d96506bdb7afe379b4ddee9bc48e (diff)
downloadChibiOS-f50d9fb0480b9ce521e80af21ffbff79e0ca5b44.tar.gz
ChibiOS-f50d9fb0480b9ce521e80af21ffbff79e0ca5b44.tar.bz2
ChibiOS-f50d9fb0480b9ce521e80af21ffbff79e0ca5b44.zip
Added support for STM32 OTH_HS peripheral (not tested yet).
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4578 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx')
-rw-r--r--os/hal/platforms/STM32F4xx/stm32_rcc.h29
-rw-r--r--os/hal/platforms/STM32F4xx/stm32f4xx.h10
2 files changed, 33 insertions, 6 deletions
diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h
index 367318e04..6418abe81 100644
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h
@@ -603,7 +603,7 @@
*
* @api
*/
-#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
/**
* @brief Disables the OTG_FS peripheral clock.
@@ -612,7 +612,7 @@
*
* @api
*/
-#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
/**
* @brief Resets the OTG_FS peripheral.
@@ -620,6 +620,31 @@
* @api
*/
#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+
+/**
+ * @brief Enables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+
+/**
+ * @brief Disables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp)
+
+/**
+ * @brief Resets the OTG_HS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHSRST)
/** @} */
/**
diff --git a/os/hal/platforms/STM32F4xx/stm32f4xx.h b/os/hal/platforms/STM32F4xx/stm32f4xx.h
index f4e88fc17..52b9f24e2 100644
--- a/os/hal/platforms/STM32F4xx/stm32f4xx.h
+++ b/os/hal/platforms/STM32F4xx/stm32f4xx.h
@@ -12,15 +12,15 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
- * - To use or not the peripheral’s drivers in application code(i.e.
- * code will be based on direct access to peripheral’s registers
+ * - To use or not the peripheral�s drivers in application code(i.e.
+ * code will be based on direct access to peripheral�s registers
* rather than drivers API), this option is controlled by
* "#define USE_STDPERIPH_DRIVER"
* - To change few application-specific parameters such as the HSE
* crystal frequency
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
+ * - Macros to access peripheral�s registers hardware
*
******************************************************************************
* @attention
@@ -4953,7 +4953,9 @@ typedef struct
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+/* CHIBIOS FIX */
+/*#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)*/
+#define RCC_AHB1RSTR_OTGHSRST ((uint32_t)0x10000000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)