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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-04-01 13:21:02 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-04-01 13:21:02 +0000
commitcf15276df33e24a72eedf38af97dde3f3404fce2 (patch)
tree6dff8618bb4c1f5ee989e0ef2368470d5a0dffde /os/hal/platforms
parent01b0220ffa200db034b0be6b0f464ec3344e3c15 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2863 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms')
-rw-r--r--os/hal/platforms/STM32/pwm_lld.h26
1 files changed, 5 insertions, 21 deletions
diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h
index e36b6f1f6..3d0d9d79c 100644
--- a/os/hal/platforms/STM32/pwm_lld.h
+++ b/os/hal/platforms/STM32/pwm_lld.h
@@ -41,37 +41,20 @@
#define PWM_CHANNELS 4
/**
- * @brief Standard output modes mask.
- */
-#define PWM_OUTPUT_MASK 0x07
-
-/**
- * @brief Output not driven, callback only.
- */
-#define PWM_OUTPUT_DISABLED 0x00
-
-/**
- * @brief Positive PWM logic, active is logic level one.
- */
-#define PWM_OUTPUT_ACTIVE_HIGH 0x01
-
-/**
- * @brief Inverse PWM logic, active is logic level zero.
- */
-#define PWM_OUTPUT_ACTIVE_LOW 0x02
-
-/**
* @brief Complementary output modes mask.
+ * @note This is an STM32-specific setting.
*/
-#define PWM_COMPLEMENTARY_OUTPUT_MASK 0x70
+#define PWM_COMPLEMENTARY_OUTPUT_MASK 0xF0
/**
* @brief Complementary output not driven.
+ * @note This is an STM32-specific setting.
*/
#define PWM_COMPLEMENTARY_OUTPUT_DISABLED 0x00
/**
* @brief Complementary output, active is logic level one.
+ * @note This is an STM32-specific setting.
* @note This setting is only available if the configuration option
* @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced
* timers TIM1 and TIM8.
@@ -80,6 +63,7 @@
/**
* @brief Complementary output, active is logic level zero.
+ * @note This is an STM32-specific setting.
* @note This setting is only available if the configuration option
* @p STM32_PWM_USE_ADVANCED is set to TRUE and only for advanced
* timers TIM1 and TIM8.