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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-14 09:34:28 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-14 09:34:28 +0000 |
| commit | ecd03e17cec7c9d2d928314d59e9d4ed427f74c3 (patch) | |
| tree | 3ad9582def8ebc7914b63f028b0a26f5629cae83 /os/hal/ports | |
| parent | 3ae66789001a8625881c5e10c96e382626478993 (diff) | |
| download | ChibiOS-ecd03e17cec7c9d2d928314d59e9d4ed427f74c3.tar.gz ChibiOS-ecd03e17cec7c9d2d928314d59e9d4ed427f74c3.tar.bz2 ChibiOS-ecd03e17cec7c9d2d928314d59e9d4ed427f74c3.zip | |
Various fixes after mass test-compile.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11268 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/LPC/LPC214x/hal_pal_lld.c | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c | 1 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 2 |
3 files changed, 3 insertions, 1 deletions
diff --git a/os/hal/ports/LPC/LPC214x/hal_pal_lld.c b/os/hal/ports/LPC/LPC214x/hal_pal_lld.c index 162c5348e..5903df2ea 100644 --- a/os/hal/ports/LPC/LPC214x/hal_pal_lld.c +++ b/os/hal/ports/LPC/LPC214x/hal_pal_lld.c @@ -100,6 +100,7 @@ void _pal_lld_setgroupmode(ioportid_t port, break;
case PAL_MODE_UNCONNECTED:
port->FIO_PIN |= mask;
+ /* Falls through.*/
case PAL_MODE_OUTPUT_PUSHPULL:
port->FIO_DIR |= mask;
break;
diff --git a/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c index 9f5a56952..9f8bde707 100644 --- a/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/STM32/LLD/USBv1/hal_usb_lld.c @@ -588,6 +588,7 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { #else
osalDbgAssert(false, "isochronous support disabled");
#endif
+ /* Falls through.*/
case USB_EP_MODE_TYPE_BULK:
epr = EPR_EP_TYPE_BULK;
break;
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index f0c7dfb99..094d6900f 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -528,7 +528,7 @@ */
#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
RCC_AHB1ENR_ETHMACTXEN | \
- RCC_AHB1ENR_ETHMACRXEN)
+ RCC_AHB1ENR_ETHMACRXEN, lp)
/**
* @brief Disables the ETH peripheral clock.
|