git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6081 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 384 insertions, 138 deletions

diff --git a/os/halnew/platforms/STM32/st_lld.c b/os/halnew/platforms/STM32/st_lld.c
new file mode 100644
index 000000000..ed1c03c56
--- /dev/null
+++ b/os/halnew/platforms/STM32/st_lld.c
@@ -0,0 +1,126 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    STM32/st_lld.c

+ * @brief   ST Driver subsystem low level driver code.

+ *

+ * @addtogroup ST

+ * @{

+ */

+

+#include "hal.h"

+

+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local types.                                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)

+/**

+ * @brief   System Timer vector.

+ * @details This interrupt is used for system tick in periodic mode.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(SysTickVector) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  osalSysLockFromISR();

+  osalOsTimerHandlerI();

+  osalSysUnlockFromISR();

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)

+/**

+ * @brief   TIM2 interrupt handler.

+ * @details This interrupt is used for system tick in free running mode.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {

+

+  OSAL_IRQ_PROLOGUE();

+

+  STM32_TIM2->SR = 0;

+

+  osalSysLockFromISR();

+  osalTimerHandlerI();

+  osalSysUnlockFromISR();

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level ST driver initialization.

+ *

+ * @notapi

+ */

+void st_lld_init(void) {

+

+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING

+  /* Free running counter mode.*/

+  rccEnableTIM2(FALSE);

+  nvicEnableVector(STM32_TIM2_NUMBER, ST_TIMER_PRIORITY_MASK);

+  STM32_TIM2->PSC = STM32_TIMCLK2 / OSAL_SYSTICK_FREQUENCY - 1;

+#endif

+

+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

+  /* Periodic systick mode, the Cortex-Mx internal systick timer is used

+     in this mode.*/

+  SysTick->LOAD = STM32_HCLK / OSAL_SYSTICK_FREQUENCY - 1;

+  SysTick->VAL = 0;

+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

+                  SysTick_CTRL_ENABLE_Msk |

+                  SysTick_CTRL_TICKINT_Msk;

+

+  nvicSetSystemHandlerPriority(HANDLER_SYSTICK, ST_TIMER_PRIORITY_MASK);

+#endif

+}

+

+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */

+

+/** @} */

diff --git a/os/halnew/platforms/STM32/st_lld.h b/os/halnew/platforms/STM32/st_lld.h
new file mode 100644
index 000000000..f9cdbb8fd
--- /dev/null
+++ b/os/halnew/platforms/STM32/st_lld.h
@@ -0,0 +1,95 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    STM32/st_lld.h

+ * @brief   ST Driver subsystem low level driver header.

+ *

+ * @addtogroup ST

+ * @{

+ */

+

+#ifndef _ST_LLD_H_

+#define _ST_LLD_H_

+

+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Configuration options

+ * @{

+ */

+/**

+ * @brief   SysTick timer priority mask.

+ */

+#if !defined(ST_TIMER_PRIORITY_MASK) || defined(__DOXYGEN__)

+#define ST_TIMER_PRIORITY_MASK              0x80

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if !(OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) &&                             \

+    !(OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING)

+#error "invalid OSAL_ST_MODE setting in osal.h"

+#endif

+

+#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) && !STM32_HAS_TIM2

+#error "TIM2 not present in the selected device"

+#endif

+

+#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) && !STM32_TIM2_IS_32BITS

+#error "TIM2 is not a 32 bits timer"

+#endif

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void st_lld_init(void);

+#ifdef __cplusplus

+}

+#endif

+

+/*===========================================================================*/

+/* Driver inline functions.                                                  */

+/*===========================================================================*/

+

+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */

+

+#endif /* _ST_LLD_H_ */

+

+/** @} */

diff --git a/os/halnew/platforms/STM32F30x/stm32_registry.h b/os/halnew/platforms/STM32F30x/stm32_registry.h
index f32637aa4..20d3dc62b 100644
--- a/os/halnew/platforms/STM32F30x/stm32_registry.h
+++ b/os/halnew/platforms/STM32F30x/stm32_registry.h
@@ -34,174 +34,199 @@
  * @{

  */

 /* ADC attributes.*/

-#define STM32_HAS_ADC1          TRUE

-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1))

-#define STM32_ADC1_DMA_CHN      0x00000000

+#define STM32_HAS_ADC1                  TRUE

+#define STM32_ADC1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 1))

+#define STM32_ADC1_DMA_CHN              0x00000000

 

-#define STM32_HAS_ADC2          TRUE

-#define STM32_ADC2_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 1) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_ADC2_DMA_CHN      0x00000000

+#define STM32_HAS_ADC2                  TRUE

+#define STM32_ADC2_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 1) |    \

+                                         STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_ADC2_DMA_CHN               0x00000000

 

-#define STM32_HAS_ADC3          TRUE

-#define STM32_ADC3_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_ADC3_DMA_CHN      0x00000000

+#define STM32_HAS_ADC3                  TRUE

+#define STM32_ADC3_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_ADC3_DMA_CHN              0x00000000

 

-#define STM32_HAS_ADC4          TRUE

-#define STM32_ADC4_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(2, 2) |            \

-                                 STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_ADC4_DMA_CHN      0x00000000

+#define STM32_HAS_ADC4                  TRUE

+#define STM32_ADC4_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 2) |    \

+                                         STM32_DMA_STREAM_ID_MSK(2, 4))

+#define STM32_ADC4_DMA_CHN              0x00000000

 

-#define STM32_HAS_SDADC1        FALSE

-#define STM32_SDADC1_DMA_MSK    0

-#define STM32_SDADC1_DMA_CHN    0x00000000

-

-#define STM32_HAS_SDADC2        FALSE

-#define STM32_SDADC2_DMA_MSK    0

-#define STM32_SDADC2_DMA_CHN    0x00000000

-

-#define STM32_HAS_SDADC3        FALSE

-#define STM32_SDADC3_DMA_MSK    0

-#define STM32_SDADC3_DMA_CHN    0x00000000

+#define STM32_HAS_SDADC1                FALSE

+#define STM32_HAS_SDADC2                FALSE

+#define STM32_HAS_SDADC3                FALSE

 

 /* CAN attributes.*/

-#define STM32_HAS_CAN1          TRUE

-#define STM32_HAS_CAN2          FALSE

-#define STM32_CAN_MAX_FILTERS   14

+#define STM32_HAS_CAN1                  TRUE

+#define STM32_HAS_CAN2                  FALSE

+#define STM32_CAN_MAX_FILTERS           14

 

 /* DAC attributes.*/

-#define STM32_HAS_DAC           TRUE

+#define STM32_HAS_DAC1                  TRUE

+#define STM32_HAS_DAC2                  TRUE

 

 /* DMA attributes.*/

-#define STM32_ADVANCED_DMA      FALSE

-#define STM32_HAS_DMA1          TRUE

-#define STM32_HAS_DMA2          TRUE

+#define STM32_ADVANCED_DMA              FALSE

+#define STM32_HAS_DMA1                  TRUE

+#define STM32_HAS_DMA2                  TRUE

 

 /* ETH attributes.*/

-#define STM32_HAS_ETH           FALSE

+#define STM32_HAS_ETH                   FALSE

 

 /* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS 34

+#define STM32_EXTI_NUM_CHANNELS         34

 

 /* GPIO attributes.*/

-#define STM32_HAS_GPIOA         TRUE

-#define STM32_HAS_GPIOB         TRUE

-#define STM32_HAS_GPIOC         TRUE

-#define STM32_HAS_GPIOD         TRUE

-#define STM32_HAS_GPIOE         TRUE

-#define STM32_HAS_GPIOF         TRUE

-#define STM32_HAS_GPIOG         FALSE

-#define STM32_HAS_GPIOH         FALSE

-#define STM32_HAS_GPIOI         FALSE

+#define STM32_HAS_GPIOA                 TRUE

+#define STM32_HAS_GPIOB                 TRUE

+#define STM32_HAS_GPIOC                 TRUE

+#define STM32_HAS_GPIOD                 TRUE

+#define STM32_HAS_GPIOE                 TRUE

+#define STM32_HAS_GPIOF                 TRUE

+#define STM32_HAS_GPIOG                 FALSE

+#define STM32_HAS_GPIOH                 FALSE

+#define STM32_HAS_GPIOI                 FALSE

 

 /* I2C attributes.*/

-#define STM32_HAS_I2C1          TRUE

-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_I2C1_RX_DMA_CHN   0x00000000

-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_I2C2          TRUE

-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C2_RX_DMA_CHN   0x00000000

-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_I2C2_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_I2C3          FALSE

-#define STM32_I2C3_RX_DMA_MSK   0

-#define STM32_I2C3_RX_DMA_CHN   0x00000000

-#define STM32_I2C3_TX_DMA_MSK   0

-#define STM32_I2C3_TX_DMA_CHN   0x00000000

+#define STM32_HAS_I2C1                  TRUE

+#define STM32_I2C1_RX_DMA_MSK           (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_I2C1_RX_DMA_CHN           0x00000000

+#define STM32_I2C1_TX_DMA_MSK           (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN           0x00000000

+

+#define STM32_HAS_I2C2                  TRUE

+#define STM32_I2C2_RX_DMA_MSK           (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C2_RX_DMA_CHN           0x00000000

+#define STM32_I2C2_TX_DMA_MSK           (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_I2C2_TX_DMA_CHN           0x00000000

+

+#define STM32_HAS_I2C3                  FALSE

+#define STM32_I2C3_RX_DMA_MSK           0

+#define STM32_I2C3_RX_DMA_CHN           0x00000000

+#define STM32_I2C3_TX_DMA_MSK           0

+#define STM32_I2C3_TX_DMA_CHN           0x00000000

 

 /* RTC attributes.*/

-#define STM32_HAS_RTC           TRUE

-#define STM32_RTC_HAS_SUBSECONDS TRUE

-#define STM32_RTC_IS_CALENDAR   TRUE

+#define STM32_HAS_RTC                   TRUE

+#define STM32_RTC_HAS_SUBSECONDS        TRUE

+#define STM32_RTC_IS_CALENDAR           TRUE

 

 /* SDIO attributes.*/

-#define STM32_HAS_SDIO          FALSE

+#define STM32_HAS_SDIO                  FALSE

 

 /* SPI attributes.*/

-#define STM32_HAS_SPI1          TRUE

-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_SPI1_RX_DMA_CHN   0x00000000

-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI1_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_SPI2          TRUE

-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_RX_DMA_CHN   0x00000000

-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_SPI2_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_SPI3          TRUE

-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)

-#define STM32_SPI3_RX_DMA_CHN   0x00000000

-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)

-#define STM32_SPI3_TX_DMA_CHN   0x00000000

+#define STM32_HAS_SPI1                  TRUE

+#define STM32_SPI1_RX_DMA_MSK           STM32_DMA_STREAM_ID_MSK(1, 2)

+#define STM32_SPI1_RX_DMA_CHN           0x00000000

+#define STM32_SPI1_TX_DMA_MSK           STM32_DMA_STREAM_ID_MSK(1, 3)

+#define STM32_SPI1_TX_DMA_CHN           0x00000000

+

+#define STM32_HAS_SPI2                  TRUE

+#define STM32_SPI2_RX_DMA_MSK           STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_SPI2_RX_DMA_CHN           0x00000000

+#define STM32_SPI2_TX_DMA_MSK           STM32_DMA_STREAM_ID_MSK(1, 5)

+#define STM32_SPI2_TX_DMA_CHN           0x00000000

+

+#define STM32_HAS_SPI3                  TRUE

+#define STM32_SPI3_RX_DMA_MSK           STM32_DMA_STREAM_ID_MSK(2, 1)

+#define STM32_SPI3_RX_DMA_CHN           0x00000000

+#define STM32_SPI3_TX_DMA_MSK           STM32_DMA_STREAM_ID_MSK(2, 2)

+#define STM32_SPI3_TX_DMA_CHN           0x00000000

 

 /* TIM attributes.*/

-#define STM32_HAS_TIM1          TRUE

-#define STM32_HAS_TIM2          TRUE

-#define STM32_HAS_TIM3          TRUE

-#define STM32_HAS_TIM4          TRUE

-#define STM32_HAS_TIM5          FALSE

-#define STM32_HAS_TIM6          TRUE

-#define STM32_HAS_TIM7          TRUE

-#define STM32_HAS_TIM8          TRUE

-#define STM32_HAS_TIM9          FALSE

-#define STM32_HAS_TIM10         FALSE

-#define STM32_HAS_TIM11         FALSE

-#define STM32_HAS_TIM12         FALSE

-#define STM32_HAS_TIM13         FALSE

-#define STM32_HAS_TIM14         FALSE

-#define STM32_HAS_TIM15         TRUE

-#define STM32_HAS_TIM16         TRUE

-#define STM32_HAS_TIM17         TRUE

-#define STM32_HAS_TIM18         FALSE

-#define STM32_HAS_TIM19         FALSE

+#define STM32_TIM_MAX_CHANNELS          6

+

+#define STM32_HAS_TIM1                  TRUE

+#define STM32_TIM1_IS_32BITS            FALSE

+#define STM32_TIM1_CHANNELS             6

+

+#define STM32_HAS_TIM2                  TRUE

+#define STM32_TIM2_IS_32BITS            TRUE

+#define STM32_TIM2_CHANNELS             4

+

+#define STM32_HAS_TIM3                  TRUE

+#define STM32_TIM3_IS_32BITS            FALSE

+#define STM32_TIM3_CHANNELS             4

+

+#define STM32_HAS_TIM4                  TRUE

+#define STM32_TIM4_IS_32BITS            FALSE

+#define STM32_TIM4_CHANNELS             4

+

+#define STM32_HAS_TIM6                  TRUE

+#define STM32_TIM6_IS_32BITS            FALSE

+#define STM32_TIM6_CHANNELS             0

+

+#define STM32_HAS_TIM7                  TRUE

+#define STM32_TIM7_IS_32BITS            FALSE

+#define STM32_TIM7_CHANNELS             0

+

+#define STM32_HAS_TIM8                  TRUE

+#define STM32_TIM8_IS_32BITS            FALSE

+#define STM32_TIM8_CHANNELS             6

+

+#define STM32_HAS_TIM15                 TRUE

+#define STM32_TIM15_IS_32BITS           FALSE

+#define STM32_TIM15_CHANNELS            2

+

+#define STM32_HAS_TIM16                 TRUE

+#define STM32_TIM16_IS_32BITS           FALSE

+#define STM32_TIM16_CHANNELS            2

+

+#define STM32_HAS_TIM17                 TRUE

+#define STM32_TIM17_IS_32BITS           FALSE

+#define STM32_TIM17_CHANNELS            2

+

+#define STM32_HAS_TIM5                  FALSE

+#define STM32_HAS_TIM9                  FALSE

+#define STM32_HAS_TIM10                 FALSE

+#define STM32_HAS_TIM11                 FALSE

+#define STM32_HAS_TIM12                 FALSE

+#define STM32_HAS_TIM13                 FALSE

+#define STM32_HAS_TIM14                 FALSE

+#define STM32_HAS_TIM18                 FALSE

+#define STM32_HAS_TIM19                 FALSE

 

 /* USART attributes.*/

-#define STM32_HAS_USART1        TRUE

-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_USART1_RX_DMA_CHN 0x00000000

-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_USART1_TX_DMA_CHN 0x00000000

-

-#define STM32_HAS_USART2        TRUE

-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_USART2_RX_DMA_CHN 0x00000000

-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_USART2_TX_DMA_CHN 0x00000000

-

-#define STM32_HAS_USART3        TRUE

-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_USART3_RX_DMA_CHN 0x00000000

-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_USART3_TX_DMA_CHN 0x00000000

-

-#define STM32_HAS_UART4         FALSE

-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_UART4_RX_DMA_CHN  0x00000000

-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_UART4_TX_DMA_CHN  0x00000000

-

-#define STM32_HAS_UART5         FALSE

-#define STM32_UART5_RX_DMA_MSK  0

-#define STM32_UART5_RX_DMA_CHN  0x00000000

-#define STM32_UART5_TX_DMA_MSK  0

-#define STM32_UART5_TX_DMA_CHN  0x00000000

-

-#define STM32_HAS_USART6        FALSE

-#define STM32_USART6_RX_DMA_MSK 0

-#define STM32_USART6_RX_DMA_CHN 0x00000000

-#define STM32_USART6_TX_DMA_MSK 0

-#define STM32_USART6_TX_DMA_CHN 0x00000000

+#define STM32_HAS_USART1                TRUE

+#define STM32_USART1_RX_DMA_MSK         (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN         0x00000000

+#define STM32_USART1_TX_DMA_MSK         (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN         0x00000000

+

+#define STM32_HAS_USART2                TRUE

+#define STM32_USART2_RX_DMA_MSK         (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN         0x00000000

+#define STM32_USART2_TX_DMA_MSK         (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN         0x00000000

+

+#define STM32_HAS_USART3                TRUE

+#define STM32_USART3_RX_DMA_MSK         (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_USART3_RX_DMA_CHN         0x00000000

+#define STM32_USART3_TX_DMA_MSK         (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_USART3_TX_DMA_CHN         0x00000000

+

+#define STM32_HAS_UART4                 TRUE

+#define STM32_UART4_RX_DMA_MSK          (STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_UART4_RX_DMA_CHN          0x00000000

+#define STM32_UART4_TX_DMA_MSK          (STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_UART4_TX_DMA_CHN          0x00000000

+

+#define STM32_HAS_UART5                 TRUE

+#define STM32_UART5_RX_DMA_MSK          0

+#define STM32_UART5_RX_DMA_CHN          0x00000000

+#define STM32_UART5_TX_DMA_MSK          0

+#define STM32_UART5_TX_DMA_CHN          0x00000000

+

+#define STM32_HAS_USART6                FALSE

+#define STM32_USART6_RX_DMA_MSK         0

+#define STM32_USART6_RX_DMA_CHN         0x00000000

+#define STM32_USART6_TX_DMA_MSK         0

+#define STM32_USART6_TX_DMA_CHN         0x00000000

 

 /* USB attributes.*/

-#define STM32_HAS_USB           TRUE

-#define STM32_HAS_OTG1          FALSE

-#define STM32_HAS_OTG2          FALSE

+#define STM32_HAS_USB                   TRUE

+#define STM32_HAS_OTG1                  FALSE

+#define STM32_HAS_OTG2                  FALSE

 /** @} */

 

 #endif /* _STM32_REGISTRY_H_ */