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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-23 14:34:26 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-09-23 14:34:26 +0000 |
| commit | c27b36536a3e9c98bceedb61efad185ebe836dad (patch) | |
| tree | fc1696a3913da5613380402d0ec17fe099f98504 /os | |
| parent | d749f21cb98b373a93140f9a3723525ddfd92447 (diff) | |
| download | ChibiOS-c27b36536a3e9c98bceedb61efad185ebe836dad.tar.gz ChibiOS-c27b36536a3e9c98bceedb61efad185ebe836dad.tar.bz2 ChibiOS-c27b36536a3e9c98bceedb61efad185ebe836dad.zip | |
Modified USARTv2 to support HW FIFOs where present.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12288 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c | 42 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h | 2 |
2 files changed, 30 insertions, 14 deletions
diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c index 8a4d20865..6c2b855af 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c @@ -338,25 +338,41 @@ static void serve_interrupt(SerialDriver *sdp) { osalSysUnlockFromISR();
}
- /* Data available.*/
- if (isr & USART_ISR_RXNE) {
+ /* Data available, note it is a while in order to handle two situations:
+ 1) Another byte arrived after removing the previous one, this would cause
+ an extra interrupt to serve.
+ 2) FIFO mode is enabled on devices that support it, we need to empty
+ the FIFO.*/
+ while (isr & USART_ISR_RXNE) {
osalSysLockFromISR();
sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
osalSysUnlockFromISR();
+
+ isr = u->ISR;
}
- /* Transmission buffer empty.*/
- if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
- msg_t b;
- osalSysLockFromISR();
- b = oqGetI(&sdp->oqueue);
- if (b < MSG_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- u->CR1 = cr1 & ~USART_CR1_TXEIE;
- }
- else
+ /* Transmission buffer empty, note it is a while in order to handle two
+ situations:
+ 1) The data registers has been emptied immediately after writing it, this
+ would cause an extra interrupt to serve.
+ 2) FIFO mode is enabled on devices that support it, we need to fill
+ the FIFO.*/
+ if (cr1 & USART_CR1_TXEIE) {
+ while (isr & USART_ISR_TXE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ if (b < MSG_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ u->CR1 = cr1 & ~USART_CR1_TXEIE;
+ break;
+ }
u->TDR = b;
- osalSysUnlockFromISR();
+ osalSysUnlockFromISR();
+
+ isr = u->ISR;
+ }
}
/* Physical transmission end.*/
diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h index 79864d808..11813b44a 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h @@ -428,7 +428,7 @@ #endif /* !defined(STM32_USART3_8_HANDLER) */
-#if STM32_SERIAL_USE_LPUART1 && \
+#if STM32_SERIAL_USE_LPUART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY)
#error "Invalid IRQ priority assigned to LPUART1"
#endif
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