diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 12:34:59 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-14 12:34:59 +0000 |
| commit | 126943984c591c952bd0b9f6b2d36d97be823de3 (patch) | |
| tree | ba80c46171dcc1e34bbd0110edb0cca645bd50ed /testhal/SPC563Mxx/ADC/mcuconf.h | |
| parent | f0e62eb4b588d8b2fbf858efb7b41226a2424d81 (diff) | |
| download | ChibiOS-126943984c591c952bd0b9f6b2d36d97be823de3.tar.gz ChibiOS-126943984c591c952bd0b9f6b2d36d97be823de3.tar.bz2 ChibiOS-126943984c591c952bd0b9f6b2d36d97be823de3.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5848 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/SPC563Mxx/ADC/mcuconf.h')
| -rw-r--r-- | testhal/SPC563Mxx/ADC/mcuconf.h | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h index 49ae96bab..db7cfabb1 100644 --- a/testhal/SPC563Mxx/ADC/mcuconf.h +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -23,6 +23,8 @@ *
* IRQ priorities:
* 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
*/
#define SPC563Mxx_MCUCONF
@@ -45,6 +47,25 @@ BIUCR_BFEN)
/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO 2
+#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
+
+/*
* ADC driver settings.
*/
#define SPC5_ADC_USE_ADC0_Q0 TRUE
@@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 TRUE
#define SPC5_ADC_USE_ADC1_Q4 TRUE
#define SPC5_ADC_USE_ADC1_Q5 TRUE
-#define SPC5_ADC_FIFO0_DMA_PRIO 12
-#define SPC5_ADC_FIFO1_DMA_PRIO 12
-#define SPC5_ADC_FIFO2_DMA_PRIO 12
-#define SPC5_ADC_FIFO3_DMA_PRIO 12
-#define SPC5_ADC_FIFO4_DMA_PRIO 12
-#define SPC5_ADC_FIFO5_DMA_PRIO 12
#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
@@ -104,8 +119,6 @@ SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO 10
-#define SPC5_SPI_DSPI2_DMA_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|