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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-07 11:03:10 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-03-07 11:03:10 +0000 |
| commit | 1d6fc52f437be05281f46ceb25d084a786a4d9a2 (patch) | |
| tree | 25919c4d1df1e2f48377ddb421502e9ed4e33a95 /testhal/SPC563Mxx/ADC/mcuconf.h | |
| parent | 79633162a0b534e544dd188423dc86107d80d9a9 (diff) | |
| download | ChibiOS-1d6fc52f437be05281f46ceb25d084a786a4d9a2.tar.gz ChibiOS-1d6fc52f437be05281f46ceb25d084a786a4d9a2.tar.bz2 ChibiOS-1d6fc52f437be05281f46ceb25d084a786a4d9a2.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5374 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/SPC563Mxx/ADC/mcuconf.h')
| -rw-r--r-- | testhal/SPC563Mxx/ADC/mcuconf.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h new file mode 100644 index 000000000..bca85fb65 --- /dev/null +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -0,0 +1,62 @@ +/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * SPC563Mxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ */
+
+#define SPC563Mxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT FALSE
+#define SPC5_CLK_BYPASS FALSE
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#define SPC5_CLK_PREDIV_VALUE 2
+#define SPC5_CLK_MFD_VALUE 80
+#define SPC5_CLK_RFD SPC5_RFD_DIV4
+#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
+ BIUCR_MASTER4_PREFETCH | \
+ BIUCR_MASTER0_PREFETCH | \
+ BIUCR_DPFEN | \
+ BIUCR_IPFEN | \
+ BIUCR_PFLIM_ON_MISS | \
+ BIUCR_BFEN)
+
+/*
+ * ADC driver settings.
+ */
+#define SPC5_ADC_USE_ADC0_Q0 TRUE
+#define SPC5_ADC_USE_ADC0_Q1 TRUE
+#define SPC5_ADC_USE_ADC0_Q2 TRUE
+#define SPC5_ADC_USE_ADC1_Q3 TRUE
+#define SPC5_ADC_USE_ADC1_Q4 TRUE
+#define SPC5_ADC_USE_ADC1_Q5 TRUE
+#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_USE_ESCIA TRUE
+#define SPC5_USE_ESCIB TRUE
+#define SPC5_ESCIA_PRIORITY 8
+#define SPC5_ESCIB_PRIORITY 8
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