diff options
| -rw-r--r-- | os/io/platforms/STM32/spi_lld.c | 4 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/nvic.c | 1 | ||||
| -rw-r--r-- | readme.txt | 2 |
3 files changed, 5 insertions, 2 deletions
diff --git a/os/io/platforms/STM32/spi_lld.c b/os/io/platforms/STM32/spi_lld.c index 99285d0e2..598e0fd5b 100644 --- a/os/io/platforms/STM32/spi_lld.c +++ b/os/io/platforms/STM32/spi_lld.c @@ -207,17 +207,17 @@ void spi_lld_start(SPIDriver *spip) { if (spip->spd_state == SPI_STOP) {
#if USE_STM32_SPI1
if (&SPID1 == spip) {
+ dmaEnable(DMA1_ID);
NVICEnableVector(DMA1_Channel2_IRQn, STM32_SPI1_IRQ_PRIORITY);
NVICEnableVector(DMA1_Channel3_IRQn, STM32_SPI1_IRQ_PRIORITY);
- dmaEnable(DMA1_ID);
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
}
#endif
#if USE_STM32_SPI2
if (&SPID2 == spip) {
+ dmaEnable(DMA1_ID);
NVICEnableVector(DMA1_Channel4_IRQn, STM32_SPI2_IRQ_PRIORITY);
NVICEnableVector(DMA1_Channel5_IRQn, STM32_SPI2_IRQ_PRIORITY);
- dmaEnable(DMA1_ID);
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
}
#endif
diff --git a/os/ports/GCC/ARMCM3/nvic.c b/os/ports/GCC/ARMCM3/nvic.c index c34aaf4ea..e61637848 100644 --- a/os/ports/GCC/ARMCM3/nvic.c +++ b/os/ports/GCC/ARMCM3/nvic.c @@ -39,6 +39,7 @@ void NVICEnableVector(uint32_t n, uint32_t prio) { unsigned sh = (n & 3) << 3;
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
+ NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
}
diff --git a/readme.txt b/readme.txt index f4e150977..2921ff6f2 100644 --- a/readme.txt +++ b/readme.txt @@ -3,6 +3,8 @@ *****************************************************************************
*** 1.3.5 ***
+- CHANGE: In the Cortex-M3 port, modified the NVICEnableVector() function
+ to make it clear pending interrupts.
*** 1.3.4 ***
- FIX: Fixed bug in STM32 PAL port driver (bug 2897636).
|