diff options
Diffstat (limited to 'os/common')
70 files changed, 11047 insertions, 0 deletions
diff --git a/os/common/ports/ARMCMx/compilers/GCC/crt0.c b/os/common/ports/ARMCMx/compilers/GCC/crt0.c new file mode 100644 index 000000000..31437a35e --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/crt0.c @@ -0,0 +1,354 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/GCC/crt0.c
+ * @brief Generic GCC Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_GCC_STARTUP
+ * @{
+ */
+
+#include <stdint.h>
+
+#if !defined(FALSE)
+#define FALSE 0
+#endif
+
+#if !defined(TRUE)
+#define TRUE (!FALSE)
+#endif
+
+#define SCB_CPACR *((uint32_t *)0xE000ED88U)
+#define SCB_FPCCR *((uint32_t *)0xE000EF34U)
+#define SCB_FPDSCR *((uint32_t *)0xE000EF3CU)
+#define FPCCR_ASPEN (0x1U << 31)
+#define FPCCR_LSPEN (0x1U << 30)
+
+typedef void (*funcp_t)(void);
+typedef funcp_t * funcpp_t;
+
+#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+
+/*
+ * Area fill code, it is a macro because here functions cannot be called
+ * until stacks are initialized.
+ */
+#define fill32(start, end, filler) { \
+ uint32_t *p1 = (start); \
+ uint32_t *p2 = (end); \
+ while (p1 < p2) \
+ *p1++ = (filler); \
+}
+
+/*===========================================================================*/
+/**
+ * @name Startup settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Control special register initialization value.
+ * @details The system is setup to run in privileged mode using the PSP
+ * stack (dual stack mode).
+ */
+#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
+#define CRT0_CONTROL_INIT 0x00000002
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
+#define CRT0_STACKS_FILL_PATTERN 0x55555555
+#endif
+
+/**
+ * @brief Stack segments initialization switch.
+ */
+#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
+#define CRT0_INIT_STACKS TRUE
+#endif
+
+/**
+ * @brief DATA segment initialization switch.
+ */
+#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
+#define CRT0_INIT_DATA TRUE
+#endif
+
+/**
+ * @brief BSS segment initialization switch.
+ */
+#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
+#define CRT0_INIT_BSS TRUE
+#endif
+
+/**
+ * @brief Constructors invocation switch.
+ */
+#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_CONSTRUCTORS TRUE
+#endif
+
+/**
+ * @brief Destructors invocation switch.
+ */
+#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
+#define CRT0_CALL_DESTRUCTORS TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Symbols from the scatter file
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Main stack lower boundary.
+ * @details This symbol must be exported by the linker script and represents
+ * the main stack lower boundary.
+ */
+extern uint32_t __main_stack_base__;
+
+/**
+ *
+ * @brief Main stack initial position.
+ * @details This symbol must be exported by the linker script and represents
+ * the main stack initial position.
+ */
+extern uint32_t __main_stack_end__;
+
+/**
+ * @brief Process stack lower boundary.
+ * @details This symbol must be exported by the linker script and represents
+ * the process stack lower boundary.
+ */
+extern uint32_t __process_stack_base__;
+
+/**
+ * @brief Process stack initial position.
+ * @details This symbol must be exported by the linker script and represents
+ * the process stack initial position.
+ */
+extern uint32_t __process_stack_end__;
+
+/**
+ * @brief ROM image of the data segment start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _textdata;
+
+/**
+ * @brief Data segment start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _data;
+
+/**
+ * @brief Data segment end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _edata;
+
+/**
+ * @brief BSS segment start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _bss_start;
+
+/**
+ * @brief BSS segment end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern uint32_t _bss_end;
+
+/**
+ * @brief Constructors table start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __init_array_start;
+
+/**
+ * @brief Constructors table end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __init_array_end;
+
+/**
+ * @brief Destructors table start.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __fini_array_start;
+
+/**
+ * @brief Destructors table end.
+ * @pre The symbol must be aligned to a 32 bits boundary.
+ */
+extern funcp_t __fini_array_end;
+
+/** @} */
+
+/**
+ * @brief Application @p main() function.
+ */
+extern void main(void);
+
+/**
+ * @brief Early initialization.
+ * @details This hook is invoked immediately after the stack initialization
+ * and before the DATA and BSS segments initialization. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+void __early_init(void) {}
+
+/**
+ * @brief Late initialization.
+ * @details This hook is invoked after the DATA and BSS segments
+ * initialization and before any static constructor. The
+ * default behavior is to do nothing.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((weak))
+#endif
+void __late_init(void) {}
+
+/**
+ * @brief Default @p main() function exit handler.
+ * @details This handler is invoked or the @p main() function exit. The
+ * default behavior is to enter an infinite loop.
+ * @note This function is a weak symbol.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((noreturn, weak))
+#endif
+void _default_exit(void) {
+ while (1)
+ ;
+}
+
+/**
+ * @brief Reset vector.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__((naked))
+#endif
+void Reset_Handler(void) {
+ uint32_t psp, reg;
+
+ /* Process Stack initialization, it is allocated starting from the
+ symbol __process_stack_end__ and its lower limit is the symbol
+ __process_stack_base__.*/
+ asm volatile ("cpsid i");
+ psp = SYMVAL(__process_stack_end__);
+ asm volatile ("msr PSP, %0" : : "r" (psp));
+
+#if CORTEX_USE_FPU
+ /* Initializing the FPU context save in lazy mode.*/
+ SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
+
+ /* CP10 and CP11 set to full access.*/
+ SCB_CPACR |= 0x00F00000;
+
+ /* FPSCR and FPDSCR initially zero.*/
+ reg = 0;
+ asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
+ SCB_FPDSCR = reg;
+
+ /* CPU mode initialization, enforced FPCA bit.*/
+ reg = CRT0_CONTROL_INIT | 4;
+#else
+ /* CPU mode initialization.*/
+ reg = CRT0_CONTROL_INIT;
+#endif
+ asm volatile ("msr CONTROL, %0" : : "r" (reg));
+ asm volatile ("isb");
+
+#if CRT0_INIT_STACKS
+ /* Main and Process stacks initialization.*/
+ fill32(&__main_stack_base__,
+ &__main_stack_end__,
+ CRT0_STACKS_FILL_PATTERN);
+ fill32(&__process_stack_base__,
+ &__process_stack_end__,
+ CRT0_STACKS_FILL_PATTERN);
+#endif
+
+ /* Early initialization hook invocation.*/
+ __early_init();
+
+#if CRT0_INIT_DATA
+ /* DATA segment initialization.*/
+ {
+ uint32_t *tp, *dp;
+
+ tp = &_textdata;
+ dp = &_data;
+ while (dp < &_edata)
+ *dp++ = *tp++;
+ }
+#endif
+
+#if CRT0_INIT_BSS
+ /* BSS segment initialization.*/
+ fill32(&_bss_start, &_bss_end, 0);
+#endif
+
+ /* Late initialization hook invocation.*/
+ __late_init();
+
+#if CRT0_CALL_CONSTRUCTORS
+ /* Constructors invocation.*/
+ {
+ funcpp_t fpp = &__init_array_start;
+ while (fpp < &__init_array_end) {
+ (*fpp)();
+ fpp++;
+ }
+ }
+#endif
+
+ /* Invoking application main() function.*/
+ main();
+
+#if CRT0_CALL_DESTRUCTORS
+ /* Destructors invocation.*/
+ {
+ funcpp_t fpp = &__fini_array_start;
+ while (fpp < &__fini_array_end) {
+ (*fpp)();
+ fpp++;
+ }
+ }
+#endif
+
+ /* Invoking the exit handler.*/
+ _default_exit();
+}
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld new file mode 100644 index 000000000..8e359d55d --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F051x8 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 64k
+ ram : org = 0x20000000, len = 8k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld new file mode 100644 index 000000000..8cc0980b3 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F100xB.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F100xB memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 128k
+ ram : org = 0x20000000, len = 8k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld new file mode 100644 index 000000000..f5b69dae1 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xB.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xB memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 128k
+ ram : org = 0x20000000, len = 20k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld new file mode 100644 index 000000000..030dab33c --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xD.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 384k
+ ram : org = 0x20000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld new file mode 100644 index 000000000..96e2fea12 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xE.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xE memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 512k
+ ram : org = 0x20000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld new file mode 100644 index 000000000..091c95471 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F103xG.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F103xG memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 1m
+ ram : org = 0x20000000, len = 96k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld new file mode 100644 index 000000000..f4292b894 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F107xC.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F107xC memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 256k
+ ram : org = 0x20000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld new file mode 100644 index 000000000..efa0d6250 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F303xC memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 256k
+ ram : org = 0x20000000, len = 40k
+ ccmram : org = 0x10000000, len = 8k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld new file mode 100644 index 000000000..82f8b38aa --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F373xC memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 256k
+ ram : org = 0x20000000, len = 32k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld new file mode 100644 index 000000000..1433b8269 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld @@ -0,0 +1,28 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F405xG memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 1M
+ ram : org = 0x20000000, len = 112k
+ ethram : org = 0x2001C000, len = 16k
+ ccmram : org = 0x10000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld new file mode 100644 index 000000000..610c3e1f8 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld @@ -0,0 +1,28 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F407xG memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 1M
+ ram : org = 0x20000000, len = 112k
+ ethram : org = 0x2001C000, len = 16k
+ ccmram : org = 0x10000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld new file mode 100644 index 000000000..d918b6f0f --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F429xI.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * ST32F429xI memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 2M
+ ram : org = 0x20000000, len = 192k
+ ccmram : org = 0x10000000, len = 64k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld new file mode 100644 index 000000000..a09ef86fa --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L152xB memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x08000000, len = 128k
+ ram : org = 0x20000000, len = 16k
+}
+
+INCLUDE rules.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/rules.ld b/os/common/ports/ARMCMx/compilers/GCC/rules.ld new file mode 100644 index 000000000..f06c4ae6b --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/rules.ld @@ -0,0 +1,137 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_start__ = ORIGIN(ram);
+__ram_size__ = LENGTH(ram);
+__ram_end__ = __ram_start__ + __ram_size__;
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ . = 0;
+ _text = .;
+
+ startup : ALIGN(16) SUBALIGN(16)
+ {
+ KEEP(*(vectors))
+ } > flash
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text.startup.*)
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ .ARM.exidx : {
+ PROVIDE(__exidx_start = .);
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ PROVIDE(__exidx_end = .);
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .textalign : ONLY_IF_RO
+ {
+ . = ALIGN(8);
+ } > flash
+
+ . = ALIGN(4);
+ _etext = .;
+ _textdata = _etext;
+
+ .stacks :
+ {
+ . = ALIGN(8);
+ __main_stack_base__ = .;
+ . += __main_stack_size__;
+ . = ALIGN(8);
+ __main_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data = .);
+ *(.data)
+ . = ALIGN(4);
+ *(.data.*)
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ PROVIDE(_edata = .);
+ } > ram AT > flash
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE(_bss_start = .);
+ *(.bss)
+ . = ALIGN(4);
+ *(.bss.*)
+ . = ALIGN(4);
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE(_bss_end = .);
+ } > ram
+}
+
+PROVIDE(end = .);
+_end = .;
+
+__heap_base__ = _end;
+__heap_end__ = __ram_end__;
diff --git a/os/common/ports/ARMCMx/compilers/GCC/rules.mk b/os/common/ports/ARMCMx/compilers/GCC/rules.mk new file mode 100644 index 000000000..e0eaf343d --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/rules.mk @@ -0,0 +1,266 @@ +# ARM Cortex-Mx common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := ,--gc-sections
+else
+ LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# FPU-related options
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+ifneq ($(USE_FPU),no)
+ OPT += -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+ DADEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+ DADEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__main_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).bin $(BUILDDIR)/$(PROJECT).dmp
+
+# Source files groups and paths
+ifeq ($(USE_THUMB),yes)
+ TCSRC += $(CSRC)
+ TCPPSRC += $(CPPSRC)
+else
+ ACSRC += $(CSRC)
+ ACPPSRC += $(CPPSRC)
+endif
+ASRC = $(ACSRC)$(ACPPSRC)
+TSRC = $(TCSRC)$(TCPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+ACOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACSRC:.c=.o)))
+ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o)))
+TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
+TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS = -mcpu=$(MCU)
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT)
+
+# Thumb interwork enabled only if needed because it kills performance.
+ifneq ($(TSRC),)
+ CFLAGS += -DTHUMB_PRESENT
+ CPPFLAGS += -DTHUMB_PRESENT
+ ASFLAGS += -DTHUMB_PRESENT
+ ifneq ($(ASRC),)
+ # Mixed ARM and THUMB mode.
+ CFLAGS += -mthumb-interwork
+ CPPFLAGS += -mthumb-interwork
+ ASFLAGS += -mthumb-interwork
+ LDFLAGS += -mthumb-interwork
+ else
+ # Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
+ CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+ CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
+ ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
+ LDFLAGS += -mno-thumb-interwork -mthumb
+ endif
+else
+ # Pure ARM mode
+ CFLAGS += -mno-thumb-interwork
+ CPPFLAGS += -mno-thumb-interwork
+ ASFLAGS += -mno-thumb-interwork
+ LDFLAGS += -mno-thumb-interwork
+endif
+
+# Generate dependency information
+CFLAGS += -MD -MP -MF .dep/$(@F).d
+CPPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
+
+MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | $(BUILDDIR)
+
+$(BUILDDIR) $(OBJDIR) $(LSTDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ mkdir -p $(OBJDIR)
+ mkdir -p $(LSTDIR)
+
+$(ACPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ACOBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) $(AOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(TCOBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
+%.elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< $@
+else
+ @echo Creating $@
+ @$(HEX) $< $@
+endif
+
+%.bin: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< $@
+else
+ @echo Creating $@
+ @$(BIN) $< $@
+endif
+
+%.dmp: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $<
+ @echo
+ @echo Done
+endif
+
+clean:
+ @echo Cleaning
+ -rm -fR .dep $(BUILDDIR)
+ @echo
+ @echo Done
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/os/common/ports/ARMCMx/compilers/GCC/vectors.c b/os/common/ports/ARMCMx/compilers/GCC/vectors.c new file mode 100644 index 000000000..252071854 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/vectors.c @@ -0,0 +1,653 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/GCC/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "cmparams.h"
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+/**
+ * @brief Type of an IRQ vector.
+ */
+typedef void (*irq_vector_t)(void);
+
+/**
+ * @brief Type of a structure representing the whole vectors table.
+ */
+typedef struct {
+ uint32_t *init_stack;
+ irq_vector_t reset_handler;
+ irq_vector_t nmi_handler;
+ irq_vector_t hardfault_handler;
+ irq_vector_t memmanage_handler;
+ irq_vector_t busfault_handler;
+ irq_vector_t usagefault_handler;
+ irq_vector_t vector1c;
+ irq_vector_t vector20;
+ irq_vector_t vector24;
+ irq_vector_t vector28;
+ irq_vector_t svc_handler;
+ irq_vector_t debugmonitor_handler;
+ irq_vector_t vector34;
+ irq_vector_t pendsv_handler;
+ irq_vector_t systick_handler;
+ irq_vector_t vectors[CORTEX_NUM_VECTORS];
+} vectors_t;
+
+/**
+ * @brief Unhandled exceptions handler.
+ * @details Any undefined exception vector points to this function by default.
+ * This function simply stops the system into an infinite loop.
+ *
+ * @notapi
+ */
+void _unhandled_exception(void) {
+
+ while (true)
+ ;
+}
+
+#if !defined(__DOXYGEN__)
+extern uint32_t __main_stack_end__;
+void Reset_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void NMI_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void HardFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void MemManage_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void BusFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void UsageFault_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
+void SVC_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void DebugMon_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
+void PendSV_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void SysTick_Handler(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
+#if CORTEX_NUM_VECTORS > 4
+void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 8
+void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 12
+void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 16
+void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 20
+void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 24
+void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 28
+void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 32
+void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 36
+void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 40
+void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 44
+void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
+void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 48
+void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 52
+void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 56
+void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 60
+void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 64
+void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 68
+void Vector150(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector154(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector158(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector15C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 72
+void Vector160(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector164(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector168(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector16C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 76
+void Vector170(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector174(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector178(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector17C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 80
+void Vector180(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector184(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector188(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector18C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 84
+void Vector190(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector194(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector198(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector19C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 88
+void Vector1A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 92
+void Vector1B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 96
+void Vector1C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 100
+void Vector1D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 104
+void Vector1E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 108
+void Vector1F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector1FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 112
+void Vector200(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector204(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector208(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector20C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 116
+void Vector210(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector214(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector218(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector21C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 120
+void Vector220(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector224(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector228(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector22C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 124
+void Vector230(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector234(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector238(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector23C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 128
+void Vector240(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector244(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector248(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector24C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 132
+void Vector250(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector254(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector258(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector25C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 136
+void Vector260(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector264(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector268(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector26C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 140
+void Vector270(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector274(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector278(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector27C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 144
+void Vector280(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector284(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector288(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector28C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 148
+void Vector290(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector294(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector298(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector29C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 152
+void Vector2A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 156
+void Vector2B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 160
+void Vector2C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 164
+void Vector2D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 168
+void Vector2E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 172
+void Vector2F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector2FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 176
+void Vector300(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector304(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector308(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector30C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 180
+void Vector310(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector314(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector318(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector31C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 184
+void Vector320(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector324(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector328(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector32C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 188
+void Vector330(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector334(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector338(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector33C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 192
+void Vector340(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector344(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector348(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector34C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 196
+void Vector350(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector354(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector358(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector35C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 200
+void Vector360(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector364(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector368(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector36C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 204
+void Vector370(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector374(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector378(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector37C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 208
+void Vector380(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector384(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector388(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector38C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 212
+void Vector390(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector394(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector398(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector39C(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 216
+void Vector3A0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3A4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3A8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3AC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 220
+void Vector3B0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3B4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3B8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3BC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 224
+void Vector3C0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3C4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3C8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3CC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 228
+void Vector3D0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3D4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3D8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3DC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 232
+void Vector3E0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3E4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3E8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3EC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#if CORTEX_NUM_VECTORS > 236
+void Vector3F0(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3F4(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3F8(void) __attribute__((weak, alias("_unhandled_exception")));
+void Vector3FC(void) __attribute__((weak, alias("_unhandled_exception")));
+#endif
+#endif /* !defined(__DOXYGEN__) */
+
+/**
+ * @brief STM32 vectors table.
+ */
+#if !defined(__DOXYGEN__)
+__attribute__ ((used, section("vectors")))
+#endif
+vectors_t _vectors = {
+ &__main_stack_end__,Reset_Handler, NMI_Handler, HardFault_Handler,
+ MemManage_Handler, BusFault_Handler, UsageFault_Handler, Vector1C,
+ Vector20, Vector24, Vector28, SVC_Handler,
+ DebugMon_Handler, Vector34, PendSV_Handler, SysTick_Handler,
+ {
+ Vector40, Vector44, Vector48, Vector4C,
+#if CORTEX_NUM_VECTORS > 4
+ Vector50, Vector54, Vector58, Vector5C,
+#endif
+#if CORTEX_NUM_VECTORS > 8
+ Vector60, Vector64, Vector68, Vector6C,
+#endif
+#if CORTEX_NUM_VECTORS > 12
+ Vector70, Vector74, Vector78, Vector7C,
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ Vector80, Vector84, Vector88, Vector8C,
+#endif
+#if CORTEX_NUM_VECTORS > 20
+ Vector90, Vector94, Vector98, Vector9C,
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ VectorA0, VectorA4, VectorA8, VectorAC,
+#endif
+#if CORTEX_NUM_VECTORS > 28
+ VectorB0, VectorB4, VectorB8, VectorBC,
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ VectorC0, VectorC4, VectorC8, VectorCC,
+#endif
+#if CORTEX_NUM_VECTORS > 36
+ VectorD0, VectorD4, VectorD8, VectorDC,
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ VectorE0, VectorE4, VectorE8, VectorEC,
+#endif
+#if CORTEX_NUM_VECTORS > 44
+ VectorF0, VectorF4, VectorF8, VectorFC,
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ Vector100, Vector104, Vector108, Vector10C,
+#endif
+#if CORTEX_NUM_VECTORS > 52
+ Vector110, Vector114, Vector118, Vector11C,
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ Vector120, Vector124, Vector128, Vector12C,
+#endif
+#if CORTEX_NUM_VECTORS > 60
+ Vector130, Vector134, Vector138, Vector13C,
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ Vector140, Vector144, Vector148, Vector14C,
+#endif
+#if CORTEX_NUM_VECTORS > 68
+ Vector150, Vector154, Vector158, Vector15C,
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ Vector160, Vector164, Vector168, Vector16C,
+#endif
+#if CORTEX_NUM_VECTORS > 76
+ Vector170, Vector174, Vector178, Vector17C,
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ Vector180, Vector184, Vector188, Vector17C,
+#endif
+#if CORTEX_NUM_VECTORS > 84
+ Vector190, Vector194, Vector198, Vector19C,
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ Vector1A0, Vector1A4, Vector1A8, Vector1AC,
+#endif
+#if CORTEX_NUM_VECTORS > 92
+ Vector1B0, Vector1B4, Vector1B8, Vector1BC,
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ Vector1C0, Vector1C4, Vector1C8, Vector1CC,
+#endif
+#if CORTEX_NUM_VECTORS > 100
+ Vector1D0, Vector1D4, Vector1D8, Vector1DC,
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ Vector1E0, Vector1E4, Vector1E8, Vector1EC,
+#endif
+#if CORTEX_NUM_VECTORS > 108
+ Vector1F0, Vector1F4, Vector1F8, Vector1FC,
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ Vector200, Vector204, Vector208, Vector20C,
+#endif
+#if CORTEX_NUM_VECTORS > 116
+ Vector210, Vector214, Vector218, Vector21C,
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ Vector220, Vector224, Vector228, Vector22C,
+#endif
+#if CORTEX_NUM_VECTORS > 124
+ Vector230, Vector234, Vector238, Vector23C,
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ Vector240, Vector244, Vector248, Vector24C,
+#endif
+#if CORTEX_NUM_VECTORS > 132
+ Vector250, Vector254, Vector258, Vector25C,
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ Vector260, Vector264, Vector268, Vector26C,
+#endif
+#if CORTEX_NUM_VECTORS > 140
+ Vector270, Vector274, Vector278, Vector27C,
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ Vector280, Vector284, Vector288, Vector28C,
+#endif
+#if CORTEX_NUM_VECTORS > 148
+ Vector290, Vector294, Vector298, Vector29C,
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ Vector2A0, Vector2A4, Vector2A8, Vector2AC,
+#endif
+#if CORTEX_NUM_VECTORS > 156
+ Vector2B0, Vector2B4, Vector2B8, Vector2BC,
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ Vector2C0, Vector2C4, Vector2C8, Vector2CC,
+#endif
+#if CORTEX_NUM_VECTORS > 164
+ Vector2D0, Vector2D4, Vector2D8, Vector2DC,
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ Vector2E0, Vector2E4, Vector2E8, Vector2EC,
+#endif
+#if CORTEX_NUM_VECTORS > 172
+ Vector2F0, Vector2F4, Vector2F8, Vector2FC,
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ Vector300, Vector304, Vector308, Vector30C,
+#endif
+#if CORTEX_NUM_VECTORS > 180
+ Vector310, Vector314, Vector318, Vector31C,
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ Vector320, Vector324, Vector328, Vector32C,
+#endif
+#if CORTEX_NUM_VECTORS > 188
+ Vector330, Vector334, Vector338, Vector33C,
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ Vector340, Vector344, Vector348, Vector34C,
+#endif
+#if CORTEX_NUM_VECTORS > 196
+ Vector350, Vector354, Vector358, Vector35C,
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ Vector360, Vector364, Vector368, Vector36C,
+#endif
+#if CORTEX_NUM_VECTORS > 204
+ Vector370, Vector374, Vector378, Vector37C,
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ Vector380, Vector384, Vector388, Vector38C,
+#endif
+#if CORTEX_NUM_VECTORS > 212
+ Vector390, Vector394, Vector398, Vector39C,
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ Vector3A0, Vector3A4, Vector3A8, Vector3AC,
+#endif
+#if CORTEX_NUM_VECTORS > 220
+ Vector3B0, Vector3B4, Vector3B8, Vector3BC,
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ Vector3C0, Vector3C4, Vector3C8, Vector3CC,
+#endif
+#if CORTEX_NUM_VECTORS > 228
+ Vector3D0, Vector3D4, Vector3D8, Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ Vector3E0, Vector3E4, Vector3E8, Vector3EC
+#endif
+#if CORTEX_NUM_VECTORS > 236
+ Vector3F0, Vector3F4, Vector3F8, Vector3FC
+#endif
+ }
+};
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/compilers/IAR/cstartup.s b/os/common/ports/ARMCMx/compilers/IAR/cstartup.s new file mode 100644 index 000000000..b64f7e2a1 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/IAR/cstartup.s @@ -0,0 +1,82 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/IAR/cstartup.s
+ * @brief Generic IAR Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_IAR_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+ MODULE ?cstartup
+
+CONTROL_MODE_PRIVILEGED SET 0
+CONTROL_MODE_UNPRIVILEGED SET 1
+CONTROL_USE_MSP SET 0
+CONTROL_USE_PSP SET 2
+
+ AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
+ PRESERVE8
+
+ SECTION .intvec:CODE:NOROOT(3)
+
+ SECTION CSTACK:DATA:NOROOT(3)
+ PUBLIC __main_thread_stack_base__
+__main_thread_stack_base__:
+ PUBLIC __heap_end__
+__heap_end__:
+
+ SECTION SYSHEAP:DATA:NOROOT(3)
+ PUBLIC __heap_base__
+__heap_base__:
+
+ PUBLIC __iar_program_start
+ EXTERN __vector_table
+ EXTWEAK __iar_init_core
+ EXTWEAK __iar_init_vfp
+ EXTERN __cmain
+
+ SECTION .text:CODE:REORDER(2)
+ REQUIRE __vector_table
+ THUMB
+__iar_program_start:
+ cpsid i
+ ldr r0, =SFE(CSTACK)
+ msr PSP, r0
+ movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
+ msr CONTROL, r0
+ isb
+ bl __early_init
+ bl __iar_init_core
+ bl __iar_init_vfp
+ b __cmain
+
+ PUBWEAK __early_init
+__early_init:
+ bx lr
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/compilers/IAR/vectors.s b/os/common/ports/ARMCMx/compilers/IAR/vectors.s new file mode 100644 index 000000000..133f63217 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/IAR/vectors.s @@ -0,0 +1,1010 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/IAR/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_IAR_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+ MODULE ?vectors
+
+ AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
+ PRESERVE8
+
+ SECTION IRQSTACK:DATA:NOROOT(3)
+ SECTION .intvec:CODE:NOROOT(3)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+
+__vector_table:
+ DCD SFE(IRQSTACK)
+ DCD __iar_program_start
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD Vector1C
+ DCD Vector20
+ DCD Vector24
+ DCD Vector28
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD Vector34
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+ DCD Vector40
+ DCD Vector44
+ DCD Vector48
+ DCD Vector4C
+ DCD Vector50
+ DCD Vector54
+ DCD Vector58
+ DCD Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ DCD Vector60
+ DCD Vector64
+ DCD Vector68
+ DCD Vector6C
+ DCD Vector70
+ DCD Vector74
+ DCD Vector78
+ DCD Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ DCD Vector80
+ DCD Vector84
+ DCD Vector88
+ DCD Vector8C
+ DCD Vector90
+ DCD Vector94
+ DCD Vector98
+ DCD Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ DCD VectorA0
+ DCD VectorA4
+ DCD VectorA8
+ DCD VectorAC
+ DCD VectorB0
+ DCD VectorB4
+ DCD VectorB8
+ DCD VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ DCD VectorC0
+ DCD VectorC4
+ DCD VectorC8
+ DCD VectorCC
+ DCD VectorD0
+ DCD VectorD4
+ DCD VectorD8
+ DCD VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ DCD VectorE0
+ DCD VectorE4
+ DCD VectorE8
+ DCD VectorEC
+ DCD VectorF0
+ DCD VectorF4
+ DCD VectorF8
+ DCD VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ DCD Vector100
+ DCD Vector104
+ DCD Vector108
+ DCD Vector10C
+ DCD Vector110
+ DCD Vector114
+ DCD Vector118
+ DCD Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ DCD Vector120
+ DCD Vector124
+ DCD Vector128
+ DCD Vector12C
+ DCD Vector130
+ DCD Vector134
+ DCD Vector138
+ DCD Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ DCD Vector140
+ DCD Vector144
+ DCD Vector148
+ DCD Vector14C
+ DCD Vector150
+ DCD Vector154
+ DCD Vector158
+ DCD Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ DCD Vector160
+ DCD Vector164
+ DCD Vector168
+ DCD Vector16C
+ DCD Vector170
+ DCD Vector174
+ DCD Vector178
+ DCD Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ DCD Vector180
+ DCD Vector184
+ DCD Vector188
+ DCD Vector18C
+ DCD Vector190
+ DCD Vector194
+ DCD Vector198
+ DCD Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ DCD Vector1A0
+ DCD Vector1A4
+ DCD Vector1A8
+ DCD Vector1AC
+ DCD Vector1B0
+ DCD Vector1B4
+ DCD Vector1B8
+ DCD Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ DCD Vector1C0
+ DCD Vector1C4
+ DCD Vector1C8
+ DCD Vector1CC
+ DCD Vector1D0
+ DCD Vector1D4
+ DCD Vector1D8
+ DCD Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ DCD Vector1E0
+ DCD Vector1E4
+ DCD Vector1E8
+ DCD Vector1EC
+ DCD Vector1F0
+ DCD Vector1F4
+ DCD Vector1F8
+ DCD Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ DCD Vector200
+ DCD Vector204
+ DCD Vector208
+ DCD Vector20C
+ DCD Vector210
+ DCD Vector214
+ DCD Vector218
+ DCD Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ DCD Vector220
+ DCD Vector224
+ DCD Vector228
+ DCD Vector22C
+ DCD Vector230
+ DCD Vector234
+ DCD Vector238
+ DCD Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ DCD Vector240
+ DCD Vector244
+ DCD Vector248
+ DCD Vector24C
+ DCD Vector250
+ DCD Vector254
+ DCD Vector258
+ DCD Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ DCD Vector260
+ DCD Vector264
+ DCD Vector268
+ DCD Vector26C
+ DCD Vector270
+ DCD Vector274
+ DCD Vector278
+ DCD Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ DCD Vector280
+ DCD Vector284
+ DCD Vector288
+ DCD Vector28C
+ DCD Vector290
+ DCD Vector294
+ DCD Vector298
+ DCD Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ DCD Vector2A0
+ DCD Vector2A4
+ DCD Vector2A8
+ DCD Vector2AC
+ DCD Vector2B0
+ DCD Vector2B4
+ DCD Vector2B8
+ DCD Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ DCD Vector2C0
+ DCD Vector2C4
+ DCD Vector2C8
+ DCD Vector2CC
+ DCD Vector2D0
+ DCD Vector2D4
+ DCD Vector2D8
+ DCD Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ DCD Vector2E0
+ DCD Vector2E4
+ DCD Vector2E8
+ DCD Vector2EC
+ DCD Vector2F0
+ DCD Vector2F4
+ DCD Vector2F8
+ DCD Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ DCD Vector300
+ DCD Vector304
+ DCD Vector308
+ DCD Vector30C
+ DCD Vector310
+ DCD Vector314
+ DCD Vector318
+ DCD Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ DCD Vector320
+ DCD Vector324
+ DCD Vector328
+ DCD Vector32C
+ DCD Vector330
+ DCD Vector334
+ DCD Vector338
+ DCD Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ DCD Vector340
+ DCD Vector344
+ DCD Vector348
+ DCD Vector34C
+ DCD Vector350
+ DCD Vector354
+ DCD Vector358
+ DCD Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ DCD Vector360
+ DCD Vector364
+ DCD Vector368
+ DCD Vector36C
+ DCD Vector370
+ DCD Vector374
+ DCD Vector378
+ DCD Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ DCD Vector380
+ DCD Vector384
+ DCD Vector388
+ DCD Vector38C
+ DCD Vector390
+ DCD Vector394
+ DCD Vector398
+ DCD Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ DCD Vector3A0
+ DCD Vector3A4
+ DCD Vector3A8
+ DCD Vector3AC
+ DCD Vector3B0
+ DCD Vector3B4
+ DCD Vector3B8
+ DCD Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ DCD Vector3C0
+ DCD Vector3C4
+ DCD Vector3C8
+ DCD Vector3CC
+ DCD Vector3D0
+ DCD Vector3D4
+ DCD Vector3D8
+ DCD Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ DCD Vector3E0
+ DCD Vector3E4
+ DCD Vector3E8
+ DCD Vector3EC
+ DCD Vector3F0
+ DCD Vector3F4
+ DCD Vector3F8
+ DCD Vector3FC
+#endif
+
+/*
+ * Default interrupt handlers.
+ */
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK Vector1C
+ PUBWEAK Vector20
+ PUBWEAK Vector24
+ PUBWEAK Vector28
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK Vector34
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK Vector40
+ PUBWEAK Vector44
+ PUBWEAK Vector48
+ PUBWEAK Vector4C
+ PUBWEAK Vector50
+ PUBWEAK Vector54
+ PUBWEAK Vector58
+ PUBWEAK Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ PUBWEAK Vector60
+ PUBWEAK Vector64
+ PUBWEAK Vector68
+ PUBWEAK Vector6C
+ PUBWEAK Vector70
+ PUBWEAK Vector74
+ PUBWEAK Vector78
+ PUBWEAK Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ PUBWEAK Vector80
+ PUBWEAK Vector84
+ PUBWEAK Vector88
+ PUBWEAK Vector8C
+ PUBWEAK Vector90
+ PUBWEAK Vector94
+ PUBWEAK Vector98
+ PUBWEAK Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ PUBWEAK VectorA0
+ PUBWEAK VectorA4
+ PUBWEAK VectorA8
+ PUBWEAK VectorAC
+ PUBWEAK VectorB0
+ PUBWEAK VectorB4
+ PUBWEAK VectorB8
+ PUBWEAK VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ PUBWEAK VectorC0
+ PUBWEAK VectorC4
+ PUBWEAK VectorC8
+ PUBWEAK VectorCC
+ PUBWEAK VectorD0
+ PUBWEAK VectorD4
+ PUBWEAK VectorD8
+ PUBWEAK VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ PUBWEAK VectorE0
+ PUBWEAK VectorE4
+ PUBWEAK VectorE8
+ PUBWEAK VectorEC
+ PUBWEAK VectorF0
+ PUBWEAK VectorF4
+ PUBWEAK VectorF8
+ PUBWEAK VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ PUBWEAK Vector100
+ PUBWEAK Vector104
+ PUBWEAK Vector108
+ PUBWEAK Vector10C
+ PUBWEAK Vector110
+ PUBWEAK Vector114
+ PUBWEAK Vector118
+ PUBWEAK Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ PUBWEAK Vector120
+ PUBWEAK Vector124
+ PUBWEAK Vector128
+ PUBWEAK Vector12C
+ PUBWEAK Vector130
+ PUBWEAK Vector134
+ PUBWEAK Vector138
+ PUBWEAK Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ PUBWEAK Vector140
+ PUBWEAK Vector144
+ PUBWEAK Vector148
+ PUBWEAK Vector14C
+ PUBWEAK Vector150
+ PUBWEAK Vector154
+ PUBWEAK Vector158
+ PUBWEAK Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ PUBWEAK Vector160
+ PUBWEAK Vector164
+ PUBWEAK Vector168
+ PUBWEAK Vector16C
+ PUBWEAK Vector170
+ PUBWEAK Vector174
+ PUBWEAK Vector178
+ PUBWEAK Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ PUBWEAK Vector180
+ PUBWEAK Vector184
+ PUBWEAK Vector188
+ PUBWEAK Vector18C
+ PUBWEAK Vector190
+ PUBWEAK Vector194
+ PUBWEAK Vector198
+ PUBWEAK Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ PUBWEAK Vector1A0
+ PUBWEAK Vector1A4
+ PUBWEAK Vector1A8
+ PUBWEAK Vector1AC
+ PUBWEAK Vector1B0
+ PUBWEAK Vector1B4
+ PUBWEAK Vector1B8
+ PUBWEAK Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ PUBWEAK Vector1C0
+ PUBWEAK Vector1C4
+ PUBWEAK Vector1C8
+ PUBWEAK Vector1CC
+ PUBWEAK Vector1D0
+ PUBWEAK Vector1D4
+ PUBWEAK Vector1D8
+ PUBWEAK Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ PUBWEAK Vector1E0
+ PUBWEAK Vector1E4
+ PUBWEAK Vector1E8
+ PUBWEAK Vector1EC
+ PUBWEAK Vector1F0
+ PUBWEAK Vector1F4
+ PUBWEAK Vector1F8
+ PUBWEAK Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ PUBWEAK Vector200
+ PUBWEAK Vector204
+ PUBWEAK Vector208
+ PUBWEAK Vector20C
+ PUBWEAK Vector210
+ PUBWEAK Vector214
+ PUBWEAK Vector218
+ PUBWEAK Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ PUBWEAK Vector220
+ PUBWEAK Vector224
+ PUBWEAK Vector228
+ PUBWEAK Vector22C
+ PUBWEAK Vector230
+ PUBWEAK Vector234
+ PUBWEAK Vector238
+ PUBWEAK Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ PUBWEAK Vector240
+ PUBWEAK Vector244
+ PUBWEAK Vector248
+ PUBWEAK Vector24C
+ PUBWEAK Vector250
+ PUBWEAK Vector254
+ PUBWEAK Vector258
+ PUBWEAK Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ PUBWEAK Vector260
+ PUBWEAK Vector264
+ PUBWEAK Vector268
+ PUBWEAK Vector26C
+ PUBWEAK Vector270
+ PUBWEAK Vector274
+ PUBWEAK Vector278
+ PUBWEAK Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ PUBWEAK Vector280
+ PUBWEAK Vector284
+ PUBWEAK Vector288
+ PUBWEAK Vector28C
+ PUBWEAK Vector290
+ PUBWEAK Vector294
+ PUBWEAK Vector298
+ PUBWEAK Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ PUBWEAK Vector2A0
+ PUBWEAK Vector2A4
+ PUBWEAK Vector2A8
+ PUBWEAK Vector2AC
+ PUBWEAK Vector2B0
+ PUBWEAK Vector2B4
+ PUBWEAK Vector2B8
+ PUBWEAK Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ PUBWEAK Vector2C0
+ PUBWEAK Vector2C4
+ PUBWEAK Vector2C8
+ PUBWEAK Vector2CC
+ PUBWEAK Vector2D0
+ PUBWEAK Vector2D4
+ PUBWEAK Vector2D8
+ PUBWEAK Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ PUBWEAK Vector2E0
+ PUBWEAK Vector2E4
+ PUBWEAK Vector2E8
+ PUBWEAK Vector2EC
+ PUBWEAK Vector2F0
+ PUBWEAK Vector2F4
+ PUBWEAK Vector2F8
+ PUBWEAK Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ PUBWEAK Vector300
+ PUBWEAK Vector304
+ PUBWEAK Vector308
+ PUBWEAK Vector30C
+ PUBWEAK Vector310
+ PUBWEAK Vector314
+ PUBWEAK Vector318
+ PUBWEAK Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ PUBWEAK Vector320
+ PUBWEAK Vector324
+ PUBWEAK Vector328
+ PUBWEAK Vector32C
+ PUBWEAK Vector330
+ PUBWEAK Vector334
+ PUBWEAK Vector338
+ PUBWEAK Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ PUBWEAK Vector340
+ PUBWEAK Vector344
+ PUBWEAK Vector348
+ PUBWEAK Vector34C
+ PUBWEAK Vector350
+ PUBWEAK Vector354
+ PUBWEAK Vector358
+ PUBWEAK Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ PUBWEAK Vector360
+ PUBWEAK Vector364
+ PUBWEAK Vector368
+ PUBWEAK Vector36C
+ PUBWEAK Vector370
+ PUBWEAK Vector374
+ PUBWEAK Vector378
+ PUBWEAK Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ PUBWEAK Vector380
+ PUBWEAK Vector384
+ PUBWEAK Vector388
+ PUBWEAK Vector38C
+ PUBWEAK Vector390
+ PUBWEAK Vector394
+ PUBWEAK Vector398
+ PUBWEAK Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ PUBWEAK Vector3A0
+ PUBWEAK Vector3A4
+ PUBWEAK Vector3A8
+ PUBWEAK Vector3AC
+ PUBWEAK Vector3B0
+ PUBWEAK Vector3B4
+ PUBWEAK Vector3B8
+ PUBWEAK Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ PUBWEAK Vector3C0
+ PUBWEAK Vector3C4
+ PUBWEAK Vector3C8
+ PUBWEAK Vector3CC
+ PUBWEAK Vector3D0
+ PUBWEAK Vector3D4
+ PUBWEAK Vector3D8
+ PUBWEAK Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ PUBWEAK Vector3E0
+ PUBWEAK Vector3E4
+ PUBWEAK Vector3E8
+ PUBWEAK Vector3EC
+ PUBWEAK Vector3F0
+ PUBWEAK Vector3F4
+ PUBWEAK Vector3F8
+ PUBWEAK Vector3FC
+#endif
+ PUBLIC _unhandled_exception
+
+ SECTION .text:CODE:REORDER(1)
+ THUMB
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+_unhandled_exception
+ b _unhandled_exception
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s b/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s new file mode 100644 index 000000000..aa97ca5ab --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/RVCT/cstartup.s @@ -0,0 +1,135 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/RVCT/cstartup.s
+ * @brief Generic RVCT Cortex-Mx startup file.
+ *
+ * @addtogroup ARMCMx_RVCT_STARTUP
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+;/* <<< Use Configuration Wizard in Context Menu >>> */
+
+;// <h> Main Stack Configuration (IRQ Stack)
+;// <o> Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+main_stack_size EQU 0x00000400
+
+;// <h> Process Stack Configuration
+;// <o> Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+proc_stack_size EQU 0x00000400
+
+;// <h> C-runtime heap size
+;// <o> C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
+;// </h>
+heap_size EQU 0x00000400
+
+ AREA MSTACK, NOINIT, READWRITE, ALIGN=3
+main_stack_mem SPACE main_stack_size
+ EXPORT __initial_msp
+__initial_msp
+
+ AREA CSTACK, NOINIT, READWRITE, ALIGN=3
+__main_thread_stack_base__
+ EXPORT __main_thread_stack_base__
+proc_stack_mem SPACE proc_stack_size
+ EXPORT __initial_sp
+__initial_sp
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE heap_size
+__heap_limit
+
+CONTROL_MODE_PRIVILEGED EQU 0
+CONTROL_MODE_UNPRIVILEGED EQU 1
+CONTROL_USE_MSP EQU 0
+CONTROL_USE_PSP EQU 2
+
+ PRESERVE8
+ THUMB
+
+ AREA |.text|, CODE, READONLY
+
+/*
+ * Reset handler.
+ */
+ IMPORT __main
+ EXPORT Reset_Handler
+Reset_Handler PROC
+ cpsid i
+ ldr r0, =__initial_sp
+ msr PSP, r0
+ movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
+ msr CONTROL, r0
+ isb
+ bl __early_init
+
+ IF {CPU} = "Cortex-M4.fp"
+ LDR R0, =0xE000ED88 ; Enable CP10,CP11
+ LDR R1, [R0]
+ ORR R1, R1, #(0xF << 20)
+ STR R1, [R0]
+ ENDIF
+
+ ldr r0, =__main
+ bx r0
+ ENDP
+
+__early_init PROC
+ EXPORT __early_init [WEAK]
+ bx lr
+ ENDP
+
+ ALIGN
+
+/*
+ * User Initial Stack & Heap.
+ */
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+ ldr r0, =Heap_Mem
+ ldr r1, =(proc_stack_mem + proc_stack_size)
+ ldr r2, =(Heap_Mem + heap_size)
+ ldr r3, =proc_stack_mem
+ bx lr
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/compilers/RVCT/vectors.s b/os/common/ports/ARMCMx/compilers/RVCT/vectors.s new file mode 100644 index 000000000..03e4e6196 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/RVCT/vectors.s @@ -0,0 +1,1006 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file ARMCMx/RVCT/vectors.c
+ * @brief Interrupt vectors for Cortex-Mx devices.
+ *
+ * @defgroup ARMCMx_RVCT_VECTORS Cortex-Mx Interrupt Vectors
+ * @{
+ */
+
+#define _FROM_ASM_
+#include "cmparams.h"
+
+#if !defined(__DOXYGEN__)
+
+#if (CORTEX_NUM_VECTORS & 7) != 0
+#error "the constant CORTEX_NUM_VECTORS must be a multiple of 8"
+#endif
+
+#if (CORTEX_NUM_VECTORS < 8) || (CORTEX_NUM_VECTORS > 240)
+#error "the constant CORTEX_NUM_VECTORS must be between 8 and 240 inclusive"
+#endif
+
+ PRESERVE8
+
+ AREA RESET, DATA, READONLY
+
+ IMPORT __initial_msp
+ IMPORT Reset_Handler
+ EXPORT __Vectors
+
+__Vectors
+ DCD __initial_msp
+ DCD Reset_Handler
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+ DCD Vector1C
+ DCD Vector20
+ DCD Vector24
+ DCD Vector28
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD Vector34
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+ DCD Vector40
+ DCD Vector44
+ DCD Vector48
+ DCD Vector4C
+ DCD Vector50
+ DCD Vector54
+ DCD Vector58
+ DCD Vector5C
+#if CORTEX_NUM_VECTORS > 8
+ DCD Vector60
+ DCD Vector64
+ DCD Vector68
+ DCD Vector6C
+ DCD Vector70
+ DCD Vector74
+ DCD Vector78
+ DCD Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ DCD Vector80
+ DCD Vector84
+ DCD Vector88
+ DCD Vector8C
+ DCD Vector90
+ DCD Vector94
+ DCD Vector98
+ DCD Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ DCD VectorA0
+ DCD VectorA4
+ DCD VectorA8
+ DCD VectorAC
+ DCD VectorB0
+ DCD VectorB4
+ DCD VectorB8
+ DCD VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ DCD VectorC0
+ DCD VectorC4
+ DCD VectorC8
+ DCD VectorCC
+ DCD VectorD0
+ DCD VectorD4
+ DCD VectorD8
+ DCD VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ DCD VectorE0
+ DCD VectorE4
+ DCD VectorE8
+ DCD VectorEC
+ DCD VectorF0
+ DCD VectorF4
+ DCD VectorF8
+ DCD VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ DCD Vector100
+ DCD Vector104
+ DCD Vector108
+ DCD Vector10C
+ DCD Vector110
+ DCD Vector114
+ DCD Vector118
+ DCD Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ DCD Vector120
+ DCD Vector124
+ DCD Vector128
+ DCD Vector12C
+ DCD Vector130
+ DCD Vector134
+ DCD Vector138
+ DCD Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ DCD Vector140
+ DCD Vector144
+ DCD Vector148
+ DCD Vector14C
+ DCD Vector150
+ DCD Vector154
+ DCD Vector158
+ DCD Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ DCD Vector160
+ DCD Vector164
+ DCD Vector168
+ DCD Vector16C
+ DCD Vector170
+ DCD Vector174
+ DCD Vector178
+ DCD Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ DCD Vector180
+ DCD Vector184
+ DCD Vector188
+ DCD Vector18C
+ DCD Vector190
+ DCD Vector194
+ DCD Vector198
+ DCD Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ DCD Vector1A0
+ DCD Vector1A4
+ DCD Vector1A8
+ DCD Vector1AC
+ DCD Vector1B0
+ DCD Vector1B4
+ DCD Vector1B8
+ DCD Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ DCD Vector1C0
+ DCD Vector1C4
+ DCD Vector1C8
+ DCD Vector1CC
+ DCD Vector1D0
+ DCD Vector1D4
+ DCD Vector1D8
+ DCD Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ DCD Vector1E0
+ DCD Vector1E4
+ DCD Vector1E8
+ DCD Vector1EC
+ DCD Vector1F0
+ DCD Vector1F4
+ DCD Vector1F8
+ DCD Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ DCD Vector200
+ DCD Vector204
+ DCD Vector208
+ DCD Vector20C
+ DCD Vector210
+ DCD Vector214
+ DCD Vector218
+ DCD Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ DCD Vector220
+ DCD Vector224
+ DCD Vector228
+ DCD Vector22C
+ DCD Vector230
+ DCD Vector234
+ DCD Vector238
+ DCD Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ DCD Vector240
+ DCD Vector244
+ DCD Vector248
+ DCD Vector24C
+ DCD Vector250
+ DCD Vector254
+ DCD Vector258
+ DCD Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ DCD Vector260
+ DCD Vector264
+ DCD Vector268
+ DCD Vector26C
+ DCD Vector270
+ DCD Vector274
+ DCD Vector278
+ DCD Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ DCD Vector280
+ DCD Vector284
+ DCD Vector288
+ DCD Vector28C
+ DCD Vector290
+ DCD Vector294
+ DCD Vector298
+ DCD Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ DCD Vector2A0
+ DCD Vector2A4
+ DCD Vector2A8
+ DCD Vector2AC
+ DCD Vector2B0
+ DCD Vector2B4
+ DCD Vector2B8
+ DCD Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ DCD Vector2C0
+ DCD Vector2C4
+ DCD Vector2C8
+ DCD Vector2CC
+ DCD Vector2D0
+ DCD Vector2D4
+ DCD Vector2D8
+ DCD Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ DCD Vector2E0
+ DCD Vector2E4
+ DCD Vector2E8
+ DCD Vector2EC
+ DCD Vector2F0
+ DCD Vector2F4
+ DCD Vector2F8
+ DCD Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ DCD Vector300
+ DCD Vector304
+ DCD Vector308
+ DCD Vector30C
+ DCD Vector310
+ DCD Vector314
+ DCD Vector318
+ DCD Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ DCD Vector320
+ DCD Vector324
+ DCD Vector328
+ DCD Vector32C
+ DCD Vector330
+ DCD Vector334
+ DCD Vector338
+ DCD Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ DCD Vector340
+ DCD Vector344
+ DCD Vector348
+ DCD Vector34C
+ DCD Vector350
+ DCD Vector354
+ DCD Vector358
+ DCD Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ DCD Vector360
+ DCD Vector364
+ DCD Vector368
+ DCD Vector36C
+ DCD Vector370
+ DCD Vector374
+ DCD Vector378
+ DCD Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ DCD Vector380
+ DCD Vector384
+ DCD Vector388
+ DCD Vector38C
+ DCD Vector390
+ DCD Vector394
+ DCD Vector398
+ DCD Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ DCD Vector3A0
+ DCD Vector3A4
+ DCD Vector3A8
+ DCD Vector3AC
+ DCD Vector3B0
+ DCD Vector3B4
+ DCD Vector3B8
+ DCD Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ DCD Vector3C0
+ DCD Vector3C4
+ DCD Vector3C8
+ DCD Vector3CC
+ DCD Vector3D0
+ DCD Vector3D4
+ DCD Vector3D8
+ DCD Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ DCD Vector3E0
+ DCD Vector3E4
+ DCD Vector3E8
+ DCD Vector3EC
+ DCD Vector3F0
+ DCD Vector3F4
+ DCD Vector3F8
+ DCD Vector3FC
+#endif
+
+ AREA |.text|, CODE, READONLY
+ THUMB
+
+/*
+ * Default interrupt handlers.
+ */
+ EXPORT _unhandled_exception
+_unhandled_exception PROC
+ EXPORT NMI_Handler [WEAK]
+ EXPORT HardFault_Handler [WEAK]
+ EXPORT MemManage_Handler [WEAK]
+ EXPORT BusFault_Handler [WEAK]
+ EXPORT UsageFault_Handler [WEAK]
+ EXPORT Vector1C [WEAK]
+ EXPORT Vector20 [WEAK]
+ EXPORT Vector24 [WEAK]
+ EXPORT Vector28 [WEAK]
+ EXPORT SVC_Handler [WEAK]
+ EXPORT DebugMon_Handler [WEAK]
+ EXPORT Vector34 [WEAK]
+ EXPORT PendSV_Handler [WEAK]
+ EXPORT SysTick_Handler [WEAK]
+ EXPORT Vector40 [WEAK]
+ EXPORT Vector44 [WEAK]
+ EXPORT Vector48 [WEAK]
+ EXPORT Vector4C [WEAK]
+ EXPORT Vector50 [WEAK]
+ EXPORT Vector54 [WEAK]
+ EXPORT Vector58 [WEAK]
+ EXPORT Vector5C [WEAK]
+#if CORTEX_NUM_VECTORS > 8
+ EXPORT Vector60 [WEAK]
+ EXPORT Vector64 [WEAK]
+ EXPORT Vector68 [WEAK]
+ EXPORT Vector6C [WEAK]
+ EXPORT Vector70 [WEAK]
+ EXPORT Vector74 [WEAK]
+ EXPORT Vector78 [WEAK]
+ EXPORT Vector7C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 16
+ EXPORT Vector80 [WEAK]
+ EXPORT Vector84 [WEAK]
+ EXPORT Vector88 [WEAK]
+ EXPORT Vector8C [WEAK]
+ EXPORT Vector90 [WEAK]
+ EXPORT Vector94 [WEAK]
+ EXPORT Vector98 [WEAK]
+ EXPORT Vector9C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 24
+ EXPORT VectorA0 [WEAK]
+ EXPORT VectorA4 [WEAK]
+ EXPORT VectorA8 [WEAK]
+ EXPORT VectorAC [WEAK]
+ EXPORT VectorB0 [WEAK]
+ EXPORT VectorB4 [WEAK]
+ EXPORT VectorB8 [WEAK]
+ EXPORT VectorBC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 32
+ EXPORT VectorC0 [WEAK]
+ EXPORT VectorC4 [WEAK]
+ EXPORT VectorC8 [WEAK]
+ EXPORT VectorCC [WEAK]
+ EXPORT VectorD0 [WEAK]
+ EXPORT VectorD4 [WEAK]
+ EXPORT VectorD8 [WEAK]
+ EXPORT VectorDC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 40
+ EXPORT VectorE0 [WEAK]
+ EXPORT VectorE4 [WEAK]
+ EXPORT VectorE8 [WEAK]
+ EXPORT VectorEC [WEAK]
+ EXPORT VectorF0 [WEAK]
+ EXPORT VectorF4 [WEAK]
+ EXPORT VectorF8 [WEAK]
+ EXPORT VectorFC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 48
+ EXPORT Vector100 [WEAK]
+ EXPORT Vector104 [WEAK]
+ EXPORT Vector108 [WEAK]
+ EXPORT Vector10C [WEAK]
+ EXPORT Vector110 [WEAK]
+ EXPORT Vector114 [WEAK]
+ EXPORT Vector118 [WEAK]
+ EXPORT Vector11C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 56
+ EXPORT Vector120 [WEAK]
+ EXPORT Vector124 [WEAK]
+ EXPORT Vector128 [WEAK]
+ EXPORT Vector12C [WEAK]
+ EXPORT Vector130 [WEAK]
+ EXPORT Vector134 [WEAK]
+ EXPORT Vector138 [WEAK]
+ EXPORT Vector13C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 64
+ EXPORT Vector140 [WEAK]
+ EXPORT Vector144 [WEAK]
+ EXPORT Vector148 [WEAK]
+ EXPORT Vector14C [WEAK]
+ EXPORT Vector150 [WEAK]
+ EXPORT Vector154 [WEAK]
+ EXPORT Vector158 [WEAK]
+ EXPORT Vector15C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 72
+ EXPORT Vector160 [WEAK]
+ EXPORT Vector164 [WEAK]
+ EXPORT Vector168 [WEAK]
+ EXPORT Vector16C [WEAK]
+ EXPORT Vector170 [WEAK]
+ EXPORT Vector174 [WEAK]
+ EXPORT Vector178 [WEAK]
+ EXPORT Vector17C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 80
+ EXPORT Vector180 [WEAK]
+ EXPORT Vector184 [WEAK]
+ EXPORT Vector188 [WEAK]
+ EXPORT Vector18C [WEAK]
+ EXPORT Vector190 [WEAK]
+ EXPORT Vector194 [WEAK]
+ EXPORT Vector198 [WEAK]
+ EXPORT Vector19C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 88
+ EXPORT Vector1A0 [WEAK]
+ EXPORT Vector1A4 [WEAK]
+ EXPORT Vector1A8 [WEAK]
+ EXPORT Vector1AC [WEAK]
+ EXPORT Vector1B0 [WEAK]
+ EXPORT Vector1B4 [WEAK]
+ EXPORT Vector1B8 [WEAK]
+ EXPORT Vector1BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 96
+ EXPORT Vector1C0 [WEAK]
+ EXPORT Vector1C4 [WEAK]
+ EXPORT Vector1C8 [WEAK]
+ EXPORT Vector1CC [WEAK]
+ EXPORT Vector1D0 [WEAK]
+ EXPORT Vector1D4 [WEAK]
+ EXPORT Vector1D8 [WEAK]
+ EXPORT Vector1DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 104
+ EXPORT Vector1E0 [WEAK]
+ EXPORT Vector1E4 [WEAK]
+ EXPORT Vector1E8 [WEAK]
+ EXPORT Vector1EC [WEAK]
+ EXPORT Vector1F0 [WEAK]
+ EXPORT Vector1F4 [WEAK]
+ EXPORT Vector1F8 [WEAK]
+ EXPORT Vector1FC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 112
+ EXPORT Vector200 [WEAK]
+ EXPORT Vector204 [WEAK]
+ EXPORT Vector208 [WEAK]
+ EXPORT Vector20C [WEAK]
+ EXPORT Vector210 [WEAK]
+ EXPORT Vector214 [WEAK]
+ EXPORT Vector218 [WEAK]
+ EXPORT Vector21C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 120
+ EXPORT Vector220 [WEAK]
+ EXPORT Vector224 [WEAK]
+ EXPORT Vector228 [WEAK]
+ EXPORT Vector22C [WEAK]
+ EXPORT Vector230 [WEAK]
+ EXPORT Vector234 [WEAK]
+ EXPORT Vector238 [WEAK]
+ EXPORT Vector23C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 128
+ EXPORT Vector240 [WEAK]
+ EXPORT Vector244 [WEAK]
+ EXPORT Vector248 [WEAK]
+ EXPORT Vector24C [WEAK]
+ EXPORT Vector250 [WEAK]
+ EXPORT Vector254 [WEAK]
+ EXPORT Vector258 [WEAK]
+ EXPORT Vector25C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 136
+ EXPORT Vector260 [WEAK]
+ EXPORT Vector264 [WEAK]
+ EXPORT Vector268 [WEAK]
+ EXPORT Vector26C [WEAK]
+ EXPORT Vector270 [WEAK]
+ EXPORT Vector274 [WEAK]
+ EXPORT Vector278 [WEAK]
+ EXPORT Vector27C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 144
+ EXPORT Vector280 [WEAK]
+ EXPORT Vector284 [WEAK]
+ EXPORT Vector288 [WEAK]
+ EXPORT Vector28C [WEAK]
+ EXPORT Vector290 [WEAK]
+ EXPORT Vector294 [WEAK]
+ EXPORT Vector298 [WEAK]
+ EXPORT Vector29C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 152
+ EXPORT Vector2A0 [WEAK]
+ EXPORT Vector2A4 [WEAK]
+ EXPORT Vector2A8 [WEAK]
+ EXPORT Vector2AC [WEAK]
+ EXPORT Vector2B0 [WEAK]
+ EXPORT Vector2B4 [WEAK]
+ EXPORT Vector2B8 [WEAK]
+ EXPORT Vector2BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 160
+ EXPORT Vector2C0 [WEAK]
+ EXPORT Vector2C4 [WEAK]
+ EXPORT Vector2C8 [WEAK]
+ EXPORT Vector2CC [WEAK]
+ EXPORT Vector2D0 [WEAK]
+ EXPORT Vector2D4 [WEAK]
+ EXPORT Vector2D8 [WEAK]
+ EXPORT Vector2DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 168
+ EXPORT Vector2E0 [WEAK]
+ EXPORT Vector2E4 [WEAK]
+ EXPORT Vector2E8 [WEAK]
+ EXPORT Vector2EC [WEAK]
+ EXPORT Vector2F0 [WEAK]
+ EXPORT Vector2F4 [WEAK]
+ EXPORT Vector2F8 [WEAK]
+ EXPORT Vector2FC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 176
+ EXPORT Vector300 [WEAK]
+ EXPORT Vector304 [WEAK]
+ EXPORT Vector308 [WEAK]
+ EXPORT Vector30C [WEAK]
+ EXPORT Vector310 [WEAK]
+ EXPORT Vector314 [WEAK]
+ EXPORT Vector318 [WEAK]
+ EXPORT Vector31C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 184
+ EXPORT Vector320 [WEAK]
+ EXPORT Vector324 [WEAK]
+ EXPORT Vector328 [WEAK]
+ EXPORT Vector32C [WEAK]
+ EXPORT Vector330 [WEAK]
+ EXPORT Vector334 [WEAK]
+ EXPORT Vector338 [WEAK]
+ EXPORT Vector33C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 192
+ EXPORT Vector340 [WEAK]
+ EXPORT Vector344 [WEAK]
+ EXPORT Vector348 [WEAK]
+ EXPORT Vector34C [WEAK]
+ EXPORT Vector350 [WEAK]
+ EXPORT Vector354 [WEAK]
+ EXPORT Vector358 [WEAK]
+ EXPORT Vector35C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 200
+ EXPORT Vector360 [WEAK]
+ EXPORT Vector364 [WEAK]
+ EXPORT Vector368 [WEAK]
+ EXPORT Vector36C [WEAK]
+ EXPORT Vector370 [WEAK]
+ EXPORT Vector374 [WEAK]
+ EXPORT Vector378 [WEAK]
+ EXPORT Vector37C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 208
+ EXPORT Vector380 [WEAK]
+ EXPORT Vector384 [WEAK]
+ EXPORT Vector388 [WEAK]
+ EXPORT Vector38C [WEAK]
+ EXPORT Vector390 [WEAK]
+ EXPORT Vector394 [WEAK]
+ EXPORT Vector398 [WEAK]
+ EXPORT Vector39C [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 216
+ EXPORT Vector3A0 [WEAK]
+ EXPORT Vector3A4 [WEAK]
+ EXPORT Vector3A8 [WEAK]
+ EXPORT Vector3AC [WEAK]
+ EXPORT Vector3B0 [WEAK]
+ EXPORT Vector3B4 [WEAK]
+ EXPORT Vector3B8 [WEAK]
+ EXPORT Vector3BC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 224
+ EXPORT Vector3C0 [WEAK]
+ EXPORT Vector3C4 [WEAK]
+ EXPORT Vector3C8 [WEAK]
+ EXPORT Vector3CC [WEAK]
+ EXPORT Vector3D0 [WEAK]
+ EXPORT Vector3D4 [WEAK]
+ EXPORT Vector3D8 [WEAK]
+ EXPORT Vector3DC [WEAK]
+#endif
+#if CORTEX_NUM_VECTORS > 232
+ EXPORT Vector3E0 [WEAK]
+ EXPORT Vector3E4 [WEAK]
+ EXPORT Vector3E8 [WEAK]
+ EXPORT Vector3EC [WEAK]
+ EXPORT Vector3F0 [WEAK]
+ EXPORT Vector3F4 [WEAK]
+ EXPORT Vector3F8 [WEAK]
+ EXPORT Vector3FC [WEAK]
+#endif
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+Vector1C
+Vector20
+Vector24
+Vector28
+SVC_Handler
+DebugMon_Handler
+Vector34
+PendSV_Handler
+SysTick_Handler
+Vector40
+Vector44
+Vector48
+Vector4C
+Vector50
+Vector54
+Vector58
+Vector5C
+#if CORTEX_NUM_VECTORS > 8
+Vector60
+Vector64
+Vector68
+Vector6C
+Vector70
+Vector74
+Vector78
+Vector7C
+#endif
+#if CORTEX_NUM_VECTORS > 16
+Vector80
+Vector84
+Vector88
+Vector8C
+Vector90
+Vector94
+Vector98
+Vector9C
+#endif
+#if CORTEX_NUM_VECTORS > 24
+VectorA0
+VectorA4
+VectorA8
+VectorAC
+VectorB0
+VectorB4
+VectorB8
+VectorBC
+#endif
+#if CORTEX_NUM_VECTORS > 32
+VectorC0
+VectorC4
+VectorC8
+VectorCC
+VectorD0
+VectorD4
+VectorD8
+VectorDC
+#endif
+#if CORTEX_NUM_VECTORS > 40
+VectorE0
+VectorE4
+VectorE8
+VectorEC
+VectorF0
+VectorF4
+VectorF8
+VectorFC
+#endif
+#if CORTEX_NUM_VECTORS > 48
+Vector100
+Vector104
+Vector108
+Vector10C
+Vector110
+Vector114
+Vector118
+Vector11C
+#endif
+#if CORTEX_NUM_VECTORS > 56
+Vector120
+Vector124
+Vector128
+Vector12C
+Vector130
+Vector134
+Vector138
+Vector13C
+#endif
+#if CORTEX_NUM_VECTORS > 64
+Vector140
+Vector144
+Vector148
+Vector14C
+Vector150
+Vector154
+Vector158
+Vector15C
+#endif
+#if CORTEX_NUM_VECTORS > 72
+Vector160
+Vector164
+Vector168
+Vector16C
+Vector170
+Vector174
+Vector178
+Vector17C
+#endif
+#if CORTEX_NUM_VECTORS > 80
+Vector180
+Vector184
+Vector188
+Vector18C
+Vector190
+Vector194
+Vector198
+Vector19C
+#endif
+#if CORTEX_NUM_VECTORS > 88
+Vector1A0
+Vector1A4
+Vector1A8
+Vector1AC
+Vector1B0
+Vector1B4
+Vector1B8
+Vector1BC
+#endif
+#if CORTEX_NUM_VECTORS > 96
+Vector1C0
+Vector1C4
+Vector1C8
+Vector1CC
+Vector1D0
+Vector1D4
+Vector1D8
+Vector1DC
+#endif
+#if CORTEX_NUM_VECTORS > 104
+Vector1E0
+Vector1E4
+Vector1E8
+Vector1EC
+Vector1F0
+Vector1F4
+Vector1F8
+Vector1FC
+#endif
+#if CORTEX_NUM_VECTORS > 112
+Vector200
+Vector204
+Vector208
+Vector20C
+Vector210
+Vector214
+Vector218
+Vector21C
+#endif
+#if CORTEX_NUM_VECTORS > 120
+Vector220
+Vector224
+Vector228
+Vector22C
+Vector230
+Vector234
+Vector238
+Vector23C
+#endif
+#if CORTEX_NUM_VECTORS > 128
+Vector240
+Vector244
+Vector248
+Vector24C
+Vector250
+Vector254
+Vector258
+Vector25C
+#endif
+#if CORTEX_NUM_VECTORS > 136
+Vector260
+Vector264
+Vector268
+Vector26C
+Vector270
+Vector274
+Vector278
+Vector27C
+#endif
+#if CORTEX_NUM_VECTORS > 144
+Vector280
+Vector284
+Vector288
+Vector28C
+Vector290
+Vector294
+Vector298
+Vector29C
+#endif
+#if CORTEX_NUM_VECTORS > 152
+Vector2A0
+Vector2A4
+Vector2A8
+Vector2AC
+Vector2B0
+Vector2B4
+Vector2B8
+Vector2BC
+#endif
+#if CORTEX_NUM_VECTORS > 160
+Vector2C0
+Vector2C4
+Vector2C8
+Vector2CC
+Vector2D0
+Vector2D4
+Vector2D8
+Vector2DC
+#endif
+#if CORTEX_NUM_VECTORS > 168
+Vector2E0
+Vector2E4
+Vector2E8
+Vector2EC
+Vector2F0
+Vector2F4
+Vector2F8
+Vector2FC
+#endif
+#if CORTEX_NUM_VECTORS > 176
+Vector300
+Vector304
+Vector308
+Vector30C
+Vector310
+Vector314
+Vector318
+Vector31C
+#endif
+#if CORTEX_NUM_VECTORS > 184
+Vector320
+Vector324
+Vector328
+Vector32C
+Vector330
+Vector334
+Vector338
+Vector33C
+#endif
+#if CORTEX_NUM_VECTORS > 192
+Vector340
+Vector344
+Vector348
+Vector34C
+Vector350
+Vector354
+Vector358
+Vector35C
+#endif
+#if CORTEX_NUM_VECTORS > 200
+Vector360
+Vector364
+Vector368
+Vector36C
+Vector370
+Vector374
+Vector378
+Vector37C
+#endif
+#if CORTEX_NUM_VECTORS > 208
+Vector380
+Vector384
+Vector388
+Vector38C
+Vector390
+Vector394
+Vector398
+Vector39C
+#endif
+#if CORTEX_NUM_VECTORS > 216
+Vector3A0
+Vector3A4
+Vector3A8
+Vector3AC
+Vector3B0
+Vector3B4
+Vector3B8
+Vector3BC
+#endif
+#if CORTEX_NUM_VECTORS > 224
+Vector3C0
+Vector3C4
+Vector3C8
+Vector3CC
+Vector3D0
+Vector3D4
+Vector3D8
+Vector3DC
+#endif
+#if CORTEX_NUM_VECTORS > 232
+Vector3E0
+Vector3E4
+Vector3E8
+Vector3EC
+Vector3F0
+Vector3F4
+Vector3F8
+Vector3FC
+#endif
+ b _unhandled_exception
+ ENDP
+
+ END
+
+#endif /* !defined(__DOXYGEN__) */
+
+/**< @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h new file mode 100644 index 000000000..8def2c0e0 --- /dev/null +++ b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h @@ -0,0 +1,90 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F0xx/cmparams.h
+ * @brief ARM Cortex-M0 parameters for the STM32F0xx.
+ *
+ * @defgroup ARMCMx_STM32F0xx STM32F0xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M0 specific parameters for the
+ * STM32F0xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M0
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 2
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 32
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F0030) && !defined(STM32F0XX_LD) && !defined(STM32F0XX_MD)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f0xx.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h new file mode 100644 index 000000000..282f26602 --- /dev/null +++ b/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h @@ -0,0 +1,113 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F1xx/cmparams.h
+ * @brief ARM Cortex-M3 parameters for the STM32F1xx.
+ *
+ * @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F1xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M3
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 0
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS __NVECTORS
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \
+ !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \
+ !defined(STM32F10X_HD) && !defined(STM32F10X_HD_VL) && \
+ !defined(STM32F10X_XL) && !defined(STM32F10X_CL)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f10x.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#if defined(STM32F10X_CL)
+#define __NVECTORS 72
+#elif defined(STM32F10X_XL)
+#define __NVECTORS 64
+#elif defined(STM32F10X_LD_VL) || \
+ defined(STM32F10X_MD_VL) || \
+ defined(STM32F10X_HD_VL)
+#define __NVECTORS 64
+#elif defined(STM32F10X_LD) || \
+ defined(STM32F10X_MD) || \
+ defined(STM32F10X_HD)
+#define __NVECTORS 64
+#else
+#error "STM32F1xx device not defined or not recognized"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h new file mode 100644 index 000000000..28e8051c6 --- /dev/null +++ b/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h @@ -0,0 +1,94 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F3xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F3xx.
+ *
+ * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F3xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M4
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 1
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 88
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32F30X)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f30x.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h new file mode 100644 index 000000000..274e54193 --- /dev/null +++ b/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h @@ -0,0 +1,94 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F37x/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F37x.
+ *
+ * @defgroup ARMCMx_STM32F37x STM32F37x Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F37x platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M4
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 1
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 88
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined (STM32F37X)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f37x.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h new file mode 100644 index 000000000..e742a7e66 --- /dev/null +++ b/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h @@ -0,0 +1,95 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F4xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32F4xx.
+ *
+ * @defgroup ARMCMx_STM32F4xx STM32F4xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32F4xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M4
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 1
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 1
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 96
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && \
+ !defined(STM32F429_439xx) && !defined(STM32F401xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32f4xx.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h new file mode 100644 index 000000000..76dcb200e --- /dev/null +++ b/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h @@ -0,0 +1,94 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32L1xx/cmparams.h
+ * @brief ARM Cortex-M4 parameters for the STM32L1xx.
+ *
+ * @defgroup ARMCMx_STM32L1xx STM32L1xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ * STM32L1xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief Cortex core model.
+ */
+#define CORTEX_MODEL CORTEX_M3
+
+/**
+ * @brief Memory Protection unit presence.
+ */
+#define CORTEX_HAS_MPU 1
+
+/**
+ * @brief Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU 0
+
+/**
+ * @brief Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS 4
+
+/**
+ * @brief Number of interrupt vectors.
+ * @note This number does not include the 16 system vectors and must be
+ * rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS 64
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+ then a file named board.h is included. This file must contain a device
+ definition compatible with the vendor include file.*/
+#if !defined(STM32L1XX_MD) && !defined(STM32L1XX_MDP) && !defined(STM32L1XX_HD)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+ from this header because we need this file to be usable also from
+ assembler source files. We verify that the info matches instead.*/
+#include "stm32l1xx.h"
+
+#if !CORTEX_HAS_MPU != !__MPU_PRESENT
+#error "CMSIS __MPU_PRESENT mismatch"
+#endif
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/compilers/GCC/crt0.s b/os/common/ports/e200/compilers/GCC/crt0.s new file mode 100644 index 000000000..07e870451 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/crt0.s @@ -0,0 +1,126 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file PPC/crt0.s
+ * @brief Generic PowerPC startup file for ChibiOS/RT.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#if !defined(__DOXYGEN__)
+
+ .section .crt0, "ax"
+ .align 2
+ .globl _boot_address
+ .type _boot_address, @function
+_boot_address:
+ /*
+ * Stack setup.
+ */
+ lis %r1, __process_stack_end__@h
+ ori %r1, %r1, __process_stack_end__@l
+ li %r0, 0
+ stwu %r0, -8(%r1)
+ /*
+ * Small sections registers initialization.
+ */
+ lis %r2, __sdata2_start__@h
+ ori %r2, %r2, __sdata2_start__@l
+ lis %r13, __sdata_start__@h
+ ori %r13, %r13, __sdata_start__@l
+ /*
+ * Early initialization.
+ */
+ bl __early_init
+ /*
+ * BSS clearing.
+ */
+ lis %r4, __bss_start__@h
+ ori %r4, %r4, __bss_start__@l
+ lis %r5, __bss_end__@h
+ ori %r5, %r5, __bss_end__@l
+ li %r7, 0
+.bssloop:
+ cmpl cr0, %r4, %r5
+ bge cr0, .bssend
+ stw %r7, 0(%r4)
+ addi %r4, %r4, 4
+ b .bssloop
+.bssend:
+ /*
+ * DATA initialization.
+ */
+ lis %r4, __romdata_start__@h
+ ori %r4, %r4, __romdata_start__@l
+ lis %r5, __data_start__@h
+ ori %r5, %r5, __data_start__@l
+ lis %r6, __data_end__@h
+ ori %r6, %r6, __data_end__@l
+.dataloop:
+ cmpl cr0, %r5, %r6
+ bge cr0, .dataend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .dataloop
+.dataend:
+ /*
+ * Late initialization.
+ */
+ bl __late_init
+ /*
+ * Main program invocation.
+ */
+ bl main
+ b _main_exit_handler
+
+ /*
+ * Default main exit code, infinite loop.
+ */
+ .weak _main_exit_handler
+ .globl _main_exit_handler
+ .type _main_exit_handler, @function
+_main_exit_handler:
+ b _main_exit_handler
+
+ /*
+ * Default early initialization code, none.
+ */
+ .weak __early_init
+ .globl __early_init
+ .type __early_init, @function
+__early_init:
+ blr
+
+ /*
+ * Default late initialization code, none.
+ */
+ .weak __late_init
+ .globl __late_init
+ .type __late_init, @function
+__late_init:
+ blr
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld new file mode 100644 index 000000000..04cf9f9a3 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B50 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 32k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld new file mode 100644 index 000000000..21f266177 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B60.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B60 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1024k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 80k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld new file mode 100644 index 000000000..b0f96746f --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560B64 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1536k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 96k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld new file mode 100644 index 000000000..9e4e3b861 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560D40 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 256k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 16k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld new file mode 100644 index 000000000..c1f78abd5 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560P50.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC560P50 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 512k
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 40k
+}
+
+INCLUDE rules_z0.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld b/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld new file mode 100644 index 000000000..a065dd32d --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC563M64 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1536k
+ ram : org = 0x40000000, len = 94k
+}
+
+INCLUDE rules_z3.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld b/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld new file mode 100644 index 000000000..1f002c807 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC563A70 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 2M
+ ram : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld b/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld new file mode 100644 index 000000000..5d61ef5b9 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC563A80 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 4M
+ ram : org = 0x40000000, len = 192k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld new file mode 100644 index 000000000..8ab1fa6c4 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EC74.ld @@ -0,0 +1,27 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EC74 memory setup.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 3M
+ dataflash : org = 0x00800000, len = 64k
+ ram : org = 0x40000000, len = 256k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld new file mode 100644 index 000000000..e8ed5092d --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EL54_LSM.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EL54 memory setup in LSM mode.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 768k
+ ram : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld new file mode 100644 index 000000000..13fe240f3 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EL60_LSM.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EL60 memory setup in LSM mode.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 1M
+ ram : org = 0x40000000, len = 128k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld b/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld new file mode 100644 index 000000000..2642b4ce2 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC56EL70_LSM.ld @@ -0,0 +1,26 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * SPC56EL70 memory setup in LSM mode.
+ */
+MEMORY
+{
+ flash : org = 0x00000000, len = 2M
+ ram : org = 0x40000000, len = 192k
+}
+
+INCLUDE rules_z4.ld
diff --git a/os/common/ports/e200/compilers/GCC/rules.mk b/os/common/ports/e200/compilers/GCC/rules.mk new file mode 100644 index 000000000..8ca82cac1 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/rules.mk @@ -0,0 +1,218 @@ +# e200z common makefile scripts and rules.
+
+##############################################################################
+# Processing options coming from the upper Makefile.
+#
+
+# Compiler options
+OPT = $(USE_OPT)
+COPT = $(USE_COPT)
+CPPOPT = $(USE_CPPOPT)
+
+# Garbage collection
+ifeq ($(USE_LINK_GC),yes)
+ OPT += -ffunction-sections -fdata-sections -fno-common
+ LDOPT := --gc-sections
+else
+ LDOPT :=
+endif
+
+# Linker extra options
+ifneq ($(USE_LDOPT),)
+ LDOPT := $(LDOPT),$(USE_LDOPT)
+endif
+
+# Link time optimizations
+ifeq ($(USE_LTO),yes)
+ OPT += -flto
+endif
+
+# VLE option handling.
+ifeq ($(USE_VLE),yes)
+ DDEFS += -DPPC_USE_VLE=1
+ DADEFS += -DPPC_USE_VLE=1
+ MCU += -mvle
+else
+ DDEFS += -DPPC_USE_VLE=0
+ DADEFS += -DPPC_USE_VLE=0
+endif
+
+# Process stack size
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__process_stack_size__=$(USE_PROCESS_STACKSIZE)
+endif
+
+# Exceptions stack size
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ LDOPT := $(LDOPT),--defsym=__irq_stack_size__=0x400
+else
+ LDOPT := $(LDOPT),--defsym=__irq_stack_size__=$(USE_EXCEPTIONS_STACKSIZE)
+endif
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+ BUILDDIR = build
+endif
+ifeq ($(BUILDDIR),.)
+ BUILDDIR = build
+endif
+OUTFILES = $(BUILDDIR)/$(PROJECT).elf $(BUILDDIR)/$(PROJECT).hex \
+ $(BUILDDIR)/$(PROJECT).mot $(BUILDDIR)/$(PROJECT).bin \
+ $(BUILDDIR)/$(PROJECT).dmp
+
+# Source files groups and paths
+SRC = $(CSRC)$(CPPSRC)
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(SRC)))
+
+# Various directories
+OBJDIR = $(BUILDDIR)/obj
+LSTDIR = $(BUILDDIR)/lst
+
+# Object files groups
+COBJS = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
+CPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
+ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(COBJS) $(CPPOBJS)
+
+# Paths
+IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
+LLIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+
+# Macros
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+
+# Libs
+LIBS = $(DLIBS) $(ULIBS)
+
+# Various settings
+MCFLAGS = -mcpu=$(MCU)
+ODFLAGS = -x --syms
+ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
+CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
+CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
+LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),$(LDOPT),--script=$(LDSCRIPT)
+
+# Generate dependency information
+CFLAGS += -MD -MP -MF .dep/$(@F).d
+CPPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+# Paths where to search for sources
+VPATH = $(SRCPATHS)
+
+#
+# Makefile rules
+#
+
+all: $(OBJS) $(OUTFILES) MAKE_ALL_RULE_HOOK
+
+MAKE_ALL_RULE_HOOK:
+
+$(OBJS): | $(BUILDDIR)
+
+$(BUILDDIR) $(OBJDIR) $(LSTDIR):
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+ @echo Compiler Options
+ @echo $(CC) -c $(CFLAGS) -I. $(IINCDIR) main.c -o main.o
+ @echo
+endif
+ mkdir -p $(OBJDIR)
+ mkdir -p $(LSTDIR)
+
+$(CPPOBJS) : $(OBJDIR)/%.o : %.cpp Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CPPC) -c $(CPPFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(COBJS) : $(OBJDIR)/%.o : %.c Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(CFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMOBJS) : $(OBJDIR)/%.o : %.s Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $(<F)
+ @$(CC) -c $(ASXFLAGS) -I. $(IINCDIR) $< -o $@
+endif
+
+%.elf: $(OBJS) $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+ @echo Linking $@
+ @$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+%.hex: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(HEX) $< $@
+else
+ @echo Creating $@
+ @$(HEX) $< $@
+endif
+
+%.mot: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(MOT) $< $@
+else
+ @echo Creating $@
+ @$(MOT) $< $@
+endif
+
+%.bin: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(BIN) $< $@
+else
+ @echo Creating $@
+ @$(BIN) $< $@
+endif
+
+%.dmp: %.elf $(LDSCRIPT)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ $(OD) $(ODFLAGS) $< > $@
+else
+ @echo Creating $@
+ @$(OD) $(ODFLAGS) $< > $@
+ @echo
+ @$(SZ) $<
+ @echo
+ @echo Done
+endif
+
+clean:
+ @echo Cleaning
+ -rm -fR .dep $(BUILDDIR)
+ @echo
+ @echo Done
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/os/common/ports/e200/compilers/GCC/rules_z0.ld b/os/common/ports/e200/compilers/GCC/rules_z0.ld new file mode 100644 index 000000000..ad44243e3 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/rules_z0.ld @@ -0,0 +1,159 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_size__ = LENGTH(ram);
+__ram_start__ = ORIGIN(ram);
+__ram_end__ = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+ . = ORIGIN(flash);
+ .boot0 : ALIGN(16) SUBALIGN(16)
+ {
+ KEEP(*(.boot))
+ } > flash
+
+ .boot1 : ALIGN(16) SUBALIGN(16)
+ {
+ KEEP(*(.handlers))
+ KEEP(*(.crt0))
+ /* The vectors table requires a 2kB alignment.*/
+ . = ALIGN(0x800);
+ KEEP(*(.vectors))
+ /* The IVPR register requires a 4kB alignment.*/
+ . = ALIGN(0x1000);
+ __ivpr_base__ = .;
+ KEEP(*(.ivors))
+ } > flash
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text_vle : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text_vle)
+ *(.text_vle.*)
+ *(.gnu.linkonce.t_vle.*)
+ } > flash
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata : ALIGN(16) SUBALIGN(16)
+ {
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ } > flash
+
+ .sdata2 : ALIGN(16) SUBALIGN(16)
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .romdata : ALIGN(16) SUBALIGN(16)
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .stacks : ALIGN(16) SUBALIGN(16)
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data : AT(__romdata_start__)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __data_end__ = .;
+ } > ram
+
+ .sbss :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/os/common/ports/e200/compilers/GCC/rules_z3.ld b/os/common/ports/e200/compilers/GCC/rules_z3.ld new file mode 100644 index 000000000..38177f3b5 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/rules_z3.ld @@ -0,0 +1,156 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_size__ = LENGTH(ram);
+__ram_start__ = ORIGIN(ram);
+__ram_end__ = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+ . = ORIGIN(flash);
+ .boot0 : ALIGN(16) SUBALIGN(16)
+ {
+ __ivpr_base__ = .;
+ KEEP(*(.boot))
+ } > flash
+
+ .boot1 : ALIGN(16) SUBALIGN(16)
+ {
+ KEEP(*(.handlers))
+ KEEP(*(.crt0))
+ /* The vectors table requires a 2kB alignment.*/
+ . = ALIGN(0x800);
+ KEEP(*(.vectors))
+ } > flash
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text_vle : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text_vle)
+ *(.text_vle.*)
+ *(.gnu.linkonce.t_vle.*)
+ } > flash
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata : ALIGN(16) SUBALIGN(16)
+ {
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ } > flash
+
+ .sdata2 : ALIGN(16) SUBALIGN(16)
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .romdata : ALIGN(16) SUBALIGN(16)
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .stacks : ALIGN(16) SUBALIGN(16)
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data : AT(__romdata_start__)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __data_end__ = .;
+ } > ram
+
+ .sbss :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/os/common/ports/e200/compilers/GCC/rules_z4.ld b/os/common/ports/e200/compilers/GCC/rules_z4.ld new file mode 100644 index 000000000..38177f3b5 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/rules_z4.ld @@ -0,0 +1,156 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+__ram_size__ = LENGTH(ram);
+__ram_start__ = ORIGIN(ram);
+__ram_end__ = ORIGIN(ram) + LENGTH(ram);
+
+ENTRY(_reset_address)
+
+SECTIONS
+{
+ . = ORIGIN(flash);
+ .boot0 : ALIGN(16) SUBALIGN(16)
+ {
+ __ivpr_base__ = .;
+ KEEP(*(.boot))
+ } > flash
+
+ .boot1 : ALIGN(16) SUBALIGN(16)
+ {
+ KEEP(*(.handlers))
+ KEEP(*(.crt0))
+ /* The vectors table requires a 2kB alignment.*/
+ . = ALIGN(0x800);
+ KEEP(*(.vectors))
+ } > flash
+
+ constructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE(__init_array_end = .);
+ } > flash
+
+ destructors : ALIGN(4) SUBALIGN(4)
+ {
+ PROVIDE(__fini_array_start = .);
+ KEEP(*(.fini_array))
+ KEEP(*(SORT(.fini_array.*)))
+ PROVIDE(__fini_array_end = .);
+ } > flash
+
+ .text_vle : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text_vle)
+ *(.text_vle.*)
+ *(.gnu.linkonce.t_vle.*)
+ } > flash
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata : ALIGN(16) SUBALIGN(16)
+ {
+ *(.glue_7t)
+ *(.glue_7)
+ *(.gcc*)
+ *(.rodata)
+ *(.rodata.*)
+ *(.rodata1)
+ } > flash
+
+ .sdata2 : ALIGN(16) SUBALIGN(16)
+ {
+ __sdata2_start__ = . + 0x8000;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ } > flash
+
+ .eh_frame_hdr :
+ {
+ *(.eh_frame_hdr)
+ } > flash
+
+ .eh_frame : ONLY_IF_RO
+ {
+ *(.eh_frame)
+ } > flash
+
+ .romdata : ALIGN(16) SUBALIGN(16)
+ {
+ __romdata_start__ = .;
+ } > flash
+
+ .stacks : ALIGN(16) SUBALIGN(16)
+ {
+ . = ALIGN(8);
+ __irq_stack_base__ = .;
+ . += __irq_stack_size__;
+ . = ALIGN(8);
+ __irq_stack_end__ = .;
+ __process_stack_base__ = .;
+ __main_thread_stack_base__ = .;
+ . += __process_stack_size__;
+ . = ALIGN(8);
+ __process_stack_end__ = .;
+ __main_thread_stack_end__ = .;
+ } > ram
+
+ .data : AT(__romdata_start__)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __sdata_start__ = . + 0x8000;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __data_end__ = .;
+ } > ram
+
+ .sbss :
+ {
+ __bss_start__ = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > ram
+
+ __heap_base__ = __bss_end__;
+ __heap_end__ = __ram_end__;
+}
diff --git a/os/common/ports/e200/compilers/GCC/vectors.h b/os/common/ports/e200/compilers/GCC/vectors.h new file mode 100644 index 000000000..60241864e --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/vectors.h @@ -0,0 +1,105 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file vectors.h
+ * @brief ISR vector module header.
+ *
+ * @addtogroup VECTORS
+ * @{
+ */
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+#include "ppcparams.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#define INTC_MCR *((volatile uint32_t *)0xfff48000)
+#define INTC_CPR *((volatile uint32_t *)0xfff48008)
+#define INTC_IACKR *((volatile uint32_t *)0xfff48010)
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+#if !defined(__DOXYGEN__)
+extern uint32_t _vectors[PPC_NUM_VECTORS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _unhandled_irq(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+/* The following code is not processed when the file is included from an
+ asm module.*/
+#if !defined(_FROM_ASM_)
+
+static inline void intc_init(void) {
+
+ INTC_MCR = 0;
+ INTC_CPR = 0;
+ INTC_IACKR = (uint32_t)_vectors;
+}
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _VECTORS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/compilers/GCC/vectors.s b/os/common/ports/e200/compilers/GCC/vectors.s new file mode 100644 index 000000000..bf6c2adf6 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/vectors.s @@ -0,0 +1,1076 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file vectors.s
+ * @brief SPC56x vectors table.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+#include "ppcparams.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* Software vectors table. The vectors are accessed from the IVOR4
+ handler only. In order to declare an interrupt handler just create
+ a function withe the same name of a vector, the symbol will
+ override the weak symbol declared here.*/
+ .section .vectors, "ax"
+ .align 4
+ .globl _vectors
+_vectors:
+ .long vector0, vector1, vector2, vector3
+#if PPC_NUM_VECTORS > 4
+ .long vector4, vector5, vector6, vector7
+#endif
+#if PPC_NUM_VECTORS > 8
+ .long vector8, vector9, vector10, vector11
+#endif
+#if PPC_NUM_VECTORS > 12
+ .long vector12, vector13, vector14, vector15
+#endif
+#if PPC_NUM_VECTORS > 16
+ .long vector16, vector17, vector18, vector19
+#endif
+#if PPC_NUM_VECTORS > 20
+ .long vector20, vector21, vector22, vector23
+#endif
+#if PPC_NUM_VECTORS > 24
+ .long vector24, vector25, vector26, vector27
+#endif
+#if PPC_NUM_VECTORS > 28
+ .long vector28, vector29, vector30, vector31
+#endif
+#if PPC_NUM_VECTORS > 32
+ .long vector32, vector33, vector34, vector35
+#endif
+#if PPC_NUM_VECTORS > 36
+ .long vector36, vector37, vector38, vector39
+#endif
+#if PPC_NUM_VECTORS > 40
+ .long vector40, vector41, vector42, vector43
+#endif
+#if PPC_NUM_VECTORS > 44
+ .long vector44, vector45, vector46, vector47
+#endif
+#if PPC_NUM_VECTORS > 48
+ .long vector48, vector49, vector50, vector51
+#endif
+#if PPC_NUM_VECTORS > 52
+ .long vector52, vector53, vector54, vector55
+#endif
+#if PPC_NUM_VECTORS > 56
+ .long vector56, vector57, vector58, vector59
+#endif
+#if PPC_NUM_VECTORS > 60
+ .long vector60, vector61, vector62, vector63
+#endif
+#if PPC_NUM_VECTORS > 64
+ .long vector64, vector65, vector66, vector67
+#endif
+#if PPC_NUM_VECTORS > 68
+ .long vector68, vector69, vector70, vector71
+#endif
+#if PPC_NUM_VECTORS > 72
+ .long vector72, vector73, vector74, vector75
+#endif
+#if PPC_NUM_VECTORS > 76
+ .long vector76, vector77, vector78, vector79
+#endif
+#if PPC_NUM_VECTORS > 80
+ .long vector80, vector81, vector82, vector83
+#endif
+#if PPC_NUM_VECTORS > 84
+ .long vector84, vector85, vector86, vector87
+#endif
+#if PPC_NUM_VECTORS > 88
+ .long vector88, vector89, vector90, vector91
+#endif
+#if PPC_NUM_VECTORS > 92
+ .long vector92, vector93, vector94, vector95
+#endif
+#if PPC_NUM_VECTORS > 96
+ .long vector96, vector97, vector98, vector99
+#endif
+#if PPC_NUM_VECTORS > 100
+ .long vector100, vector101, vector102, vector103
+#endif
+#if PPC_NUM_VECTORS > 104
+ .long vector104, vector105, vector106, vector107
+#endif
+#if PPC_NUM_VECTORS > 108
+ .long vector108, vector109, vector110, vector111
+#endif
+#if PPC_NUM_VECTORS > 112
+ .long vector112, vector113, vector114, vector115
+#endif
+#if PPC_NUM_VECTORS > 116
+ .long vector116, vector117, vector118, vector119
+#endif
+#if PPC_NUM_VECTORS > 120
+ .long vector120, vector121, vector122, vector123
+#endif
+#if PPC_NUM_VECTORS > 124
+ .long vector124, vector125, vector126, vector127
+#endif
+#if PPC_NUM_VECTORS > 128
+ .long vector128, vector129, vector130, vector131
+#endif
+#if PPC_NUM_VECTORS > 132
+ .long vector132, vector133, vector134, vector135
+#endif
+#if PPC_NUM_VECTORS > 136
+ .long vector136, vector137, vector138, vector139
+#endif
+#if PPC_NUM_VECTORS > 140
+ .long vector140, vector141, vector142, vector143
+#endif
+#if PPC_NUM_VECTORS > 144
+ .long vector144, vector145, vector146, vector147
+#endif
+#if PPC_NUM_VECTORS > 148
+ .long vector148, vector149, vector150, vector151
+#endif
+#if PPC_NUM_VECTORS > 152
+ .long vector152, vector153, vector154, vector155
+#endif
+#if PPC_NUM_VECTORS > 156
+ .long vector156, vector157, vector158, vector159
+#endif
+#if PPC_NUM_VECTORS > 160
+ .long vector160, vector161, vector162, vector163
+#endif
+#if PPC_NUM_VECTORS > 164
+ .long vector164, vector165, vector166, vector167
+#endif
+#if PPC_NUM_VECTORS > 168
+ .long vector168, vector169, vector170, vector171
+#endif
+#if PPC_NUM_VECTORS > 172
+ .long vector172, vector173, vector174, vector175
+#endif
+#if PPC_NUM_VECTORS > 176
+ .long vector176, vector177, vector178, vector179
+#endif
+#if PPC_NUM_VECTORS > 180
+ .long vector180, vector181, vector182, vector183
+#endif
+#if PPC_NUM_VECTORS > 184
+ .long vector184, vector185, vector186, vector187
+#endif
+#if PPC_NUM_VECTORS > 188
+ .long vector188, vector189, vector190, vector191
+#endif
+#if PPC_NUM_VECTORS > 192
+ .long vector192, vector193, vector194, vector195
+#endif
+#if PPC_NUM_VECTORS > 196
+ .long vector196, vector197, vector198, vector199
+#endif
+#if PPC_NUM_VECTORS > 200
+ .long vector200, vector201, vector202, vector203
+#endif
+#if PPC_NUM_VECTORS > 204
+ .long vector204, vector205, vector206, vector207
+#endif
+#if PPC_NUM_VECTORS > 208
+ .long vector208, vector209, vector210, vector211
+#endif
+#if PPC_NUM_VECTORS > 212
+ .long vector212, vector213, vector214, vector215
+#endif
+#if PPC_NUM_VECTORS > 216
+ .long vector216, vector217, vector218, vector219
+#endif
+#if PPC_NUM_VECTORS > 220
+ .long vector220, vector221, vector222, vector223
+#endif
+#if PPC_NUM_VECTORS > 224
+ .long vector224, vector225, vector226, vector227
+#endif
+#if PPC_NUM_VECTORS > 228
+ .long vector228, vector229, vector230, vector231
+#endif
+#if PPC_NUM_VECTORS > 232
+ .long vector232, vector233, vector234, vector235
+#endif
+#if PPC_NUM_VECTORS > 236
+ .long vector236, vector237, vector238, vector239
+#endif
+#if PPC_NUM_VECTORS > 240
+ .long vector240, vector241, vector242, vector243
+#endif
+#if PPC_NUM_VECTORS > 244
+ .long vector244, vector245, vector246, vector247
+#endif
+#if PPC_NUM_VECTORS > 248
+ .long vector248, vector249, vector250, vector251
+#endif
+#if PPC_NUM_VECTORS > 252
+ .long vector252, vector253, vector254, vector255
+#endif
+#if PPC_NUM_VECTORS > 256
+ .long vector256, vector257, vector258, vector259
+#endif
+#if PPC_NUM_VECTORS > 260
+ .long vector260, vector261, vector262, vector263
+#endif
+#if PPC_NUM_VECTORS > 264
+ .long vector264, vector265, vector266, vector267
+#endif
+#if PPC_NUM_VECTORS > 268
+ .long vector268, vector269, vector270, vector271
+#endif
+#if PPC_NUM_VECTORS > 272
+ .long vector272, vector273, vector274, vector275
+#endif
+#if PPC_NUM_VECTORS > 276
+ .long vector276, vector277, vector278, vector279
+#endif
+#if PPC_NUM_VECTORS > 280
+ .long vector280, vector281, vector282, vector283
+#endif
+#if PPC_NUM_VECTORS > 284
+ .long vector284, vector285, vector286, vector287
+#endif
+#if PPC_NUM_VECTORS > 288
+ .long vector288, vector289, vector290, vector291
+#endif
+#if PPC_NUM_VECTORS > 292
+ .long vector292, vector293, vector294, vector295
+#endif
+#if PPC_NUM_VECTORS > 296
+ .long vector296, vector297, vector298, vector299
+#endif
+#if PPC_NUM_VECTORS > 300
+ .long vector300, vector301, vector302, vector303
+#endif
+#if PPC_NUM_VECTORS > 304
+ .long vector304, vector305, vector306, vector307
+#endif
+#if PPC_NUM_VECTORS > 308
+ .long vector308, vector309, vector310, vector311
+#endif
+#if PPC_NUM_VECTORS > 312
+ .long vector312, vector313, vector314, vector315
+#endif
+#if PPC_NUM_VECTORS > 316
+ .long vector316, vector317, vector318, vector319
+#endif
+#if PPC_NUM_VECTORS > 320
+ .long vector320, vector321, vector322, vector323
+#endif
+#if PPC_NUM_VECTORS > 324
+ .long vector324, vector325, vector326, vector327
+#endif
+#if PPC_NUM_VECTORS > 328
+ .long vector328, vector329, vector330, vector331
+#endif
+#if PPC_NUM_VECTORS > 332
+ .long vector332, vector333, vector334, vector335
+#endif
+#if PPC_NUM_VECTORS > 336
+ .long vector336, vector337, vector338, vector339
+#endif
+#if PPC_NUM_VECTORS > 340
+ .long vector340, vector341, vector342, vector343
+#endif
+#if PPC_NUM_VECTORS > 344
+ .long vector344, vector345, vector346, vector347
+#endif
+#if PPC_NUM_VECTORS > 348
+ .long vector348, vector349, vector350, vector351
+#endif
+#if PPC_NUM_VECTORS > 352
+ .long vector352, vector353, vector354, vector355
+#endif
+#if PPC_NUM_VECTORS > 356
+ .long vector356, vector357, vector358, vector359
+#endif
+#if PPC_NUM_VECTORS > 360
+ .long vector360, vector361, vector362, vector363
+#endif
+#if PPC_NUM_VECTORS > 364
+ .long vector364, vector365, vector366, vector367
+#endif
+#if PPC_NUM_VECTORS > 368
+ .long vector368, vector369, vector370, vector371
+#endif
+#if PPC_NUM_VECTORS > 372
+ .long vector372, vector373, vector374, vector375
+#endif
+#if PPC_NUM_VECTORS > 376
+ .long vector376, vector377, vector378, vector379
+#endif
+#if PPC_NUM_VECTORS > 380
+ .long vector380, vector381, vector382, vector383
+#endif
+#if PPC_NUM_VECTORS > 384
+ .long vector384, vector385, vector386, vector387
+#endif
+#if PPC_NUM_VECTORS > 388
+ .long vector388, vector389, vector390, vector391
+#endif
+#if PPC_NUM_VECTORS > 392
+ .long vector392, vector393, vector394, vector395
+#endif
+#if PPC_NUM_VECTORS > 396
+ .long vector396, vector397, vector398, vector399
+#endif
+#if PPC_NUM_VECTORS > 400
+ .long vector400, vector401, vector402, vector403
+#endif
+#if PPC_NUM_VECTORS > 404
+ .long vector404, vector405, vector406, vector407
+#endif
+#if PPC_NUM_VECTORS > 408
+ .long vector408, vector409, vector410, vector411
+#endif
+#if PPC_NUM_VECTORS > 412
+ .long vector412, vector413, vector414, vector415
+#endif
+#if PPC_NUM_VECTORS > 416
+ .long vector416, vector417, vector418, vector419
+#endif
+#if PPC_NUM_VECTORS > 420
+ .long vector420, vector421, vector422, vector423
+#endif
+#if PPC_NUM_VECTORS > 424
+ .long vector424, vector425, vector426, vector427
+#endif
+#if PPC_NUM_VECTORS > 428
+ .long vector428, vector429, vector430, vector431
+#endif
+#if PPC_NUM_VECTORS > 432
+ .long vector432, vector433, vector434, vector435
+#endif
+#if PPC_NUM_VECTORS > 436
+ .long vector436, vector437, vector438, vector439
+#endif
+#if PPC_NUM_VECTORS > 440
+ .long vector440, vector441, vector442, vector443
+#endif
+#if PPC_NUM_VECTORS > 444
+ .long vector444, vector445, vector446, vector447
+#endif
+#if PPC_NUM_VECTORS > 448
+ .long vector448, vector449, vector450, vector451
+#endif
+#if PPC_NUM_VECTORS > 452
+ .long vector452, vector453, vector454, vector455
+#endif
+#if PPC_NUM_VECTORS > 456
+ .long vector456, vector457, vector458, vector459
+#endif
+#if PPC_NUM_VECTORS > 460
+ .long vector460, vector461, vector462, vector463
+#endif
+#if PPC_NUM_VECTORS > 464
+ .long vector464, vector465, vector466, vector467
+#endif
+#if PPC_NUM_VECTORS > 468
+ .long vector468, vector469, vector470, vector471
+#endif
+#if PPC_NUM_VECTORS > 472
+ .long vector472, vector473, vector474, vector475
+#endif
+#if PPC_NUM_VECTORS > 476
+ .long vector476, vector477, vector478, vector479
+#endif
+#if PPC_NUM_VECTORS > 480
+ .long vector480, vector481, vector482, vector483
+#endif
+#if PPC_NUM_VECTORS > 484
+ .long vector484, vector485, vector486, vector487
+#endif
+#if PPC_NUM_VECTORS > 488
+ .long vector488, vector489, vector490, vector491
+#endif
+#if PPC_NUM_VECTORS > 492
+ .long vector492, vector493, vector494, vector495
+#endif
+#if PPC_NUM_VECTORS > 496
+ .long vector496, vector497, vector498, vector499
+#endif
+#if PPC_NUM_VECTORS > 500
+ .long vector500, vector501, vector502, vector503
+#endif
+#if PPC_NUM_VECTORS > 504
+ .long vector504, vector505, vector506, vector507
+#endif
+#if PPC_NUM_VECTORS > 508
+ .long vector508, vector509, vector510, vector511
+#endif
+
+ .text
+ .align 2
+
+ .weak vector0, vector1, vector2, vector3
+ .weak vector4, vector5, vector6, vector7
+ .weak vector8, vector9, vector10, vector11
+ .weak vector12, vector13, vector14, vector15
+ .weak vector16, vector17, vector18, vector19
+ .weak vector20, vector21, vector22, vector23
+ .weak vector24, vector25, vector26, vector27
+ .weak vector28, vector29, vector30, vector31
+ .weak vector32, vector33, vector34, vector35
+ .weak vector36, vector37, vector38, vector39
+ .weak vector40, vector41, vector42, vector43
+ .weak vector44, vector45, vector46, vector47
+ .weak vector48, vector49, vector50, vector51
+ .weak vector52, vector53, vector54, vector55
+ .weak vector56, vector57, vector58, vector59
+ .weak vector60, vector61, vector62, vector63
+ .weak vector64, vector65, vector66, vector67
+ .weak vector68, vector69, vector70, vector71
+ .weak vector72, vector73, vector74, vector75
+ .weak vector76, vector77, vector78, vector79
+ .weak vector80, vector81, vector82, vector83
+ .weak vector84, vector85, vector86, vector87
+ .weak vector88, vector89, vector90, vector91
+ .weak vector92, vector93, vector94, vector95
+ .weak vector96, vector97, vector98, vector99
+ .weak vector100, vector101, vector102, vector103
+ .weak vector104, vector105, vector106, vector107
+ .weak vector108, vector109, vector110, vector111
+ .weak vector112, vector113, vector114, vector115
+ .weak vector116, vector117, vector118, vector119
+ .weak vector120, vector121, vector122, vector123
+ .weak vector124, vector125, vector126, vector127
+ .weak vector128, vector129, vector130, vector131
+ .weak vector132, vector133, vector134, vector135
+ .weak vector136, vector137, vector138, vector139
+ .weak vector140, vector141, vector142, vector143
+ .weak vector144, vector145, vector146, vector147
+ .weak vector148, vector149, vector150, vector151
+ .weak vector152, vector153, vector154, vector155
+ .weak vector156, vector157, vector158, vector159
+ .weak vector160, vector161, vector162, vector163
+ .weak vector164, vector165, vector166, vector167
+ .weak vector168, vector169, vector170, vector171
+ .weak vector172, vector173, vector174, vector175
+ .weak vector176, vector177, vector178, vector179
+ .weak vector180, vector181, vector182, vector183
+ .weak vector184, vector185, vector186, vector187
+ .weak vector188, vector189, vector190, vector191
+ .weak vector192, vector193, vector194, vector195
+ .weak vector196, vector197, vector198, vector199
+ .weak vector200, vector201, vector202, vector203
+ .weak vector204, vector205, vector206, vector207
+ .weak vector208, vector209, vector210, vector211
+ .weak vector212, vector213, vector214, vector215
+ .weak vector216, vector217, vector218, vector219
+ .weak vector220, vector221, vector222, vector223
+ .weak vector224, vector225, vector226, vector227
+ .weak vector228, vector229, vector230, vector231
+ .weak vector232, vector233, vector234, vector235
+ .weak vector236, vector237, vector238, vector239
+ .weak vector240, vector241, vector242, vector243
+ .weak vector244, vector245, vector246, vector247
+ .weak vector248, vector249, vector250, vector251
+ .weak vector252, vector253, vector254, vector255
+ .weak vector256, vector257, vector258, vector259
+ .weak vector260, vector261, vector262, vector263
+ .weak vector264, vector265, vector266, vector267
+ .weak vector268, vector269, vector270, vector271
+ .weak vector272, vector273, vector274, vector275
+ .weak vector276, vector277, vector278, vector279
+ .weak vector280, vector281, vector282, vector283
+ .weak vector284, vector285, vector286, vector287
+ .weak vector288, vector289, vector290, vector291
+ .weak vector292, vector293, vector294, vector295
+ .weak vector296, vector297, vector298, vector299
+ .weak vector300, vector301, vector302, vector303
+ .weak vector304, vector305, vector306, vector307
+ .weak vector308, vector309, vector310, vector311
+ .weak vector312, vector313, vector314, vector315
+ .weak vector316, vector317, vector318, vector319
+ .weak vector320, vector321, vector322, vector323
+ .weak vector324, vector325, vector326, vector327
+ .weak vector328, vector329, vector330, vector331
+ .weak vector332, vector333, vector334, vector335
+ .weak vector336, vector337, vector338, vector339
+ .weak vector340, vector341, vector342, vector343
+ .weak vector344, vector345, vector346, vector347
+ .weak vector348, vector349, vector350, vector351
+ .weak vector352, vector353, vector354, vector355
+ .weak vector356, vector357, vector358, vector359
+ .weak vector360, vector361, vector362, vector363
+ .weak vector364, vector365, vector366, vector367
+ .weak vector368, vector369, vector370, vector371
+ .weak vector372, vector373, vector374, vector375
+ .weak vector376, vector377, vector378, vector379
+ .weak vector380, vector381, vector382, vector383
+ .weak vector384, vector385, vector386, vector387
+ .weak vector388, vector389, vector390, vector391
+ .weak vector392, vector393, vector394, vector395
+ .weak vector396, vector397, vector398, vector399
+ .weak vector400, vector401, vector402, vector403
+ .weak vector404, vector405, vector406, vector407
+ .weak vector408, vector409, vector410, vector411
+ .weak vector412, vector413, vector414, vector415
+ .weak vector416, vector417, vector418, vector419
+ .weak vector420, vector421, vector422, vector423
+ .weak vector424, vector425, vector426, vector427
+ .weak vector428, vector429, vector430, vector431
+ .weak vector432, vector433, vector434, vector435
+ .weak vector436, vector437, vector438, vector439
+ .weak vector440, vector441, vector442, vector443
+ .weak vector444, vector445, vector446, vector447
+ .weak vector448, vector449, vector450, vector451
+ .weak vector452, vector453, vector454, vector455
+ .weak vector456, vector457, vector458, vector459
+ .weak vector460, vector461, vector462, vector463
+ .weak vector464, vector465, vector466, vector467
+ .weak vector468, vector469, vector470, vector471
+ .weak vector472, vector473, vector474, vector475
+ .weak vector476, vector477, vector478, vector479
+ .weak vector480, vector481, vector482, vector483
+ .weak vector484, vector485, vector486, vector487
+ .weak vector488, vector489, vector490, vector491
+ .weak vector492, vector493, vector494, vector495
+ .weak vector496, vector497, vector498, vector499
+ .weak vector500, vector501, vector502, vector503
+ .weak vector504, vector505, vector506, vector507
+ .weak vector508, vector509, vector510, vector511
+
+vector0:
+vector1:
+vector2:
+vector3:
+vector4:
+vector5:
+vector6:
+vector7:
+vector8:
+vector9:
+vector10:
+vector11:
+vector12:
+vector13:
+vector14:
+vector15:
+vector16:
+vector17:
+vector18:
+vector19:
+vector20:
+vector21:
+vector22:
+vector23:
+vector24:
+vector25:
+vector26:
+vector27:
+vector28:
+vector29:
+vector30:
+vector31:
+vector32:
+vector33:
+vector34:
+vector35:
+vector36:
+vector37:
+vector38:
+vector39:
+vector40:
+vector41:
+vector42:
+vector43:
+vector44:
+vector45:
+vector46:
+vector47:
+vector48:
+vector49:
+vector50:
+vector51:
+vector52:
+vector53:
+vector54:
+vector55:
+vector56:
+vector57:
+vector58:
+vector59:
+vector60:
+vector61:
+vector62:
+vector63:
+vector64:
+vector65:
+vector66:
+vector67:
+vector68:
+vector69:
+vector70:
+vector71:
+vector72:
+vector73:
+vector74:
+vector75:
+vector76:
+vector77:
+vector78:
+vector79:
+vector80:
+vector81:
+vector82:
+vector83:
+vector84:
+vector85:
+vector86:
+vector87:
+vector88:
+vector89:
+vector90:
+vector91:
+vector92:
+vector93:
+vector94:
+vector95:
+vector96:
+vector97:
+vector98:
+vector99:
+vector100:
+vector101:
+vector102:
+vector103:
+vector104:
+vector105:
+vector106:
+vector107:
+vector108:
+vector109:
+vector110:
+vector111:
+vector112:
+vector113:
+vector114:
+vector115:
+vector116:
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+vector361:
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+vector365:
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+vector370:
+vector371:
+vector372:
+vector373:
+vector374:
+vector375:
+vector376:
+vector377:
+vector378:
+vector379:
+vector380:
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+vector382:
+vector383:
+vector384:
+vector385:
+vector386:
+vector387:
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+vector389:
+vector390:
+vector391:
+vector392:
+vector393:
+vector394:
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+vector396:
+vector397:
+vector398:
+vector399:
+vector400:
+vector401:
+vector402:
+vector403:
+vector404:
+vector405:
+vector406:
+vector407:
+vector408:
+vector409:
+vector410:
+vector411:
+vector412:
+vector413:
+vector414:
+vector415:
+vector416:
+vector417:
+vector418:
+vector419:
+vector420:
+vector421:
+vector422:
+vector423:
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+vector425:
+vector426:
+vector427:
+vector428:
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+vector430:
+vector431:
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+vector433:
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+vector436:
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+vector440:
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+vector445:
+vector446:
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+vector456:
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+vector460:
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+vector462:
+vector463:
+vector464:
+vector465:
+vector466:
+vector467:
+vector468:
+vector469:
+vector470:
+vector471:
+vector472:
+vector473:
+vector474:
+vector475:
+vector476:
+vector477:
+vector478:
+vector479:
+vector480:
+vector481:
+vector482:
+vector483:
+vector484:
+vector485:
+vector486:
+vector487:
+vector488:
+vector489:
+vector490:
+vector491:
+vector492:
+vector493:
+vector494:
+vector495:
+vector496:
+vector497:
+vector498:
+vector499:
+vector500:
+vector501:
+vector502:
+vector503:
+vector504:
+vector505:
+vector506:
+vector507:
+vector508:
+vector509:
+vector510:
+vector511:
+
+ .weak _unhandled_irq
+ .type _unhandled_irq, @function
+_unhandled_irq:
+ b _unhandled_irq
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560BCxx/boot.h b/os/common/ports/e200/devices/SPC560BCxx/boot.h new file mode 100644 index 000000000..51b2607ae --- /dev/null +++ b/os/common/ports/e200/devices/SPC560BCxx/boot.h @@ -0,0 +1,118 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560BCxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560BCxx/boot.s b/os/common/ports/e200/devices/SPC560BCxx/boot.s new file mode 100644 index 000000000..7c8457161 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560BCxx/boot.s @@ -0,0 +1,214 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/boot.s
+ * @brief SPC560BCxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+IVOR0: b IVOR0
+ .align 4
+IVOR1: b _IVOR1
+ .align 4
+IVOR2: b _IVOR2
+ .align 4
+IVOR3: b _IVOR3
+ .align 4
+IVOR4: b _IVOR4
+ .align 4
+IVOR5: b _IVOR5
+ .align 4
+IVOR6: b _IVOR6
+ .align 4
+IVOR7: b _IVOR7
+ .align 4
+IVOR8: b _IVOR8
+ .align 4
+IVOR9: b _IVOR9
+ .align 4
+IVOR10: b _IVOR10
+ .align 4
+IVOR11: b _IVOR11
+ .align 4
+IVOR12: b _IVOR12
+ .align 4
+IVOR13: b _IVOR13
+ .align 4
+IVOR14: b _IVOR14
+ .align 4
+IVOR15: b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+ .weak _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h b/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h new file mode 100644 index 000000000..5b29a80c8 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560BCxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560BCxx.
+ *
+ * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560BCxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 217
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Bxx/boot.h b/os/common/ports/e200/devices/SPC560Bxx/boot.h new file mode 100644 index 000000000..7e60b8f78 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Bxx/boot.h @@ -0,0 +1,118 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Bxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Bxx/boot.s b/os/common/ports/e200/devices/SPC560Bxx/boot.s new file mode 100644 index 000000000..86600aac2 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Bxx/boot.s @@ -0,0 +1,214 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/boot.s
+ * @brief SPC560Bxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+IVOR0: b IVOR0
+ .align 4
+IVOR1: b _IVOR1
+ .align 4
+IVOR2: b _IVOR2
+ .align 4
+IVOR3: b _IVOR3
+ .align 4
+IVOR4: b _IVOR4
+ .align 4
+IVOR5: b _IVOR5
+ .align 4
+IVOR6: b _IVOR6
+ .align 4
+IVOR7: b _IVOR7
+ .align 4
+IVOR8: b _IVOR8
+ .align 4
+IVOR9: b _IVOR9
+ .align 4
+IVOR10: b _IVOR10
+ .align 4
+IVOR11: b _IVOR11
+ .align 4
+IVOR12: b _IVOR12
+ .align 4
+IVOR13: b _IVOR13
+ .align 4
+IVOR14: b _IVOR14
+ .align 4
+IVOR15: b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+ .weak _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h new file mode 100644 index 000000000..451971b61 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Bxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Bxx.
+ *
+ * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Bxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 234
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Dxx/boot.h b/os/common/ports/e200/devices/SPC560Dxx/boot.h new file mode 100644 index 000000000..bb51eebda --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Dxx/boot.h @@ -0,0 +1,118 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Dxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Dxx/boot.s b/os/common/ports/e200/devices/SPC560Dxx/boot.s new file mode 100644 index 000000000..520cdf41a --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Dxx/boot.s @@ -0,0 +1,214 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/boot.s
+ * @brief SPC560Dxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+IVOR0: b IVOR0
+ .align 4
+IVOR1: b _IVOR1
+ .align 4
+IVOR2: b _IVOR2
+ .align 4
+IVOR3: b _IVOR3
+ .align 4
+IVOR4: b _IVOR4
+ .align 4
+IVOR5: b _IVOR5
+ .align 4
+IVOR6: b _IVOR6
+ .align 4
+IVOR7: b _IVOR7
+ .align 4
+IVOR8: b _IVOR8
+ .align 4
+IVOR9: b _IVOR9
+ .align 4
+IVOR10: b _IVOR10
+ .align 4
+IVOR11: b _IVOR11
+ .align 4
+IVOR12: b _IVOR12
+ .align 4
+IVOR13: b _IVOR13
+ .align 4
+IVOR14: b _IVOR14
+ .align 4
+IVOR15: b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+ .weak _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h new file mode 100644 index 000000000..51f6824b7 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Dxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Dxx.
+ *
+ * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Dxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 155
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Pxx/boot.h b/os/common/ports/e200/devices/SPC560Pxx/boot.h new file mode 100644 index 000000000..56bc4a565 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Pxx/boot.h @@ -0,0 +1,118 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC560Pxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_ME 0x00001000
+#define MSR_DE 0x00000200
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Pxx/boot.s b/os/common/ports/e200/devices/SPC560Pxx/boot.s new file mode 100644 index 000000000..bbeab7dcd --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Pxx/boot.s @@ -0,0 +1,214 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/boot.s
+ * @brief SPC560Pxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+ .long 0x015A0000
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ blr
+
+ .section .ivors, "ax"
+
+ .globl IVORS
+IVORS:
+IVOR0: b IVOR0
+ .align 4
+IVOR1: b _IVOR1
+ .align 4
+IVOR2: b _IVOR2
+ .align 4
+IVOR3: b _IVOR3
+ .align 4
+IVOR4: b _IVOR4
+ .align 4
+IVOR5: b _IVOR5
+ .align 4
+IVOR6: b _IVOR6
+ .align 4
+IVOR7: b _IVOR7
+ .align 4
+IVOR8: b _IVOR8
+ .align 4
+IVOR9: b _IVOR9
+ .align 4
+IVOR10: b _IVOR10
+ .align 4
+IVOR11: b _IVOR11
+ .align 4
+IVOR12: b _IVOR12
+ .align 4
+IVOR13: b _IVOR13
+ .align 4
+IVOR14: b _IVOR14
+ .align 4
+IVOR15: b _IVOR15
+
+ .section .handlers, "ax"
+
+ /*
+ * Default IVOR handlers.
+ */
+ .align 2
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
+ .weak _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h new file mode 100644 index 000000000..83cc43a75 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Pxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC560Pxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC560Pxx.
+ *
+ * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC560Pxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z0
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 20
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS FALSE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE FALSE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER FALSE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 261
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC563Mxx/boot.h b/os/common/ports/e200/devices/SPC563Mxx/boot.h new file mode 100644 index 000000000..52bee9f45 --- /dev/null +++ b/os/common/ports/e200/devices/SPC563Mxx/boot.h @@ -0,0 +1,119 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC563Mxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC563Mxx/boot.s b/os/common/ports/e200/devices/SPC563Mxx/boot.s new file mode 100644 index 000000000..7b9dc0e10 --- /dev/null +++ b/os/common/ports/e200/devices/SPC563Mxx/boot.s @@ -0,0 +1,188 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/boot.s
+ * @brief SPC563Mxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_coreinit:
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h b/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h new file mode 100644 index 000000000..29bc22eb7 --- /dev/null +++ b/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC563Mxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC563Mxx.
+ *
+ * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC563Mxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z3
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 360
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC564Axx/boot.h b/os/common/ports/e200/devices/SPC564Axx/boot.h new file mode 100644 index 000000000..7b105153a --- /dev/null +++ b/os/common/ports/e200/devices/SPC564Axx/boot.h @@ -0,0 +1,242 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC564Axx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC564Axx/boot.s b/os/common/ports/e200/devices/SPC564Axx/boot.s new file mode 100644 index 000000000..ef7e4df91 --- /dev/null +++ b/os/common/ports/e200/devices/SPC564Axx/boot.s @@ -0,0 +1,353 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/boot.s
+ * @brief SPC564Axx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ isync
+ blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB1.
+ */
+ lis %r3, 0
+ mtspr 625, %r3 /* MAS1 */
+ mtspr 626, %r3 /* MAS2 */
+ mtspr 627, %r3 /* MAS3 */
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB0 allocated to internal RAM.
+ */
+ lis %r3, TLB0_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB0_MAS1@h
+ ori %r3, %r3, TLB0_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB0_MAS2@h
+ ori %r3, %r3, TLB0_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB0_MAS3@h
+ ori %r3, %r3, TLB0_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ lis %r3, TLB2_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB2_MAS1@h
+ ori %r3, %r3, TLB2_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB2_MAS2@h
+ ori %r3, %r3, TLB2_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB2_MAS3@h
+ ori %r3, %r3, TLB2_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ lis %r3, TLB3_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB3_MAS1@h
+ ori %r3, %r3, TLB3_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB3_MAS2@h
+ ori %r3, %r3, TLB3_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB3_MAS3@h
+ ori %r3, %r3, TLB3_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB4_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB4_MAS1@h
+ ori %r3, %r3, TLB4_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB4_MAS2@h
+ ori %r3, %r3, TLB4_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB4_MAS3@h
+ ori %r3, %r3, TLB4_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * *Finally* the TLB1 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ lis %r3, TLB1_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB1_MAS1@h
+ ori %r3, %r3, TLB1_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB1_MAS2@h
+ ori %r3, %r3, TLB1_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB1_MAS3@h
+ ori %r3, %r3, TLB1_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ mflr %r4
+ lis %r6, _ramcode@h
+ ori %r6, %r6, _ramcode@l
+ lis %r7, 0x40010000@h
+ mtctr %r7
+ lwz %r3, 0(%r6)
+ stw %r3, 0(%r7)
+ lwz %r3, 4(%r6)
+ stw %r3, 4(%r7)
+ lwz %r3, 8(%r6)
+ stw %r3, 8(%r7)
+ bctrl
+ mtlr %r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, BOOT_LICSR1_DEFAULT@h
+ ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC564Axx/ppcparams.h b/os/common/ports/e200/devices/SPC564Axx/ppcparams.h new file mode 100644 index 000000000..badc1a83b --- /dev/null +++ b/os/common/ports/e200/devices/SPC564Axx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC564Axx/ppcparams.h
+ * @brief PowerPC parameters for the SPC564Axx.
+ *
+ * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC564Axx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 486
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ECxx/boot.h b/os/common/ports/e200/devices/SPC56ECxx/boot.h new file mode 100644 index 000000000..74d0cfe90 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ECxx/boot.h @@ -0,0 +1,252 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC56ECxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
+#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ECxx/boot.s b/os/common/ports/e200/devices/SPC56ECxx/boot.s new file mode 100644 index 000000000..10319e6e2 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ECxx/boot.s @@ -0,0 +1,407 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ECxx/boot.s
+ * @brief SPC56ECxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+#if BOOT_PERFORM_CORE_INIT
+ bl _coreinit
+#endif
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ isync
+ blr
+
+ .align 2
+_coreinit:
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ lis %r3, 0
+ mtspr 625, %r3 /* MAS1 */
+ mtspr 626, %r3 /* MAS2 */
+ mtspr 627, %r3 /* MAS3 */
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ lis %r3, TLB1_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB1_MAS1@h
+ ori %r3, %r3, TLB1_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB1_MAS2@h
+ ori %r3, %r3, TLB1_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB1_MAS3@h
+ ori %r3, %r3, TLB1_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ lis %r3, TLB2_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB2_MAS1@h
+ ori %r3, %r3, TLB2_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB2_MAS2@h
+ ori %r3, %r3, TLB2_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB2_MAS3@h
+ ori %r3, %r3, TLB2_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ lis %r3, TLB3_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB3_MAS1@h
+ ori %r3, %r3, TLB3_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB3_MAS2@h
+ ori %r3, %r3, TLB3_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB3_MAS3@h
+ ori %r3, %r3, TLB3_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB4_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB4_MAS1@h
+ ori %r3, %r3, TLB4_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB4_MAS2@h
+ ori %r3, %r3, TLB4_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB4_MAS3@h
+ ori %r3, %r3, TLB4_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB5_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB5_MAS1@h
+ ori %r3, %r3, TLB5_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB5_MAS2@h
+ ori %r3, %r3, TLB5_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB5_MAS3@h
+ ori %r3, %r3, TLB5_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, %r31
+ mtspr 9, %r31 /* CTR */
+ mtspr 22, %r31 /* DEC */
+ mtspr 26, %r31 /* SRR0-1 */
+ mtspr 27, %r31
+ mtspr 54, %r31 /* DECAR */
+ mtspr 58, %r31 /* CSRR0-1 */
+ mtspr 59, %r31
+ mtspr 61, %r31 /* DEAR */
+ mtspr 256, %r31 /* USPRG0 */
+ mtspr 272, %r31 /* SPRG1-7 */
+ mtspr 273, %r31
+ mtspr 274, %r31
+ mtspr 275, %r31
+ mtspr 276, %r31
+ mtspr 277, %r31
+ mtspr 278, %r31
+ mtspr 279, %r31
+ mtspr 285, %r31 /* TBU */
+ mtspr 284, %r31 /* TBL */
+#if 0
+ mtspr 318, %r31 /* DVC1-2 */
+ mtspr 319, %r31
+#endif
+ mtspr 562, %r31 /* DBCNT */
+ mtspr 570, %r31 /* MCSRR0 */
+ mtspr 571, %r31 /* MCSRR1 */
+ mtspr 604, %r31 /* SPRG8-9 */
+ mtspr 605, %r31
+
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ lis %r3, TLB0_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB0_MAS1@h
+ ori %r3, %r3, TLB0_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB0_MAS2@h
+ ori %r3, %r3, TLB0_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB0_MAS3@h
+ ori %r3, %r3, TLB0_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ mflr %r4
+ lis %r6, _ramcode@h
+ ori %r6, %r6, _ramcode@l
+ lis %r7, 0x40010000@h
+ mtctr %r7
+ lwz %r3, 0(%r6)
+ stw %r3, 0(%r7)
+ lwz %r3, 4(%r6)
+ stw %r3, 4(%r7)
+ lwz %r3, 8(%r6)
+ stw %r3, 8(%r7)
+ bctrl
+ mtlr %r4
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, BOOT_LICSR1_DEFAULT@h
+ ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h b/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h new file mode 100644 index 000000000..d46216e73 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ECxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ECxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC56ECxx.
+ *
+ * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC56ECxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 279
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ELxx/boot.h b/os/common/ports/e200/devices/SPC56ELxx/boot.h new file mode 100644 index 000000000..9bc54e695 --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ELxx/boot.h @@ -0,0 +1,252 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file boot.h
+ * @brief Boot parameters for the SPC56ELxx.
+ * @{
+ */
+
+#ifndef _BOOT_H_
+#define _BOOT_H_
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/**
+ * @name MASx registers definitions
+ * @{
+ */
+#define MAS0_TBLMAS_TBL 0x10000000
+#define MAS0_ESEL_MASK 0x000F0000
+#define MAS0_ESEL(n) ((n) << 16)
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID_MASK 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSISE_MASK 0x00000F80
+#define MAS1_TSISE_1K 0x00000000
+#define MAS1_TSISE_2K 0x00000080
+#define MAS1_TSISE_4K 0x00000100
+#define MAS1_TSISE_8K 0x00000180
+#define MAS1_TSISE_16K 0x00000200
+#define MAS1_TSISE_32K 0x00000280
+#define MAS1_TSISE_64K 0x00000300
+#define MAS1_TSISE_128K 0x00000380
+#define MAS1_TSISE_256K 0x00000400
+#define MAS1_TSISE_512K 0x00000480
+#define MAS1_TSISE_1M 0x00000500
+#define MAS1_TSISE_2M 0x00000580
+#define MAS1_TSISE_4M 0x00000600
+#define MAS1_TSISE_8M 0x00000680
+#define MAS1_TSISE_16M 0x00000700
+#define MAS1_TSISE_32M 0x00000780
+#define MAS1_TSISE_64M 0x00000800
+#define MAS1_TSISE_128M 0x00000880
+#define MAS1_TSISE_256M 0x00000900
+#define MAS1_TSISE_512M 0x00000980
+#define MAS1_TSISE_1G 0x00000A00
+#define MAS1_TSISE_2G 0x00000A80
+#define MAS1_TSISE_4G 0x00000B00
+
+#define MAS2_EPN_MASK 0xFFFFFC00
+#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
+#define MAS2_EBOOK 0x00000000
+#define MAS2_VLE 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN_MASK 0xFFFFFC00
+#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+/** @} */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BPRED_MASK 0x00000006
+#define BUCSR_BPRED_0 0x00000000
+#define BUCSR_BPRED_1 0x00000002
+#define BUCSR_BPRED_2 0x00000004
+#define BUCSR_BPRED_3 0x00000006
+#define BUCSR_BALLOC_MASK 0x00000030
+#define BUCSR_BALLOC_0 0x00000000
+#define BUCSR_BALLOC_1 0x00000010
+#define BUCSR_BALLOC_2 0x00000020
+#define BUCSR_BALLOC_3 0x00000030
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name LICSR1 registers definitions
+ * @{
+ */
+#define LICSR1_ICE 0x00000001
+#define LICSR1_ICINV 0x00000002
+#define LICSR1_ICORG 0x00000010
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*
+ * TLB default settings.
+ */
+#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
+#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
+#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
+#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
+#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
+#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
+#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
+ MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
+ MAS3_UR | MAS3_SR)
+
+#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
+#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
+#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
+#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
+#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
+#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
+#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
+#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
+#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
+#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
+ MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
+
+/*
+ * BUCSR default settings.
+ */
+#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
+ BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
+#endif
+
+/*
+ * LICSR1 default settings.
+ */
+#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
+#endif
+
+/*
+ * MSR default settings.
+ */
+#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
+#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+#endif
+
+/*
+ * Boot default settings.
+ */
+#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
+#define BOOT_PERFORM_CORE_INIT 1
+#endif
+
+/*
+ * VLE mode default settings.
+ */
+#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
+#define BOOT_USE_VLE 1
+#endif
+
+/*
+ * RAM relocation flag.
+ */
+#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
+#define BOOT_RELOCATE_IN_RAM 0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* _BOOT_H_ */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ELxx/boot.s b/os/common/ports/e200/devices/SPC56ELxx/boot.s new file mode 100644 index 000000000..2a6c57f2c --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ELxx/boot.s @@ -0,0 +1,409 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ELxx/boot.s
+ * @brief SPC56ELxx boot-related code.
+ *
+ * @addtogroup PPC_BOOT
+ * @{
+ */
+
+#include "boot.h"
+
+#if !defined(__DOXYGEN__)
+
+ /* BAM record.*/
+ .section .boot, "ax"
+
+#if BOOT_USE_VLE
+ .long 0x015A0000
+#else
+ .long 0x005A0000
+#endif
+ .long _reset_address
+
+ .align 2
+ .globl _reset_address
+ .type _reset_address, @function
+_reset_address:
+ bl _coreinit
+ bl _ivinit
+
+#if BOOT_RELOCATE_IN_RAM
+ /*
+ * Image relocation in RAM.
+ */
+ lis %r4, __ram_reloc_start__@h
+ ori %r4, %r4, __ram_reloc_start__@l
+ lis %r5, __ram_reloc_dest__@h
+ ori %r5, %r5, __ram_reloc_dest__@l
+ lis %r6, __ram_reloc_end__@h
+ ori %r6, %r6, __ram_reloc_end__@l
+.relloop:
+ cmpl cr0, %r4, %r6
+ bge cr0, .relend
+ lwz %r7, 0(%r4)
+ addi %r4, %r4, 4
+ stw %r7, 0(%r5)
+ addi %r5, %r5, 4
+ b .relloop
+.relend:
+ lis %r3, _boot_address@h
+ ori %r3, %r3, _boot_address@l
+ mtctr %r3
+ bctrl
+#else
+ b _boot_address
+#endif
+
+#if BOOT_PERFORM_CORE_INIT
+ .align 2
+_ramcode:
+ tlbwe
+ isync
+ blr
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ .align 2
+_coreinit:
+#if BOOT_PERFORM_CORE_INIT
+ /*
+ * Invalidating all TLBs except TLB0.
+ */
+ lis %r3, 0
+ mtspr 625, %r3 /* MAS1 */
+ mtspr 626, %r3 /* MAS2 */
+ mtspr 627, %r3 /* MAS3 */
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+ lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
+ mtspr 624, %r3 /* MAS0 */
+ tlbwe
+
+ /*
+ * TLB1 allocated to internal RAM.
+ */
+ lis %r3, TLB1_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB1_MAS1@h
+ ori %r3, %r3, TLB1_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB1_MAS2@h
+ ori %r3, %r3, TLB1_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB1_MAS3@h
+ ori %r3, %r3, TLB1_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB2 allocated to internal Peripherals Bridge A.
+ */
+ lis %r3, TLB2_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB2_MAS1@h
+ ori %r3, %r3, TLB2_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB2_MAS2@h
+ ori %r3, %r3, TLB2_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB2_MAS3@h
+ ori %r3, %r3, TLB2_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB3 allocated to internal Peripherals Bridge B.
+ */
+ lis %r3, TLB3_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB3_MAS1@h
+ ori %r3, %r3, TLB3_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB3_MAS2@h
+ ori %r3, %r3, TLB3_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB3_MAS3@h
+ ori %r3, %r3, TLB3_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB4 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB4_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB4_MAS1@h
+ ori %r3, %r3, TLB4_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB4_MAS2@h
+ ori %r3, %r3, TLB4_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB4_MAS3@h
+ ori %r3, %r3, TLB4_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * TLB5 allocated to on-platform peripherals.
+ */
+ lis %r3, TLB5_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB5_MAS1@h
+ ori %r3, %r3, TLB5_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB5_MAS2@h
+ ori %r3, %r3, TLB5_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB5_MAS3@h
+ ori %r3, %r3, TLB5_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ tlbwe
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, %r31
+ mtspr 9, %r31 /* CTR */
+ mtspr 22, %r31 /* DEC */
+ mtspr 26, %r31 /* SRR0-1 */
+ mtspr 27, %r31
+ mtspr 54, %r31 /* DECAR */
+ mtspr 58, %r31 /* CSRR0-1 */
+ mtspr 59, %r31
+ mtspr 61, %r31 /* DEAR */
+ mtspr 256, %r31 /* USPRG0 */
+ mtspr 272, %r31 /* SPRG1-7 */
+ mtspr 273, %r31
+ mtspr 274, %r31
+ mtspr 275, %r31
+ mtspr 276, %r31
+ mtspr 277, %r31
+ mtspr 278, %r31
+ mtspr 279, %r31
+ mtspr 285, %r31 /* TBU */
+ mtspr 284, %r31 /* TBL */
+#if 0
+ mtspr 318, %r31 /* DVC1-2 */
+ mtspr 319, %r31
+#endif
+ mtspr 562, %r31 /* DBCNT */
+ mtspr 570, %r31 /* MCSRR0 */
+ mtspr 571, %r31 /* MCSRR1 */
+ mtspr 604, %r31 /* SPRG8-9 */
+ mtspr 605, %r31
+
+#if BOOT_PERFORM_CORE_INIT
+ /*
+ * *Finally* the TLB0 is re-allocated to flash, note, the final phase
+ * is executed from RAM.
+ */
+ lis %r3, TLB0_MAS0@h
+ mtspr 624, %r3 /* MAS0 */
+ lis %r3, TLB0_MAS1@h
+ ori %r3, %r3, TLB0_MAS1@l
+ mtspr 625, %r3 /* MAS1 */
+ lis %r3, TLB0_MAS2@h
+ ori %r3, %r3, TLB0_MAS2@l
+ mtspr 626, %r3 /* MAS2 */
+ lis %r3, TLB0_MAS3@h
+ ori %r3, %r3, TLB0_MAS3@l
+ mtspr 627, %r3 /* MAS3 */
+ mflr %r4
+ lis %r6, _ramcode@h
+ ori %r6, %r6, _ramcode@l
+ lis %r7, 0x40010000@h
+ mtctr %r7
+ lwz %r3, 0(%r6)
+ stw %r3, 0(%r7)
+ lwz %r3, 4(%r6)
+ stw %r3, 4(%r7)
+ lwz %r3, 8(%r6)
+ stw %r3, 8(%r7)
+ bctrl
+ mtlr %r4
+#endif /* BOOT_PERFORM_CORE_INIT */
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BOOT_BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ /*
+ * Cache invalidated and then enabled.
+ */
+ li %r3, LICSR1_ICINV
+ mtspr 1011, %r3 /* LICSR1 */
+.inv: mfspr %r3, 1011 /* LICSR1 */
+ andi. %r3, %r3, LICSR1_ICINV
+ bne .inv
+ lis %r3, BOOT_LICSR1_DEFAULT@h
+ ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
+ mtspr 1011, %r3 /* LICSR1 */
+
+ blr
+
+ /*
+ * Exception vectors initialization.
+ */
+ .align 2
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, BOOT_MSR_DEFAULT@h
+ ori %r3, %r3, BOOT_MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ .section .handlers, "ax"
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _unhandled_exception
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h b/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h new file mode 100644 index 000000000..c588a1d8e --- /dev/null +++ b/os/common/ports/e200/devices/SPC56ELxx/ppcparams.h @@ -0,0 +1,77 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC56ELxx/ppcparams.h
+ * @brief PowerPC parameters for the SPC56ELxx.
+ *
+ * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
+ * @ingroup PPC_SPECIFIC
+ * @details This file contains the PowerPC specific parameters for the
+ * SPC56ELxx platform.
+ * @{
+ */
+
+#ifndef _PPCPARAMS_H_
+#define _PPCPARAMS_H_
+
+/**
+ * @brief PPC core model.
+ */
+#define PPC_VARIANT PPC_VARIANT_e200z4
+
+/**
+ * @brief Number of writable bits in IVPR register.
+ */
+#define PPC_IVPR_BITS 16
+
+/**
+ * @brief IVORx registers support.
+ */
+#define PPC_SUPPORTS_IVORS TRUE
+
+/**
+ * @brief Book E instruction set support.
+ */
+#define PPC_SUPPORTS_BOOKE TRUE
+
+/**
+ * @brief VLE instruction set support.
+ */
+#define PPC_SUPPORTS_VLE TRUE
+
+/**
+ * @brief Supports VLS Load/Store Multiple Volatile instructions.
+ */
+#define PPC_SUPPORTS_VLE_MULTI TRUE
+
+/**
+ * @brief Supports the decrementer timer.
+ */
+#define PPC_SUPPORTS_DECREMENTER TRUE
+
+/**
+ * @brief Number of interrupt sources.
+ */
+#define PPC_NUM_VECTORS 256
+
+#endif /* _PPCPARAMS_H_ */
+
+/** @} */
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