diff options
Diffstat (limited to 'os/hal/platforms/STM32/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 50 |
1 files changed, 29 insertions, 21 deletions
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index 7878bb518..b2a7a0fe5 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -146,43 +146,51 @@ void stm32_clock_init(void) { */
void stm32_clock_init(void) {
- /* HSI setup, it enforces the reset situation in order to handle possible
- problems with JTAG probes and re-initializations.*/
+ /* HSI setup.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
+ RCC->CFGR = 0;
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
- RCC->CFGR = 0; /* CFGR reset value. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is the source.*/
- RCC->CFGR2 = 0;
- /* HSE setup, it is only performed if the HSE clock is selected as source
- of the system clock (directly or through the PLLs).*/
-#if (STM32_SW == STM32_SW_HSE) || \
- ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
+ /* HSE setup, it is only performed if the current configuration uses
+ it somehow.*/
+#if STM32_ACTIVATE_PLL2 || \
+ STM32_ACTIVATE_PLL3 || \
+ (STM32_SW == STM32_SW_HSE) || \
+ ((STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE) && \
+ (STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE is stable. */
#endif
- /* PLL2 setup, it is only performed if the PLL2 clock is selected as source
- for the PLL clock else it is left disabled.*/
-#if STM32_SW == STM32_SW_PLL
-#if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
- RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL;
- RCC->CR |= RCC_CR_PLL2ON;
+ /* Settings of various dividers and multipliers in CFGR2.*/
+ RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
+ STM32_PREDIV1 | STM32_PREDIV1SRC;
+
+ /* PLL2 setup, if activated.*/
+#if STM32_ACTIVATE_PLL2
+ RCC->CR |= RCC_CR_PLL2ON;
while (!(RCC->CR & RCC_CR_PLL2RDY))
- ; /* Waits until PLL is stable. */
+ ; /* Waits until PLL2 is stable. */
#endif
- /* PLL setup, it is only performed if the PLL is the selected source of
- the system clock else it is left disabled.*/
- RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC;
- RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
- RCC->CR |= RCC_CR_PLLON;
+ /* PLL3 setup, if activated.*/
+#if STM32_ACTIVATE_PLL3
+ RCC->CR |= RCC_CR_PLL3ON;
+ while (!(RCC->CR & RCC_CR_PLL3RDY))
+ ; /* Waits until PLL3 is stable. */
+#endif
+
+ /* PLL1 setup, if activated.*/
+#if STM32_ACTIVATE_PLL1
+ RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
- ; /* Waits until PLL2 is stable. */
+ ; /* Waits until PLL1 is stable. */
#endif
/* Clock settings.*/
|