diff options
Diffstat (limited to 'os/hal/platforms/STM32/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 100 |
1 files changed, 88 insertions, 12 deletions
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index b56e6bbbb..9dc66a3f0 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -90,33 +90,109 @@ void hal_lld_init(void) { * @brief STM32 clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
*/
+#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
+ defined(STM32F10X_HD) || defined(__DOXYGEN__)
+/*
+ * Clocks initialization for the LD, MD and HD sub-families.
+ */
void stm32_clock_init(void) {
- /* HSI setup.*/
- RCC->CR = 0x00000083; /* Reset value, HSI ON. */
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
+ RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
- ; /* Waits until HSI stable. */
- /* HSE setup.*/
+ ; /* Wait until HSI is stable. */
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ; /* Wait until HSI is the source.*/
+
+ /* HSE setup, it is only performed if the HSE clock is selected as source
+ of the system clock (directly or through the PLL).*/
+#if (STM32_SW == STM32_SW_HSE) || \
+ ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
- ; /* Waits until HSE stable. */
+ ; /* Waits until HSE is stable. */
+#endif
+
+ /* PLL setup, it is only performed if the PLL is the selected source of
+ the system clock else it is left disabled.*/
#if STM32_SW == STM32_SW_PLL
- /* PLL setup, only if the PLL is the selected source of the system clock
- else it is left disabled.*/
- RCC->CFGR = ((STM32_PLLMUL - 2) << 18) | STM32_PLLXTPRE | STM32_PLLSRC;
- RCC->CR |= RCC_CR_PLLON;
+ RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
- ; /* Waits until PLL stable. */
+ ; /* Waits until PLL is stable. */
#endif
+
/* Clock settings.*/
- RCC->CFGR = ((STM32_PLLMUL - 2) << 18) | STM32_PLLXTPRE | STM32_PLLSRC |
+ RCC->CFGR = STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
- RCC->CFGR |= STM32_SW; /* Switches on the clock sources. */
+
+ /* Switching on the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
+#endif
}
+#elif defined(STM32F10X_CL)
+/*
+ * Clocks initialization for the CL sub-family.
+ */
+void stm32_clock_init(void) {
+
+ /* HSI setup, it enforces the reset situation in order to handle possible
+ problems with JTAG probes and re-initializations.*/
+ RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
+ while (!(RCC->CR & RCC_CR_HSIRDY))
+ ; /* Wait until HSI is stable. */
+ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
+ RCC->CFGR = 0; /* CFGR reset value. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+ ; /* Wait until HSI is the source.*/
+ RCC->CFGR2 = 0;
+
+ /* HSE setup, it is only performed if the HSE clock is selected as source
+ of the system clock (directly or through the PLLs).*/
+#if (STM32_SW == STM32_SW_HSE) || \
+ ((STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_PREDIV1))
+ RCC->CR |= RCC_CR_HSEON;
+ while (!(RCC->CR & RCC_CR_HSERDY))
+ ; /* Waits until HSE is stable. */
+#endif
+
+ /* PLL2 setup, it is only performed if the PLL2 clock is selected as source
+ for the PLL clock else it is left disabled.*/
+#if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2
+ RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL;
+ RCC->CR |= RCC_CR_PLL2ON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL is stable. */
+#endif
+
+ /* PLL setup, it is only performed if the PLL is the selected source of
+ the system clock else it is left disabled.*/
+#if STM32_SW == STM32_SW_PLL
+ RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC;
+ RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLL2RDY))
+ ; /* Waits until PLL2 is stable. */
+#endif
+
+ /* Switching on the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ ;
+#endif
+}
+#else
+void stm32_clock_init(void) {}
+#endif
/** @} */
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