diff options
Diffstat (limited to 'os/hal/platforms/STM32/spi_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32/spi_lld.c | 269 |
1 files changed, 103 insertions, 166 deletions
diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index dfe72822a..d8ae657a7 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -1,5 +1,6 @@ /*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
@@ -66,8 +67,8 @@ static uint16_t dummyrx; * @param[in] spip pointer to the @p SPIDriver object
*/
#define dma_stop(spip) { \
- dmaChannelDisable(spip->spd_dmatx); \
- dmaChannelDisable(spip->spd_dmarx); \
+ dmaChannelDisable(spip->dmatx); \
+ dmaChannelDisable(spip->dmarx); \
}
/**
@@ -76,16 +77,26 @@ static uint16_t dummyrx; * @param[in] spip pointer to the @p SPIDriver object
*/
#define dma_start(spip) { \
- dmaChannelEnable((spip)->spd_dmarx); \
- dmaChannelEnable((spip)->spd_dmatx); \
+ dmaChannelEnable((spip)->dmarx); \
+ dmaChannelEnable((spip)->dmatx); \
}
/**
- * @brief Shared end-of-transfer service routine.
+ * @brief Shared end-of-rx service routine.
*
* @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] flags pre-shifted content of the ISR register
*/
-static void serve_interrupt(SPIDriver *spip) {
+static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
+
+ /* DMA errors handling.*/
+#if defined(STM32_SPI_DMA_ERROR_HOOK)
+ if ((flags & DMA_ISR_TEIF1) != 0) {
+ STM32_SPI_DMA_ERROR_HOOK(spip);
+ }
+#else
+ (void)flags;
+#endif
/* Stop everything.*/
dma_stop(spip);
@@ -95,114 +106,29 @@ static void serve_interrupt(SPIDriver *spip) { _spi_isr_code(spip);
}
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)
/**
- * @brief SPI1 RX DMA interrupt handler (channel 2).
+ * @brief Shared end-of-tx service routine.
*
- * @isr
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] flags pre-shifted content of the ISR register
*/
-CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
+static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) {
- if ((STM32_DMA1->ISR & DMA_ISR_TEIF2) != 0) {
- STM32_SPI_SPI1_DMA_ERROR_HOOK();
+ /* DMA errors handling.*/
+#if defined(STM32_SPI_DMA_ERROR_HOOK)
+ (void)spip;
+ if ((flags & DMA_ISR_TEIF1) != 0) {
+ STM32_SPI_DMA_ERROR_HOOK(spip);
}
- serve_interrupt(&SPID1);
- dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_2);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief SPI1 TX DMA interrupt handler (channel 3).
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- STM32_SPI_SPI1_DMA_ERROR_HOOK();
- dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_3);
-
- CH_IRQ_EPILOGUE();
-}
+#else
+ (void)spip;
+ (void)flags;
#endif
-
-#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)
-/**
- * @brief SPI2 RX DMA interrupt handler (channel 4).
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- if ((STM32_DMA1->ISR & DMA_ISR_TEIF4) != 0) {
- STM32_SPI_SPI2_DMA_ERROR_HOOK();
- }
- serve_interrupt(&SPID2);
- dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_4);
-
- CH_IRQ_EPILOGUE();
}
-/**
- * @brief SPI2 TX DMA interrupt handler (channel 5).
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- STM32_SPI_SPI2_DMA_ERROR_HOOK();
- dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_5);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)
-/**
- * @brief SPI3 RX DMA interrupt handler (DMA2, channel 1).
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- if ((STM32_DMA2->ISR & DMA_ISR_TEIF1) != 0) {
- STM32_SPI_SPI3_DMA_ERROR_HOOK();
- }
- serve_interrupt(&SPID3);
- dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_1);
-
- CH_IRQ_EPILOGUE();
-}
-
-/**
- * @brief SPI3 TX DMA2 interrupt handler (DMA2, channel 2).
- *
- * @isr
- */
-CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- STM32_SPI_SPI3_DMA_ERROR_HOOK();
- dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_2);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
@@ -218,33 +144,27 @@ void spi_lld_init(void) { dummytx = 0xFFFF;
#if STM32_SPI_USE_SPI1
- RCC->APB2RSTR = RCC_APB2RSTR_SPI1RST;
- RCC->APB2RSTR = 0;
spiObjectInit(&SPID1);
- SPID1.spd_thread = NULL;
- SPID1.spd_spi = SPI1;
- SPID1.spd_dmarx = STM32_DMA1_CH2;
- SPID1.spd_dmatx = STM32_DMA1_CH3;
+ SPID1.thread = NULL;
+ SPID1.spi = SPI1;
+ SPID1.dmarx = STM32_DMA1_CH2;
+ SPID1.dmatx = STM32_DMA1_CH3;
#endif
#if STM32_SPI_USE_SPI2
- RCC->APB1RSTR = RCC_APB1RSTR_SPI2RST;
- RCC->APB1RSTR = 0;
spiObjectInit(&SPID2);
- SPID2.spd_thread = NULL;
- SPID2.spd_spi = SPI2;
- SPID2.spd_dmarx = STM32_DMA1_CH4;
- SPID2.spd_dmatx = STM32_DMA1_CH5;
+ SPID2.thread = NULL;
+ SPID2.spi = SPI2;
+ SPID2.dmarx = STM32_DMA1_CH4;
+ SPID2.dmatx = STM32_DMA1_CH5;
#endif
#if STM32_SPI_USE_SPI3
- RCC->APB1RSTR = RCC_APB1RSTR_SPI3RST;
- RCC->APB1RSTR = 0;
spiObjectInit(&SPID3);
- SPID3.spd_thread = NULL;
- SPID3.spd_spi = SPI3;
- SPID3.spd_dmarx = STM32_DMA2_CH1;
- SPID3.spd_dmatx = STM32_DMA2_CH2;
+ SPID3.thread = NULL;
+ SPID3.spi = SPI3;
+ SPID3.dmarx = STM32_DMA2_CH1;
+ SPID3.dmatx = STM32_DMA2_CH2;
#endif
}
@@ -258,10 +178,14 @@ void spi_lld_init(void) { void spi_lld_start(SPIDriver *spip) {
/* If in stopped state then enables the SPI and DMA clocks.*/
- if (spip->spd_state == SPI_STOP) {
+ if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
- dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
+ /* Note, the DMA must be enabled before the IRQs.*/
+ dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_2,
+ (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip);
+ dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_3,
+ (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip);
NVICEnableVector(DMA1_Channel2_IRQn,
CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY));
NVICEnableVector(DMA1_Channel3_IRQn,
@@ -271,7 +195,11 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
- dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
+ /* Note, the DMA must be enabled before the IRQs.*/
+ dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_4,
+ (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip);
+ dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_5,
+ (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip);
NVICEnableVector(DMA1_Channel4_IRQn,
CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY));
NVICEnableVector(DMA1_Channel5_IRQn,
@@ -281,7 +209,11 @@ void spi_lld_start(SPIDriver *spip) { #endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
- dmaEnable(DMA2_ID); /* NOTE: Must be enabled before the IRQs.*/
+ /* Note, the DMA must be enabled before the IRQs.*/
+ dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_1,
+ (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip);
+ dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_2,
+ (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip);
NVICEnableVector(DMA2_Channel1_IRQn,
CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY));
NVICEnableVector(DMA2_Channel2_IRQn,
@@ -291,23 +223,25 @@ void spi_lld_start(SPIDriver *spip) { #endif
/* DMA setup.*/
- dmaChannelSetPeripheral(spip->spd_dmarx, &spip->spd_spi->DR);
- dmaChannelSetPeripheral(spip->spd_dmatx, &spip->spd_spi->DR);
+ dmaChannelSetPeripheral(spip->dmarx, &spip->spi->DR);
+ dmaChannelSetPeripheral(spip->dmatx, &spip->spi->DR);
}
/* More DMA setup.*/
- if ((spip->spd_config->spc_cr1 & SPI_CR1_DFF) == 0)
- spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
- DMA_CCR1_TEIE; /* 8 bits transfers. */
+ if ((spip->config->cr1 & SPI_CR1_DFF) == 0)
+ spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
+ DMA_CCR1_TEIE; /* 8 bits transfers. */
else
- spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
- DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |
- DMA_CCR1_PSIZE_0; /* 16 bits transfers. */
+ spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
+ DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |
+ DMA_CCR1_PSIZE_0; /* 16 bits transfers. */
/* SPI setup and enable.*/
- spip->spd_spi->CR1 = 0;
- spip->spd_spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
- spip->spd_spi->CR1 = spip->spd_config->spc_cr1 | SPI_CR1_MSTR | SPI_CR1_SPE;
+ spip->spi->CR1 = 0;
+ spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
+ SPI_CR1_SSI;
+ spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
+ spip->spi->CR1 |= SPI_CR1_SPE;
}
/**
@@ -320,16 +254,17 @@ void spi_lld_start(SPIDriver *spip) { void spi_lld_stop(SPIDriver *spip) {
/* If in ready state then disables the SPI clock.*/
- if (spip->spd_state == SPI_READY) {
+ if (spip->state == SPI_READY) {
/* SPI disable.*/
- spip->spd_spi->CR1 = 0;
+ spip->spi->CR1 = 0;
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
NVICDisableVector(DMA1_Channel2_IRQn);
NVICDisableVector(DMA1_Channel3_IRQn);
- dmaDisable(DMA1_ID);
+ dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_2);
+ dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_3);
RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
}
#endif
@@ -337,7 +272,8 @@ void spi_lld_stop(SPIDriver *spip) { if (&SPID2 == spip) {
NVICDisableVector(DMA1_Channel4_IRQn);
NVICDisableVector(DMA1_Channel5_IRQn);
- dmaDisable(DMA1_ID);
+ dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_4);
+ dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_5);
RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
}
#endif
@@ -345,7 +281,8 @@ void spi_lld_stop(SPIDriver *spip) { if (&SPID3 == spip) {
NVICDisableVector(DMA2_Channel1_IRQn);
NVICDisableVector(DMA2_Channel2_IRQn);
- dmaDisable(DMA2_ID);
+ dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_1);
+ dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_2);
RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN;
}
#endif
@@ -361,7 +298,7 @@ void spi_lld_stop(SPIDriver *spip) { */
void spi_lld_select(SPIDriver *spip) {
- palClearPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad);
+ palClearPad(spip->config->ssport, spip->config->sspad);
}
/**
@@ -374,7 +311,7 @@ void spi_lld_select(SPIDriver *spip) { */
void spi_lld_unselect(SPIDriver *spip) {
- palSetPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad);
+ palSetPad(spip->config->ssport, spip->config->sspad);
}
/**
@@ -390,10 +327,10 @@ void spi_lld_unselect(SPIDriver *spip) { */
void spi_lld_ignore(SPIDriver *spip, size_t n) {
- dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, &dummytx,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmarx, n, &dummyrx,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmatx, n, &dummytx,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
}
/**
@@ -414,11 +351,11 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { void spi_lld_exchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
- dmaChannelSetup(spip->spd_dmarx, n, rxbuf,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmarx, n, rxbuf,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, txbuf,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmatx, n, txbuf,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
DMA_CCR1_EN);
}
@@ -437,10 +374,10 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, */
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
- dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, txbuf,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmarx, n, &dummyrx,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmatx, n, txbuf,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
DMA_CCR1_EN);
}
@@ -459,11 +396,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { */
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
- dmaChannelSetup(spip->spd_dmarx, n, rxbuf,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmarx, n, rxbuf,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, &dummytx,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmatx, n, &dummytx,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
}
/**
@@ -480,10 +417,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { */
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
- spip->spd_spi->DR = frame;
- while ((spip->spd_spi->SR & SPI_SR_RXNE) == 0)
+ spip->spi->DR = frame;
+ while ((spip->spi->SR & SPI_SR_RXNE) == 0)
;
- return spip->spd_spi->DR;
+ return spip->spi->DR;
}
#endif /* HAL_USE_SPI */
|