diff options
Diffstat (limited to 'os/hal/platforms/STM32L1xx/hal_lld.h')
| -rw-r--r-- | os/hal/platforms/STM32L1xx/hal_lld.h | 268 |
1 files changed, 230 insertions, 38 deletions
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 97cfde0b7..8d6cfd6f0 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -37,40 +37,52 @@ #ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
-/* Tricks required to make the TRUE/FALSE declaration inside the library
- compatible.*/
-#undef FALSE
-#undef TRUE
-#include "stm32l1xx.h"
-#define FALSE 0
-#define TRUE (!FALSE)
+#include "stm32.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
- * @brief Platform name.
+ * @name Platform identification
+ * @{
*/
-#define PLATFORM_NAME "STM32L Ultra Low Power Medium Density"
+#define PLATFORM_NAME "STM32L1 Ultra Low Power Medium Density"
+/** @} */
+/**
+ * @name Internal clock sources
+ * @{
+ */
#define STM32_HSICLK 16000000 /**< High speed internal clock. */
#define STM32_LSICLK 38000 /**< Low speed internal clock. */
+/** @} */
-/* PWR_CR register bits definitions.*/
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
#define STM32_VOS_MASK (3 << 11) /**< Core voltage mask. */
#define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
+/** @} */
-/* RCC_CR register bits definitions.*/
+/**
+ * @name RCC_CR register bits definitions
+ * @{
+ */
#define STM32_RTCPRE_MASK (3 << 29) /**< RTCPRE mask. */
#define STM32_RTCPRE_DIV2 (0 << 29) /**< HSE divided by 2. */
#define STM32_RTCPRE_DIV4 (1 << 29) /**< HSE divided by 4. */
#define STM32_RTCPRE_DIV8 (2 << 29) /**< HSE divided by 2. */
#define STM32_RTCPRE_DIV16 (3 << 29) /**< HSE divided by 16. */
+/** @} */
-/* RCC_CFGR register bits definitions.*/
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
#define STM32_SW_HSI (1 << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
@@ -115,8 +127,12 @@ #define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */
#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */
+/** @} */
-/* RCC_ICSCR register bits definitions.*/
+/**
+ * @name RCC_ICSCR register bits definitions
+ * @{
+ */
#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
#define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */
#define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */
@@ -125,29 +141,51 @@ #define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
+/** @} */
-/* RCC_CSR register bits definitions.*/
+/**
+ * @name RCC_CSR register bits definitions
+ * @{
+ */
#define STM32_RTCSEL_MASK (3 << 16) /**< RTC source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 16) /**< No RTC source. */
#define STM32_RTCSEL_LSE (1 << 16) /**< RTC source is LSE. */
#define STM32_RTCSEL_LSI (2 << 16) /**< RTC source is LSI. */
#define STM32_RTCSEL_HSEDIV (3 << 16) /**< RTC source is HSE divided. */
+/** @} */
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
-/* STM32L1xx capabilities.*/
+/**
+ * @name STM32L1xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
+/* CAN attributes.*/
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
+/* DAC attributes.*/
#define STM32_HAS_DAC TRUE
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
#define STM32_HAS_DMA1 TRUE
#define STM32_HAS_DMA2 FALSE
+/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 23
+
+/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
@@ -156,18 +194,53 @@ #define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x00000000
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00000000
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN 0x00000000
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_I2C3 FALSE
+#define STM32_I2C3_RX_DMA_MSK 0
+#define STM32_I2C3_RX_DMA_CHN 0x00000000
+#define STM32_I2C3_TX_DMA_MSK 0
+#define STM32_I2C3_TX_DMA_CHN 0x00000000
+
+/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
+/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
+/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN 0x00000000
+#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN 0x00000000
+#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_SPI3 FALSE
+#define STM32_SPI3_RX_DMA_MSK 0
+#define STM32_SPI3_RX_DMA_CHN 0x00000000
+#define STM32_SPI3_TX_DMA_MSK 0
+#define STM32_SPI3_TX_DMA_CHN 0x00000000
+/* TIM attributes.*/
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM2 TRUE
#define STM32_HAS_TIM3 TRUE
@@ -186,20 +259,116 @@ #define STM32_HAS_TIM16 FALSE
#define STM32_HAS_TIM17 FALSE
+/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 TRUE
-#define STM32_HAS_UART3 FALSE
-#define STM32_HAS_UART4 FALSE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+#define STM32_HAS_UART4 FALSE
+#define STM32_UART4_RX_DMA_MSK 0
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK 0
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART5 FALSE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
+
+/* USB attributes.*/
#define STM32_HAS_USB TRUE
#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Platform specific friendly IRQ names. */
+/*===========================================================================*/
+
+/**
+ * @name IRQ VECTOR names
+ * @{
+ */
+#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
+#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
+ detect. */
+#define TAMPER_STAMP_IRQHandler Vector48 /**< Tamper and Time Stamp
+ through EXTI. */
+#define RTC_WKUP_IRQHandler Vector4C /**< RTC Wakeup Timer through
+ EXTI. */
+#define FLASH_IRQHandler Vector50 /**< Flash. */
+#define RCC_IRQHandler Vector54 /**< RCC. */
+#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
+#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
+#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
+#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
+#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
+#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
+#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
+#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
+#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
+#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
+#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
+#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
+#define ADC1_IRQHandler Vector88 /**< ADC1. */
+#define USB_HP_IRQHandler Vector8C /**< USB High Priority. */
+#define USB_LP_IRQHandler Vector90 /**< USB Low Priority. */
+#define DAC_IRQHandler Vector94 /**< DAC. */
+#define COMP_IRQHandler Vector98 /**< Comparator through EXTI. */
+#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
+#define TIM9_IRQHandler VectorA0 /**< TIM9. */
+#define TIM10_IRQHandler VectorA4 /**< TIM10. */
+#define TIM11_IRQHandler VectorA8 /**< TIM11. */
+#define LCD_IRQHandler VectorAC /**< LCD. */
+#define TIM2_IRQHandler VectorB0 /**< TIM2. */
+#define TIM3_IRQHandler VectorB4 /**< TIM3. */
+#define TIM4_IRQHandler VectorB8 /**< TIM4. */
+#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
+#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
+#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
+#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */
+#define SPI1_IRQHandler VectorCC /**< SPI1. */
+#define SPI2_IRQHandler VectorD0 /**< SPI2. */
+#define USART1_IRQHandler VectorD4 /**< USART1. */
+#define USART2_IRQHandler VectorD8 /**< USART2. */
+#define USART3_IRQHandler VectorDC /**< USART3. */
+#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
+#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */
+#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */
+#define TIM6_IRQHandler VectorEC /**< TIM6. */
+#define TIM7_IRQHandler VectorF0 /**< TIM7. */
+/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
+ * @name Configuration options
+ * @{
+ */
+/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
@@ -357,6 +526,7 @@ #if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCPRE STM32_RTCPRE_DIV2
#endif
+/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
@@ -365,19 +535,34 @@ /* Voltage related limits.*/
#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
/**
- * @brief Maximum HSECLK at current voltage setting.
+ * @brief Maximum HSE clock frequency at current voltage setting.
*/
-#define STM32_HSECLK_MAX 32000000#if
+#define STM32_HSECLK_MAX 32000000
/**
- * @brief Maximum SYSCLK at current voltage setting.
+ * @brief Maximum SYSCLK clock frequency at current voltage setting.
*/
#define STM32_SYSCLK_MAX 32000000
/**
- * @brief Maximum PLLCLKOUT at current voltage setting.
+ * @brief Maximum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MAX 96000000
+
+/**
+ * @brief Minimum VCO clock frequency at current voltage setting.
+ */
+#define STM32_PLLVCO_MIN 6000000
+
+/**
+ * @brief Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX 32000000
+
+/**
+ * @brief Maximum APB2 clock frequency.
*/
-#define STM32_PLLCLKOUT_MAX 96000000
+#define STM32_PCLK2_MAX 32000000
/**
* @brief Maximum frequency not requiring a wait state for flash accesses.
@@ -392,13 +577,19 @@ #elif STM32_VOS == STM32_VOS_1P5
#define STM32_HSECLK_MAX 16000000
#define STM32_SYSCLK_MAX 16000000
-#define STM32_PLLCLKOUT_MAX 48000000
+#define STM32_PLLVCO_MAX 48000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PCLK1_MAX 16000000
+#define STM32_PCLK2_MAX 16000000
#define STM32_0WS_THRESHOLD 8000000
#define STM32_HSI_AVAILABLE TRUE
#elif STM32_VOS == STM32_VOS_1P2
#define STM32_HSECLK_MAX 4000000
#define STM32_SYSCLK_MAX 4000000
-#define STM32_PLLCLKOUT_MAX 24000000
+#define STM32_PLLVCO_MAX 24000000
+#define STM32_PLLVCO_MIN 6000000
+#define STM32_PCLK1_MAX 4000000
+#define STM32_PCLK2_MAX 4000000
#define STM32_0WS_THRESHOLD 2000000
#define STM32_HSI_AVAILABLE FALSE
#else
@@ -458,11 +649,11 @@ #if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
#error "STM32_LSECLK outside acceptable range (1...1000KHz)"
#endif
-#else /* !#if STM32_LSE_ENABLED */
+#else /* !STM32_LSE_ENABLED */
#if STM_RTCCLK == STM32_LSECLK
#error "required LSE clock is not enabled"
#endif
-#endif /* !#if STM32_LSE_ENABLED */
+#endif /* !STM32_LSE_ENABLED */
/* PLL related checks.*/
#if STM32_USB_CLOCK_ENABLED || \
@@ -537,8 +728,8 @@ #define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
/* PLL output frequency range check.*/
-#if (STM32_PLLVCO < 6000000) || (STM32_PLLVCO > 96000000)
-#error "STM32_PLLVCO outside acceptable range (6...96MHz)"
+#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
+#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
#endif
/**
@@ -643,8 +834,8 @@ #endif
/* APB1 frequency check.*/
-#if STM32_PCLK2 > STM32_SYSCLK_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
#endif
/**
@@ -665,8 +856,8 @@ #endif
/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_SYSCLK_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
#endif
/**
@@ -711,13 +902,13 @@ * @brief HSE divider toward RTC clock.
*/
#if (STM32_RTCPRE == STM32_RTCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (HSECLK / 2)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 2)
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV4) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (HSECLK / 4)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 4)
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV8) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (HSECLK / 8)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 8)
#elif (STM32_RTCPRE == STM32_RTCPRE_DIV16) || defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (HSECLK / 16)
+#define STM32_HSEDIVCLK (STM32_HSECLK / 16)
#else
#error "invalid STM32_RTCPRE value specified"
#endif
@@ -787,8 +978,9 @@ /* External declarations. */
/*===========================================================================*/
-/* STM32 DMA support code.*/
+/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
+#include "stm32_rcc.h"
#ifdef __cplusplus
extern "C" {
|