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+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @defgroup STM8S STM8S Drivers
+ * @details This section describes all the supported drivers on the STM8S
+ *          platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup STM8S_HAL STM8S Initialization Support
+ * @details The STM8S HAL support is responsible for system initialization.
+ *
+ * @section stm8s_hal_1 Supported HW resources
+ * - CLK.
+ * .
+ * @section stm8s_hal_2 STM8S HAL driver implementation features
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * .
+ * @ingroup STM8S
+ */
+
+/**
+ * @defgroup STM8S_PAL STM8S PAL Support
+ * @details The STM8S PAL driver uses the GPIO peripherals.
+ *
+ * @section stm8s_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOE.
+ * - GPIOF.
+ * - GPIOG (where present).
+ * - GPIOH (where present).
+ * - GPIOI (where present).
+ * .
+ * @section stm8s_pal_2 STM8S PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 8 bits wide ports.
+ * - Atomic set/reset/toggle functions because special STM8S instruction set.
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section stm8s_pal_3 Supported PAL setup modes
+ * The STM8S PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section stm8s_pal_4 Suboptimal behavior
+ * The STM8S GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Bus/group writing is not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup STM8S
+ */
+
+/**
+ * @defgroup STM8S_SERIAL STM8S Serial Support
+ * @details The STM8S Serial driver uses the UART peripherals in a
+ *          buffered, interrupt driven, implementation.
+ *
+ * @section stm8s_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - UART1.
+ * - UART2 (where present).
+ * - UART3 (where present).
+ * .
+ * @section stm8s_serial_2 STM8S Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * .
+ * @ingroup STM8S
+ */
+
+/**
+ * @defgroup STM8S_SPI STM8S SPI Support
+ * @details The SPI driver supports the STM8S SPI peripheral in an interrupt
+ *          driven implementation.
+ * @note    Being the SPI a fast peripheral, much care must be taken to
+ *          not saturate the CPU bandwidth with an excessive IRQ rate. The
+ *          maximum transfer bit rate is likely limited by the IRQ
+ *          handling.
+ *
+ * @section stm8s_spi_1 Supported HW resources
+ * - SPI.
+ * .
+ * @section stm8s_spi_2 STM8S SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Fully interrupt driven.
+ * .
+ * @ingroup STM8S
+ */