/* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ #ifndef MCUCONF_H #define MCUCONF_H /* * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. * * DMA priorities: * 0...3 Lowest...Highest. */ #define STM32F4xx_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED FALSE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLM_VALUE 25 #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 4 #define STM32_PLLQ_VALUE 7 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE /* * IRQ system settings. */ #define STM32_IRQ_EXTI0_PRIORITY 6 #define STM32_IRQ_EXTI1_PRIORITY 6 #define STM32_IRQ_EXTI2_PRIORITY 6 #define STM32_IRQ_EXTI3_PRIORITY 6 #define STM32_IRQ_EXTI4_PRIORITY 6 #define STM32_IRQ_EXTI5_9_PRIORITY 6 #define STM32_IRQ_EXTI10_15_PRIORITY 6 #define STM32_IRQ_EXTI16_PRIORITY 6 #define STM32_IRQ_EXTI17_PRIORITY 15 #define STM32_IRQ_EXTI18_PRIORITY 6 #define STM32_IRQ_EXTI19_PRIORITY 6 #define STM32_IRQ_EXTI20_PRIORITY 6 #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 /* * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_IRQ_PRIORITY 6 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * GPT driver system settings. */ #define STM32_GPT_USE_TIM1 FALSE #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM9 FALSE #define STM32_GPT_USE_TIM11 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 #define STM32_GPT_TIM5_IRQ_PRIORITY 7 #define STM32_GPT_TIM9_IRQ_PRIORITY 7 #define STM32_GPT_TIM11_IRQ_PRIORITY 7 /* * I2C driver system settings. */ #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* * I2S driver system settings. */ #define STM32_I2S_USE_SPI2 FALSE #define STM32_I2S_USE_SPI3 FALSE #define STM32_I2S_SPI2_IRQ_PRIORITY 10 #define STM32_I2S_SPI3_IRQ_PRIORITY 10 #define STM32_I2S_SPI2_DMA_PRIORITY 1 #define STM32_I2S_SPI3_DMA_PRIORITY 1 #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ #define STM32
/*
    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/*
 * Buzzer driver for Olimex LPC-P2148.
 * Uses the timer 1 for wave generation and a Virtual Timer for the sound
 * duration.
 * The driver also generates an event when the sound is done and the buzzer
 * goes silent.
 */
#include <ch.h>

#include "lpc214x.h"
#include "board.h"
#include "buzzer.h"

EventSource BuzzerSilentEventSource;

#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1)
#define StopCounter(t)  ((t)->TC_EMR = 0, (t)->TC_TCR = 2)

void InitBuzzer(void) {

  chEvtInit(&BuzzerSilentEventSource);

  /*
   * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions.
   * Enables Timer1 clock.
   */
  PINSEL0 &= 0xF0FFFFFF;
  PINSEL0 |= 0x0A000000;
  PCONP = (PCONP & PCALL) | PCTIM1;

  /*
   * Timer setup.
   */
  TC *tc = T1Base;
  StopCounter(tc);
  tc->TC_CTCR = 0;                      // Clock source is PCLK.
  tc->TC_PR   = 0;                        // Prescaler disabled.
  tc->TC_MCR  = 2;                       // Clear TC on match MR0.
}

static void stop(void *p) {
  TC *tc = T1Base;

  StopCounter(tc);
  chEvtSendI(&BuzzerSilentEventSource);
}

void PlaySound(int freq, systime_t duration) {
  static VirtualTimer bvt;
  TC *tc = T1Base;

  chSysLock();

  if (chVTIsArmedI(&bvt)) {              // If a sound is already being played
    chVTResetI(&bvt);                   // then aborts it.
    StopCounter(tc);
  }

  tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
  StartCounter(tc);
  chVTSetI(&bvt, duration, stop, NULL);

  chSysUnlock();
}

void PlaySoundWait(int freq, systime_t duration) {
  TC *tc = T1Base;

  StopCounter(tc);
  tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
  StartCounter(tc);
  chThdSleep(duration);
  StopCounter(tc);
}
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